CN105632930A - FinFET device and manufacturing method thereof - Google Patents
FinFET device and manufacturing method thereof Download PDFInfo
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- CN105632930A CN105632930A CN201410612974.5A CN201410612974A CN105632930A CN 105632930 A CN105632930 A CN 105632930A CN 201410612974 A CN201410612974 A CN 201410612974A CN 105632930 A CN105632930 A CN 105632930A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000002955 isolation Methods 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 15
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 230000008719 thickening Effects 0.000 abstract description 2
- 230000001681 protective effect Effects 0.000 abstract 3
- 239000004065 semiconductor Substances 0.000 description 16
- 230000008569 process Effects 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- 238000003475 lamination Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000001894 space-charge-limited current method Methods 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004143 HfON Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004166 TaN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention provides an FinFET device and a manufacturing method thereof. The manufacturing method comprises the steps of a. providing a substrate on which a fin is disposed; b. forming shallow trench isolation on the substrate and at two sides of the fin; c. forming a protective mask at the two sides of the fin; d. thinning the shallow trench isolation to expose the fin partially; e. forming an isolation oxide layer on the fin that is not covered by the shallow trench isolation and the protective mask; f. removing the protective mask, and thickening the shallow trench isolation so as to be level with the isolation oxide layer; and g. forming a source and drain region, a gate structure and an interlayer dielectric layer in sequence on the thickened shallow trench isolation. According to the invention, the method of forming the oxide isolation layer in a region below a device trench allows a bulk silicon device have similar performance to an SOI device, and the punch-through current can be effectively suppressed without affecting other parameters of the device.
Description
Technical field
The present invention relates to a kind of method, semi-conductor device manufacturing method, in particular it relates to a kind of FinFET manufacture method.
Technical background
Along with the dimensions scale downward of semiconductor device, occur in that the problem that threshold voltage declines with channel length reduction, that is, create short-channel effect in the semiconductor device. Relate to the challenge with manufacture view in order to tackle from quasiconductor, result in FinFET, be i.e. the development of FinFET.
A kind of phenomenon being connected with the depletion region of drain junction is tied in the source that channel punchthrough effect (Channelpunch-througheffect) is field-effect transistor. Work as channel punchthrough, just make the potential barrier between source/drain significantly reduce, then namely inject a large amount of carrier from source toward raceway groove, and drift about by the space-charge region between source-leakage, form one very big electric current; The size of this electric current is subjected to the restriction of space charge, is so-called space charge limited current. This space charge limited current is that the channel current controlled with grid voltage is in parallel, and therefore channel punchthrough will make the total current by device be greatly increased; And in channel punchthrough situation, even if gate voltage is lower than threshold voltage, also has electric current between source-leakage and pass through. This effect is a kind of effect being likely to occur in small size field-effect transistor, and along with the further reduction of channel width, it is also more and more significant on the impact of device property.
In body silicon device, generally adopt and the fin portion below raceway groove is carried out heavy doping to suppress channel punchthrough effect. Doping method general at present is that ion implanting forms required heavily doped region, but, the degree of depth of ion implanting is difficult to accurate control; channel surface can be caused damage simultaneously; in order to eliminate damage, it will usually form one layer of thin oxide layer in channel surface, add process complexity. Meanwhile, the distribution of impurity is difficult to control to, and is difficult to form super steep retrograde well in trench bottom accurately, but can introduce impurity and defect in channels, affects the Sub-Threshold Characteristic of device. Therefore, need badly and existing technique is improved, solve this problem.
Summary of the invention
It is desirable to provide a kind of FinFET and manufacture method thereof, it is possible to effectively suppress punchthrough current, do not affect other parameters of device simultaneously.
The invention provides a kind of FinFET manufacture method, including:
A., substrate is provided, it has fin;
B. on the substrate of described fin both sides, form shallow trench isolation;
C. protection mask is formed in described fin both sides;
D. the isolation of described shallow trench is carried out thinning, spill part fin;
E. on the fin do not isolated by shallow trench and protect mask to cover, form isolating oxide layer;
F. remove protection mask, the isolation of described shallow trench is thickeied so that it is concordant with isolating oxide layer;
G. in the shallow trench isolation thickeied, source-drain area, grid structure and interlayer dielectric layer are sequentially formed.
Wherein, in step c, the material of described protection mask is silicon nitride and/or silicon oxide; In step d, the isolation of described shallow trench is carried out thinning method is anisotropic rie; It is 10��40nm that described shallow trench isolates thinning thickness; In step e, the method forming isolating oxide layer is dry-oxygen oxidation; The method that the isolation of described shallow trench is thickeied is plasma deposition.
Accordingly, present invention also offers a kind of FinFET, including:
Substrate;
Fin, is positioned at described types of flexure;
Shallow trench is isolated, and is positioned on the substrate of described fin both sides;
Isolating oxide layer, is arranged in described fin, and its top is concordant with shallow trench isolation;
Grid structure, is positioned at described first shallow trench isolation top, wraps up described fin;
Source-drain area, lays respectively at the fin two ends of gate stack both sides.
Wherein, the thickness of described isolating oxide layer is 10��40nm.
FinFET provided by the invention, on the basis of existing bulk silicon technological, fin regions below device channel forms oxidization isolation layer, it is possible to effectively reduce the carrier concentration in the more weak region of the grid-control of device, there is the performance similar with SOI device. Compared with prior art, the present invention can not only well suppress punchthrough current, drastically increases device performance simultaneously, and does not increase process complexity.
Accompanying drawing explanation
Fig. 1 and Fig. 9 schematically shows the three-dimensional equiangular figure forming each stage semiconductor structure of method according to the manufacture semiconductor fin of the present invention.
Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 schematically show the profile forming each stage semiconductor structure of method according to the manufacture semiconductor fin of the present invention.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, embodiments of the invention are described in detail.
Being described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of same or like function from start to finish. The embodiment described below with reference to accompanying drawing is illustrative of, and is only used for explaining the present invention, and is not construed as limiting the claims.
The invention provides a kind of FinFET, including: substrate 100; Fin 200, is positioned at above described substrate 100; Shallow trench isolation 300, is positioned on the substrate 100 of described fin 200 both sides; Isolating oxide layer 400, is arranged in described fin 200, and it is concordant that its top isolates 300 with shallow trench; Grid structure 600, is positioned at above described first shallow trench isolation 300, wraps up described fin 200; Source-drain area, lays respectively at fin 200 two ends of gate stack 600 both sides. Wherein, the thickness of described isolating oxide layer 400 is 10��40nm.
Channel punchthrough current is to tie due to the source of field-effect transistor to be connected with the depletion region of drain junction and produce, and studies carefully its source, be due to raceway groove below region grid-control ability very weak, it is impossible to the carrier in this region is produced effectively control, forms bigger leakage current. Therefore, the present invention from this starting point, on the basis of existing bulk silicon technological, forms oxidization isolation layer in the fin regions below device channel, can effectively reduce the carrier concentration in the more weak region of the grid-control of device, make device have the performance similar with SOI device. Compared with prior art, the present invention can not only well suppress punchthrough current, drastically increases device performance simultaneously, and does not increase process complexity.
Accordingly, present invention also offers a kind of FinFET manufacture method, including:
A., substrate 100 and fin 200 are provided;
B. on the substrate 100 of described fin 200 both sides, form shallow trench isolation 300;
C. protection mask 220 is formed in described fin 200 both sides;
D. described shallow trench isolation 300 is carried out thinning, spill part fin 200;
E. on the fin not covered by shallow trench isolation 300 and protection mask 220, isolating oxide layer 400 is formed;
F. remove protection mask 220, described shallow trench is isolated 300 and thickeies so that it is be concordant with isolating oxide layer 400;
G. on described semiconductor structure, sequentially form source-drain area, grid structure 600 and interlayer dielectric layer 500.
Wherein, in step c, the material of described protection mask 220 is silicon nitride and/or silicon oxide; In step d, described shallow trench isolation 300 is carried out thinning method is anisotropic rie; It is 10��40nm that described shallow trench isolates 300 thinning thickness; In step e, the method forming isolating oxide layer 400 is dry-oxygen oxidation; It is plasma deposition that described shallow trench is isolated 300 methods thickeied.
It is more fully described the invention of this reality hereinafter with reference to accompanying drawing. In various figures, identical element adopts similar accompanying drawing labelling to represent. For the sake of clarity, the various piece in accompanying drawing is not necessarily to scale.
It is to be understood that, when the structure of outlines device, when one layer, one region is called be positioned at another layer, another region " above " or when " top ", can refer to be located immediately at above another layer, another region, or itself and another layer, also comprise other layer or region between another region. Further, if overturn by device, this layer, one region will be located in another layer, another region " below " or " lower section ".
If being located immediately at another layer, another region above scenario to describe, herein will adopt " directly exist ... above " or " ... adjoin above and with it " form of presentation.
Describe hereinafter the many specific details of the present invention, for instance the structure of device, material, size, process technique and technology, in order to be more clearly understood that the present invention. But just as the skilled person will understand, it is possible to do not realize the present invention according to these specific details. Such as, the semi-conducting material of substrate and fin can be selected from IV race quasiconductor, such as Si or Ge, or Group III-V semiconductor, such as GaAs, InP, GaN, SiC, or the lamination of above-mentioned semi-conducting material.
Referring to Fig. 1, use the first substrate 100 in the present invention. Described first backing material is semi-conducting material, it is possible to be silicon, germanium, GaAs etc., it is preferred that in the present embodiment, and substrate used is silicon substrate.
It follows that through projection, exposure, development, described substrate is performed etching by the common process such as etching, forming fin 200, described lithographic method can be dry etching or dry/wet etching. As in figure 2 it is shown, after fin 200 has etched, the mask plate 210 as hard mask wouldn't be removed, it is simple to reusable in subsequent technique.
It follows that described semiconductor structure is carried out shallow trench isolation, to form fleet plough groove isolation structure 300, as shown in Figure 3. Preferably, in semiconductor fin 200, silicon nitride and buffering silicon dioxide pattern are first become, as the mask of trench etching. Next on substrate, the groove with certain depth and sidewall angle is eroded away. Then growth a thin layer silicon dioxide, with the drift angle of round and smooth groove and remove in etching process silicon face introduce damage. Carrying out trench fill after oxidation, filled media can be silicon dioxide. Next using CMP that semiconductor substrate surface is planarized, silicon nitride is as the barrier layer of CMP. Afterwards, with silicon nitride for mask, semicon-ductor structure surface being performed etching, in order to avoid introducing longitudinal diffusion in subsequent technique during diffusion in fin 200, described etching depth is more than actually required fin height, it is possible to be 20��60nm. After having etched, form fleet plough groove isolation structure 300, its distance from top fin 200 top 20��60nm. The phosphoric acid finally using heat takes out the silicon nitride exposed, and exposes fin 200.
It follows that form protection mask 210 at described fleet plough groove isolation structure 300 and fin 200 surface. The material of described protection mask 210 can be silicon oxide and/or silicon nitride. The fin protecting this part when its role is to be formed oxidization isolation layer in subsequent process is not oxidized. In order to make protection mask 210 have reasonable step coverage; the mode of using plasma deposit herein; isolate 300 surfaces at described fin 200 and shallow trench and deposit layer of silicon dioxide uniformly; its thickness is 6��20nm; identical with the thickness of hard mask 210; in the present embodiment, the thickness of described protection mask 210 is 10nm, as shown in Figure 4.
It follows that described oxide layer to be carried out anisortopicpiston reactive ion etching, remove the oxide layer of horizontal direction, form protection mask 210 in fin both sides, as shown in Figure 5.
It follows that carry out thinning to described shallow trench isolation 300, spill part fin 200, as shown in Figure 6. Not damaging other structures in order to ensure while isolating 300 at thinning shallow trench, thining method adopts anisortopicpiston reactive ion etching. Shallow trench isolates the height that 300 thinning thickness are in subsequent technique isolating oxide layer 400, and this thickness can be 10��40nm, determines with specific reference to device architecture.
It follows that form isolating oxide layer 400 on the fin not covered by shallow trench isolation 300 and protection mask 220. The method forming isolating oxide layer 400 is dry-oxygen oxidation, and owing to the silicon dioxide volume of dry-oxygen oxidation generation is more than the silicon before oxidation, after therefore having aoxidized, the thickness of isolating oxide layer 400 is more than the thickness of fin 200, as shown in Figure 7.
It follows that remove protection mask 220, described shallow trench is isolated 300 and thickeies so that it is be concordant with isolating oxide layer 400, as shown in Figure 8. Concrete thickening method is identical with the method above forming shallow trench isolation 300, does not repeat them here.
It follows that be formed over grid structure 600 at raceway groove, grid structure 600 includes gate dielectric layer, work function regulating course and gate metal layer, as shown in Figure 9. Concrete, described gate dielectric layer can be thermal oxide layer, including silicon oxide, silicon oxynitride; It is alternatively high K dielectric, for instance HfAlON, HfSiAlON, HfTaAlON, HfTiAlON, HfON, HfSiON, HfTaON, HfTiON, Al2O3��La2O3��ZrO2, one in LaAlO or its combination, the thickness of gate dielectric layer can be 1nm-10nm, for instance 3nm, 5nm or 8nm. Described work function regulating course can adopt the materials such as TiN, TaN to make, and its thickness range is 3nm��15nm. Described gate metal layer can be one layer or multiple structure. Its material can be TaN, TaC, TiN, TaAlN, TiAlN, MoAlN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax��NiTaxIn one or its combination. Its thickness range can be such as 10nm-40nm, such as 20nm or 30nm. Pseudo-gate stack, and form source-drain area. Dummy gate lamination can be monolayer, it is also possible to be multilamellar. Pseudo-gate stack can include polymeric material, non-crystalline silicon, polysilicon or TiN, and thickness can be 10-100nm. The techniques such as thermal oxide, chemical vapour deposition (CVD) CVD, ald ALD can be adopted to form pseudo-gate stack. Described source-drain area forming method can be that then ion implanting anneals active ions, original position doped epitaxial and/or combination.
Alternatively, the sidewall of gate stack forms side wall, for being separated by grid. Side wall can by silicon nitride, silicon oxide, silicon oxynitride, carborundum and combination thereof, and/or other suitable materials are formed. Side wall can have multiple structure. Side wall can pass through to include deposition-etch technique and be formed, and its thickness range can be 10nm-100nm, such as 30nm, 50nm or 80nm.
It follows that form source-drain area on the fin of gate stack 600 both sides. Concrete, the method for the ion implanting by tilting, form required Impurity Distribution at fin 200 two ends. According to type of device, the foreign particle of injection can be AsN type device or BP type device etc.
It follows that deposit interlayer dielectric layer 500, and parallel flat, expose pseudo-gate stack. Concrete, interlayer dielectric layer 500 can pass through CVD, high-density plasma CVD, spin coating or other suitable methods and be formed. The material of interlayer dielectric layer 500 can adopt and include SiO2, carbon doping SiO2, BPSG, PSG, UGS, silicon oxynitride, low-k materials or its combination. The thickness range of interlayer dielectric layer 500 can be 40nm-150nm, such as 80nm, 100nm or 120nm. Process it follows that perform planarization, make pseudo-gate stack come out, and flush the term " flushing " in the present invention with interlayer dielectric layer 500 and refer to difference in height between the two in the scope that fabrication error allows.
What adopt in the present embodiment is first grid technique, but the understanding that those of skill in the art can will be apparent from, the method forming break-through barrier layer in the present invention can be equally used for first grid technique, and detailed process does not repeat them here.
FinFET provided by the invention, on the basis of existing bulk silicon technological, fin regions below device channel forms oxidization isolation layer, it is possible to effectively reduce the carrier concentration in the more weak region of the grid-control of device, there is the performance similar with SOI device. Compared with prior art, the present invention can not only well suppress punchthrough current, drastically increases device performance simultaneously, and does not increase process complexity.
Although being described in detail about example embodiment and advantage thereof, it should be understood that when the protection domain that spirit and the claims without departing from the present invention limit, it is possible to these embodiments are carried out various change, substitutions and modifications. For other examples, those of ordinary skill in the art is it should be readily appreciated that while keeping in scope, the order of processing step can change.
Additionally, the range of application of the present invention is not limited to the technique of the specific embodiment described in description, mechanism, manufacture, material composition, means, method and step. From the disclosure, will readily appreciate that as those of ordinary skill in the art, for having existed or be about to technique, mechanism, manufacture, material composition, means, method or the step developed at present later, wherein they perform the result that the function that is substantially the same of corresponding embodiment or acquisition with present invention description are substantially the same, and can they be applied according to the present invention. Therefore, claims of the present invention are intended to be included in its protection domain these technique, mechanism, manufacture, material composition, means, method or step.
Claims (8)
1. a FinFET manufacture method, including:
A., substrate (100) is provided, substrate (100) has fin (200);
B. (300) are isolated at the upper shallow trench that formed of the substrate (100) of described fin (200) both sides;
C. protection mask (220) is formed in described fin (200) both sides;
D. described shallow trench is isolated (300) and carry out thinning, spill the part of fin (200);
E. on the fin not covered by shallow trench isolation (300) and protection mask (220), isolating oxide layer (400) is formed;
F. remove protection mask (220), described shallow trench is isolated (300) and thickeies so that it is be concordant with isolating oxide layer (400);
G. on shallow trench isolation (300) thickeied, source-drain area, grid structure (600) and interlayer dielectric layer (500) are sequentially formed.
2. FinFET manufacture method according to claim 1, it is characterised in that in step c, the material of described protection mask (220) is silicon nitride and/or silicon oxide.
3. FinFET manufacture method according to claim 1, it is characterised in that in step d, described shallow trench isolation (300) is carried out thinning method is anisotropic rie.
4. FinFET manufacture method according to claim 1, it is characterised in that in step d, the thickness that described shallow trench isolates (300) thinning is 10��40nm.
5. FinFET manufacture method according to claim 1, it is characterised in that in step e, the method forming isolating oxide layer (400) is dry-oxygen oxidation.
6. FinFET manufacture method according to claim 1, it is characterised in that in step f, the method that described shallow trench isolation (300) is thickeied is plasma deposition.
7. a FinFET, including:
Substrate (100);
Fin (200), is positioned at described substrate (100) top;
Shallow trench isolation (300), is positioned on the substrate (100) of described fin (200) both sides;
Isolating oxide layer (400), is arranged in described fin (200), and it is concordant that its top isolates (300) with shallow trench;
Grid structure (600), is positioned at described first shallow trench isolation (300) top, wraps up described fin (200);
Source-drain area, lays respectively at fin (200) two ends of gate stack (600) both sides.
8. FinFET according to claim 7, it is characterised in that the thickness of described isolating oxide layer (400) is 10��40nm.
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| CN201410612974.5A CN105632930A (en) | 2014-11-04 | 2014-11-04 | FinFET device and manufacturing method thereof |
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| CN201410612974.5A CN105632930A (en) | 2014-11-04 | 2014-11-04 | FinFET device and manufacturing method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087861A (en) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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