CN115084134A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN115084134A
CN115084134A CN202110282878.9A CN202110282878A CN115084134A CN 115084134 A CN115084134 A CN 115084134A CN 202110282878 A CN202110282878 A CN 202110282878A CN 115084134 A CN115084134 A CN 115084134A
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fin
layer
substrate
forming
work function
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A structure of a semiconductor and a forming method thereof are provided, the structure of the semiconductor comprises: the transistor comprises a substrate, a first transistor body and a second transistor body, wherein the substrate comprises a first device area and a second device area which are adjacent, the first device area is used for forming a first type transistor, and the second device area is used for forming a second type transistor; the fin parts are respectively raised on the substrate of the first device area and the substrate of the second device area; the dummy fin part is raised on the substrate at the junction of the first device area and the second device area and is spaced from the fin part; the isolation layer is positioned on the substrate with the exposed fin parts and covers the fin parts and partial side walls of the pseudo fin parts; the gate dielectric layer is positioned in the first device area and the second device area and conformally covers the tops and the side walls of the fin part and the pseudo fin part; the first work function layer conformally covers the gate dielectric layer in the first device area; and the second work function layer conformally covers the gate dielectric layer in the second device area. The dummy fin portion reduces the probability of ion interdiffusion between different work function layers in adjacent device regions, thereby improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which are beneficial to further improving the semiconductor performance.
To solve the above problems, the present invention further provides a semiconductor structure, comprising: a substrate including adjacent first and second device regions, the first device region being for forming a first type transistor, the second device region being for forming a second type transistor, the first and second types being different; the fin parts are respectively raised on the substrate of the first device area and the substrate of the second device area; the dummy fin portion is protruded on the substrate at the junction of the first device area and the second device area and is spaced from the fin portion, and the material of the dummy fin portion comprises dielectric material; the isolation layer is positioned on the substrate with the exposed fin parts and covers partial side walls of the fin parts and the pseudo fin parts; the gate dielectric layer is positioned in the first device area and the second device area and conformally covers the tops and the side walls of the fin part and the pseudo fin part; the first work function layer conformally covers the gate dielectric layer in the first device area; and the second work function layer conformally covers the gate dielectric layer in the second device area.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different; in the second device area, removing part of the thickness of the substrate, and forming a groove in the rest of the substrate; forming a dummy fin portion on the side wall of the groove, wherein the dummy fin portion comprises a dielectric material; after the pseudo fin portion is formed, a fin portion material layer is formed in the residual space of the groove; patterning the substrate of the first device region and a fin material layer of the second device region, forming a substrate and a fin portion protruding from the substrate and spaced from the dummy fin portion in the first device region and the second device region, wherein the fin portion of the second device region is formed by the fin material layer; forming an isolation layer on the substrate with the exposed fin parts, wherein the isolation layer covers the fin parts and partial side walls of the pseudo fin parts; forming a gate dielectric layer which conformally covers the tops and the side walls of the fin part and the pseudo fin part on the top of the isolation layer; forming a first work function layer crossing the fin part in the first device region, wherein the first work function layer conformally covers the gate dielectric layer; and forming a second work function layer crossing the fin part in the second device area, wherein the second work function layer conformally covers the gate dielectric layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a method for forming a semiconductor structure, wherein a substrate comprises a first device area and a second device area which are adjacent; in the second device area, removing part of the thickness of the substrate, and forming a groove in the rest of the substrate; forming a dummy fin portion on the side wall of the groove, wherein the dummy fin portion comprises a dielectric material; after the pseudo fin portion is formed, a fin portion material layer is formed in the residual space of the groove; patterning the substrate of the first device region and a fin material layer of the second device region, forming a substrate and a fin portion protruding from the substrate and spaced from the dummy fin portion in the first device region and the second device region, wherein the fin portion of the second device region is formed by the fin material layer; forming an isolation layer on the substrate with the exposed fin parts, wherein the isolation layer covers the fin parts and partial side walls of the pseudo fin parts; forming a gate dielectric layer which conformally covers the tops and the side walls of the fin part and the pseudo fin part on the top of the isolation layer; forming a first work function layer crossing the fin portion in the first device area, wherein the first work function layer conformally covers the gate dielectric layer; and forming a second work function layer crossing the fin part in the second device area, wherein the second work function layer conformally covers the gate dielectric layer. In the embodiment of the invention, before the substrate and the fin portion are formed, the dummy fin portion is formed on the side wall of the groove, that is, the dummy fin portion is formed at the boundary between the first device region and the second device region, the second work function layer located in the second device region is separated from the first work function layer located in the first device region by the dummy fin portion, and the dummy fin portion can prevent easily-diffused ions (for example, easily-diffused metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along the direction parallel to the surface of the substrate, that is, the probability of mutual diffusion of ions between different work function layers in adjacent device regions is reduced, which is beneficial to ensuring the respective performances of the first work function layer and the second work function layer, thereby improving the performance of the semiconductor structure.
The embodiment of the invention provides a semiconductor structure, wherein a pseudo fin part is convexly erected on a substrate at the junction of a first device area and a second device area and is spaced from a fin part, and the pseudo fin part comprises a dielectric material; the isolation layer is positioned on the substrate with the exposed fin part and covers partial side walls of the fin part and the pseudo fin part; the gate dielectric layer is positioned in the first device area and the second device area and conformally covers the tops and the side walls of the fin part and the pseudo fin part; the first work function layer conformally covers the gate dielectric layer in the first device area; and the second work function layer conformally covers the gate dielectric layer in the second device area. In the embodiment of the present invention, the second work function layer located in the second device region is separated from the first work function layer located in the first device region by the dummy fin portion located on the substrate at the boundary between the first device region and the second device region, and the dummy fin portion can block easily-diffused ions (for example, easily-diffused metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along a direction parallel to the substrate surface, that is, the probability of ion interdiffusion between different work function layers in adjacent device regions is reduced, which is beneficial to ensuring the respective performances of the first work function layer and the second work function layer, thereby improving the performance of the semiconductor structure.
Drawings
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 5-7 are schematic structural diagrams illustrating a semiconductor structure according to an embodiment of the present invention;
fig. 8 to 23 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Detailed Description
The performance of semiconductor structures currently needs to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to 4 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, the substrate 10 includes a first device region 10a and a second device region 10b which are adjacent to each other, the first device region 10a is used for forming an NMOS transistor, and the second device region 10b is used for forming a PMOS transistor; forming a mask layer 11 in the first device region 10 a; and removing a part of the thickness of the substrate 10 in the second device region 10b by using the mask layer 11 as a mask, and forming a groove 13 in the rest of the substrate 10.
Referring to fig. 2, a fin material layer 15 is formed in the recess 13.
Referring to fig. 3, patterning the base 10 of the first device region 10a and the fin material layer 15 of the second device region 10b, forming a substrate 17 in the first device region 10a and the second device region 10b, and forming a fin 18 protruding from the substrate 17, wherein the fin 18 of the second device region is formed by the fin material layer 15; and forming an isolation layer 20 on the substrate 17 exposed out of the fin portion 18, wherein the isolation layer 20 covers part of the side wall of the fin portion 18.
Referring to fig. 4, in the second device region 10b, a first work function layer 30 conformally covering the fin 18 and the isolation layer 20 is formed; after the first work function layer 30 is formed, a second work function layer 21 conformally covering the fin 18, the isolation layer 20, and the first work function layer 30 is formed in the first device region 10a and the second device region 10 b.
The first device region 10a is configured to form an NMOS transistor, the second device region 10b is configured to form a PMOS transistor, and in order to enable threshold voltages of the NMOS transistor and the PMOS transistor to respectively reach preset values, the NMOS transistor and the PMOS transistor need to use different work function layers.
However, when the NMOS transistor and the PMOS transistor share a metal gate structure, the second work function layer 21 conformally covers not only the fin 18 of the first device region 10a but also the first work function layer 30, and thus the first work function layer 30 and the second work function layer 21 have an interface at the boundary between the first device region 10a and the second device region 10 b.
Accordingly, the easily-diffused ions (e.g., easily-diffused metal ions) in the first work function layer 30 are easily diffused into the second work function layer 21 in the first device region 10a along a direction parallel to the surface of the substrate 17, and similarly, the easily-diffused ions (e.g., easily-diffused metal ions) in the second work function layer 21 in the first device region 10a are also easily diffused into the first work function layer 30 along a direction parallel to the surface of the substrate 17, so that the probability of ion interdiffusion between different work function layers in adjacent device regions is increased, the respective performances of the first work function layer 21 and the second work function layer 30 are reduced, and the performance of the semiconductor structure is affected.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different; in the second device area, removing part of the thickness of the substrate, and forming a groove in the rest of the substrate; forming a dummy fin portion on the side wall of the groove, wherein the dummy fin portion comprises a dielectric material; after the pseudo fin portion is formed, a fin portion material layer is formed in the residual space of the groove; patterning the substrate of the first device region and a fin material layer of the second device region, and forming a substrate and a fin portion protruding from the substrate and spaced from the dummy fin portion in the first device region and the second device region, wherein the fin portion of the second device region is formed by the fin material layer; forming an isolation layer on the substrate with the exposed fin parts, wherein the isolation layer covers the fin parts and partial side walls of the pseudo fin parts; forming a gate dielectric layer which conformally covers the tops and the side walls of the fin part and the pseudo fin part on the top of the isolation layer; forming a first work function layer crossing the fin portion in the first device area, wherein the first work function layer conformally covers the gate dielectric layer; and forming a second work function layer crossing the fin part in the second device area, wherein the second work function layer conformally covers the gate dielectric layer.
In the embodiment of the invention, before the substrate and the fin portion are formed, the dummy fin portion is formed on the side wall of the groove, that is, the dummy fin portion is formed at the boundary between the first device region and the second device region, the second work function layer located in the second device region is separated from the first work function layer located in the first device region by the dummy fin portion, and the dummy fin portion can prevent easily-diffused ions (for example, easily-diffused metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along the direction parallel to the surface of the substrate, that is, the probability of mutual diffusion of ions between different work function layers in adjacent device regions is reduced, which is beneficial to ensuring the respective performances of the first work function layer and the second work function layer, thereby improving the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 7 are schematic structural diagrams of a semiconductor structure according to an embodiment of the invention.
The semiconductor structure includes: a substrate 208 including a first device region 200a and a second device region 200b adjacent to each other, the first device region 200a being used for forming a first type transistor, the second device region 200b being used for forming a second type transistor, the first type and the second type being different; a fin 209 protruding from the substrate 208 in the first device region 200a and the second device region 200b, respectively; a dummy fin 204 protruding from the substrate 208 at the interface between the first device region 200a and the second device region 200b and spaced apart from the fin 209, the dummy fin 209 comprising a dielectric material; an isolation layer 212, located on the substrate 208 where the fin portion 209 is exposed, where the isolation layer 212 covers the fin portion 209 and a portion of sidewalls of the dummy fin portion 204; a gate dielectric layer 213, located in the first device region 200a and the second device region 200b, and conformally covering the tops and sidewalls of the fin 209 and the dummy fin 204; a first work function layer 215 conformally covering the gate dielectric layer 213 in the first device region 200 a; and a second work function layer 214 conformally covering the gate dielectric layer 213 in the second device region 200 b.
In this embodiment, the dummy fin 204 on the substrate 208 at the boundary between the first device region 200a and the second device region 200b separates the second work function layer 214 in the second device region 200b from the first work function layer 215 in the first device region 200a, and the dummy fin 204 can block easily-diffusible ions (e.g., easily-diffusible metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along a direction parallel to the surface of the substrate 208, that is, the probability of ion mutual diffusion between different work function layers in adjacent device regions is reduced, which is beneficial to ensuring the respective performances of the first work function layer 215 and the second work function layer 214, thereby improving the performance of the semiconductor structure.
In this embodiment, the first device region 200a is used to form a first type transistor, the second device region 200b is used to form a second type transistor, and the first type and the second type are different. Specifically, the first type and the second type are different and refer to: the first type and the second type have different conductivity types. In this embodiment, the first type is N-type, and the second type is P-type. Namely, the first device region 100a is an NMOS device region, and the first type transistor is an NMOS transistor; the second device area 100b is a PMOS device area, and the second-type transistor is a PMOS transistor.
In other embodiments, the first type is P-type and the second type is N-type.
In other embodiments, the following may be also possible: the first type transistor and the second type transistor are both NMOS transistors or both PMOS transistors, but the threshold voltages of the first type transistor and the second type transistor are different, so that work function layers of different stack structures, materials or thicknesses are required to adjust the respective threshold voltages.
In this embodiment, the first device region 200a and the second device region 200b are adjacent regions.
In this embodiment, the substrate 208 of the second device region 200b includes a bottom substrate 220 and a top substrate 211 located on the bottom substrate 220, the material of the bottom substrate 220 is the same as the substrate material of the first device region 200a, and the material of the top substrate 211 is the same as the material of the fin 209 of the second device region 200 b.
In this embodiment, the material of the substrate 208 in the first device region 200a is silicon.
The first type and the second type have different conductive types, so that the first type transistor and the second type transistor have different materials of the corresponding fin parts. As an example, in the forming process of the semiconductor structure, a part of the thickness of the substrate in the second device region 200b is usually removed, after a groove is formed in the substrate, a fin material layer is re-grown in the groove, then the substrate of the first device region 200a and the fin material layer of the second device region 200b are patterned, a substrate 208 and a fin 209 protruding from the substrate 208 are formed in the first device region 200a and the second device region 200b, and the fin 209 of the second device region 200b is formed by the fin material layer.
Therefore, in this embodiment, the substrate 208 of the second device region 200b includes a bottom substrate 220 and a top substrate 211 located on the bottom substrate 220, the bottom substrate 220 is made of the same material as the substrate 208 of the first device region 200a, and the top substrate 211 is made of the same material as the fin 209 of the second device region 200 b. Wherein the top substrate 211 is also formed by the fin material layer.
Specifically, the bottom substrate 220 and the substrate 208 of the first device region 200a are of an integral structure, and the top substrate 211 and the fin portion 209 of the second device region 200b are of an integral structure.
Therefore, in this embodiment, the material of the bottom substrate 220 in the second device region 200b is silicon.
In this embodiment, the fin 209 is respectively protruded from the substrate 208 of the first device region 200a and the second device region 200 b.
In the present embodiment, the material of the fin 209 may comprise silicon, silicon germanium, or a group iii-v semiconductor material, depending on the type and performance requirements of the transistor.
In this embodiment, the fin 209 in the first device region 200a and the second device region 200b are made of different materials to meet the performance requirements of different types of transistors.
As an example, the first transistor is an NMOS transistor, and the second transistor is a PMOS transistor, so the material of the fin 209 of the first device region 200a is silicon, and the material of the fin 209 of the second device region 200b is silicon germanium
The silicon germanium is used as the material of the fin portion 209 of the second device region 200b, which can improve the transfer rate of carriers in the fin portion 209, thereby improving the electrical performance of the PMOS transistor.
In this embodiment, the dummy fin 204 protrudes from the substrate 208 at the boundary between the first device region 200a and the second device region 200b and is spaced apart from the fin 209, and the dummy fin 204 includes a dielectric material.
The second work function layer 214 located in the second device region 200b is separated from the first work function layer 215 located in the first device region 200a by the dummy fin portion 204 located on the substrate 208 at the boundary between the first device region 200a and the second device region 200b, and the dummy fin portion 204 can block easily-diffused ions (for example, easily-diffused metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along the direction parallel to the substrate surface, that is, the probability of ion interdiffusion between different work function layers in adjacent device regions is reduced, which is beneficial to ensuring the respective performances of the first work function layer 215 and the second work function layer 214, thereby improving the performance of the semiconductor structure.
In this embodiment, the direction perpendicular to the extending direction of the fin 209 is taken as a lateral direction, and the lateral dimension of the dummy fin 204 is 3 nm to 10 nm.
It should be noted that the lateral dimension of the dummy fin 204 should not be too large or too small. If the lateral size of the dummy fin portion is too large, it is easy to cause the distance between the dummy fin portion 204 and the adjacent fin portion 209 to be too short, and accordingly, the aspect ratio between the dummy fin portion 204 and the adjacent fin portion 209 is too large, which affects the filling effect of the subsequent work function layer, thereby affecting the performance of the semiconductor structure; if the lateral dimension of the dummy fin 204 is too small, the insulation effect of the dummy fin 204 is poor, and it is not possible to completely block the easy-to-diffuse ions (e.g., easy-to-diffuse metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along the direction parallel to the substrate surface, that is, the probability of the mutual diffusion of ions between different work function layers in adjacent device regions is increased, thereby affecting the performance of the semiconductor structure. Therefore, in the present embodiment, the direction perpendicular to the extending direction of the fin 209 is taken as a lateral direction, and the lateral dimension of the dummy fin 204 is 3 nm to 10 nm. For example, the dummy fins 204 have a lateral dimension of 5 nm or 7 nm.
In this embodiment, the dummy fins 204 are made of a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride.
The dielectric material has an insulating function. That is, the dielectric material can block easily-diffused ions (e.g., easily-diffused metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along a direction parallel to the substrate surface, so that the probability of ion interdiffusion between different work function layers in adjacent device regions is reduced, and the dummy fin 204 has no conductivity so as not to affect the electrical performance of the transistor.
In this embodiment, the top of the dummy fin 204 is higher than or flush with the top of the fin 209.
It should be noted that, in the formation process of the semiconductor structure, a part of the thickness of the substrate in the second device region 200b is usually removed, after a groove is formed in the substrate, before a fin material layer is re-grown in the groove, the dummy fin 204 is formed on the sidewall of the groove, and therefore, the top of the dummy fin 204 is higher than or flush with the top of the fin 209.
Moreover, by making the top of the dummy fin 204 higher than or flush with the top of the fin 209, when the first work function layer 215 also conformally covers the dummy fin 204 and the second work function layer 214 in the second device region 200b, the diffusion path of the easily-diffused ions in the second work function layer 214 into the first device region 200a via the sidewall and the top of the dummy fin 204 becomes longer, thereby further reducing the probability of the easily-diffused ions in the second work function layer 214 diffusing into the first work function layer 215 in the first device region 200 a. Meanwhile, the probability of interconnection between the first source-drain doping layer 217 and the second source-drain doping layer 219 in the epitaxial growth process is further reduced, and the performance of the semiconductor structure is improved.
In this embodiment, the bottom of the dummy fin 204 also extends into the substrate 208, and the bottom of the dummy fin 204 is flush with the bottom of the top substrate 211.
As can be seen from the above description, in the formation process of the semiconductor structure, a part of the thickness of the substrate in the second device region 200b is usually removed, and after forming a groove in the substrate, a fin material layer is re-grown in the groove; before the fin material layer is re-grown in the groove, the dummy fins 204 are formed on the sidewalls of the groove, so that the bottom of the dummy fins 204 also extends into the substrate 208, and the bottom of the dummy fins 204 is flush with the bottom of the top substrate 211.
It should be noted that after the fin material layer is regrown in the groove, well region ion implantation is also performed on the fin material layer before patterning the substrate of the first device region and the fin material layer of the second device region. In the well region ion implantation process, the dummy fin portion 204 can block ions implanted into the second device region 200b from diffusing into the first device region 200a, and confine the ions in the second device region 200 b.
Accordingly, in the present embodiment, the fin portion 209 of the second device region 200b has a well region therein. Specifically, the second transistor is a PMOS transistor, and thus, the well region of the second device region 200b has N-type ions.
In this embodiment, the isolation layer 212 is located on the substrate 208 where the fin portion 209 is exposed, and the isolation layer 212 covers the fin portion 209 and a portion of the sidewall of the dummy fin portion 204.
The isolation layer 212 serves to isolate adjacent devices. The material of the isolation layer 212 may include silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 212 is silicon oxide.
In this embodiment, the gate dielectric layer 213 is located in the first device region 200a and the second device region 200b and conformally covers the top and sidewalls of the fin 209 and the dummy fin 204. The first work function layer 215 and the second work function layer 214 respectively cover the gate dielectric layer 213.
The material of the gate dielectric layer 213 comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a). In this embodiment, the material of the gate dielectric layer 213 includes a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
In this embodiment, the first work function layer 215 conformally covers the gate dielectric layer 213 in the first device region 200 a.
The first work function layer 215 is used to adjust the threshold voltage of the first type transistor. In this embodiment, the material of the first work function layer 215 includes one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN, and TiAlC. The specific material and film structure of the first work function layer 215 depend on the performance of the first type transistor.
Specifically, the first type transistor is an NMOS transistor, the first work function layer 115 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. In other embodiments, when the first type transistor is a PMOS transistor, the second work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN.
In this embodiment, the first work function layer 215 further conformally covers the gate dielectric layer 213 on the dummy fin 204 and the second work function layer 214.
In the formation of the semiconductor structure, the first work function layer is formed in the first device region, typically after the second work function layer is formed in the second device region.
It should be noted that the first work function layer 215 can meet the process requirement for adjusting the threshold voltage of the first type transistor, the second work function layer 214 can meet the process requirement for adjusting the threshold voltage of the second type transistor, and the first work function layer 215 is usually formed in the second device region 200b during the process of forming the first work function layer 215, and in order to reduce the process steps and the process cost, the step of patterning the first work function layer 215 is omitted, so that the first work function layer 215 also conformally covers the dummy fin portion 204 and the second work function layer 214 in the second device region 200 b.
It should be further noted that the second work function layer 214 can meet the process requirement for adjusting the threshold voltage of the second type transistor, and the dummy fin 204 separates the second work function layer 214 located in the second device region 200b from the first work function layer 215 located in the first device region 200a, so that even if the first work function layer 215 further conformally covers the dummy fin 204 and the second work function layer 214 located in the second device region 200b, the probability of ion interdiffusion between different work function layers in adjacent device regions can be still reduced, which is beneficial to ensuring the respective performances of the first work function layer 215 and the second work function layer 214, thereby improving the performance of the semiconductor structure.
In this embodiment, the second work function layer 214 conformally covers the gate dielectric layer 213 in the second device region 200 b.
The second work function layer 214 is used to adjust the threshold voltage of the second type transistor. In this embodiment, the material of the second work function layer 214 includes one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN, and TiAlC. The specific material and film structure of the second work function layer 214 depend on the performance of the first type transistor.
Specifically, the second type transistor is a PMOS transistor, the second work function layer 214 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. In other embodiments, when the second type transistor is an NMOS transistor, the second work function layer 214 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.
In this embodiment, the semiconductor structure further includes: a gate layer 216 located in the first device region 200a and the second device region 200b and covering the first work function layer 215, the second work function layer 214 and the dummy fin 209.
The gate layer 216 is used for subsequent electrical connection to external structures. The material of the gate layer 216 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. In this embodiment, the material of the gate layer 216 includes W.
In this embodiment, the gate layer 216 is shared by the first device region 200a and the second device region 200 b.
Referring to fig. 6-7 in combination, fig. 6 is a top view of the gate layer 216, the fin 209, and the dummy fin 204 of fig. 5, and fig. 7 is a cross-sectional view taken along the CD of fig. 6.
In this embodiment, the fin 209 includes a channel region 330 along the extension direction of the fin 209.
Specifically, the region of the fin 209 covered by the gate layer 216 is a channel region.
As shown in fig. 7, in this embodiment, the semiconductor structure further includes: the first source-drain doping layer 217 is located in the first device region 200a and located in the fin portion 209 on two sides of the channel region 330; and the second source-drain doping layer 219 is located in the second device region 200b, located in the fin portion 209 on two sides of the channel region 330, and isolated by the dummy fin portion 204 between the first source-drain doping layer 217 and the second source-drain doping layer 219 which are adjacent to each other.
The first source-drain doping layer 217 serves as a source region or a drain region of the first device region 200a, and when the semiconductor structure works, the first source-drain doping layer 217 provides stress for the channel region, so that the mobility of carriers is improved.
The second source-drain doping layer 219 serves as a source region or a drain region of the second device region 200b, and when the semiconductor structure works, the second source-drain doping layer 219 provides stress for the channel region, so that the mobility of carriers is improved.
In this embodiment, the first device region 200a is an NMOS transistor, and the first source-drain doping layer 217 is an epitaxial layer doped with N-type ions. The N-type ions are P ions, As ions or Sb ions. N-type ions are doped in the epitaxial layer to replace the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. As an example, the epitaxial layer corresponding to the first source-drain doping layer 217 is made of SiP or Si.
In this embodiment, the second device region 200b is used to form a PMOS transistor, and the second source-drain doping layer 219 is an epitaxial layer doped with P-type ions. The P-type ions are B ions, Ga ions or In ions. By doping the P-type ions in the epitaxial layer, the P-type ions replace the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. As an example, the epitaxial layer corresponding to the second source-drain doping layer 219 is made of SiGe.
The first source-drain doping layer 217 and the second source-drain doping layer 219 are formed in an epitaxial growth mode, the first source-drain doping layer 217 and the second source-drain doping layer 219 are isolated by the dummy fin portion 204, the probability that the first source-drain doping layer 217 and the second source-drain doping layer 219 are connected with each other in the epitaxial growth process is reduced, and the performance of the semiconductor structure is improved.
With continued reference to fig. 7, the semiconductor structure further includes: and the interlayer dielectric layer 218 is positioned in the first device region 200a and the second device region 200b and covers the first source-drain doping layer 217, the second source-drain doping layer 219, the dummy fin portion 204 and the isolation layer 212.
The interlevel dielectric layer 218 is used to isolate adjacent devices. The material of the interlayer dielectric layer 218 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 218 is made of silicon oxide.
Fig. 8 to 23 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 8, a substrate 100 is provided, the substrate 100 includes a first device region 100a and a second device region 100b adjacent to each other, the first device region 100a is used for forming a first type transistor, the second device region 100b is used for forming a second type transistor, and the first type and the second type are different.
The substrate 100 is used to provide a process platform for subsequent process steps.
In the present embodiment, the substrate 100 is used to form a fin field effect transistor (FinFET).
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be silicon carbide, gallium arsenide, or indium gallium arsenide.
In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 100 includes a first device region 100a and a second device region 100b, the first device region 100a is used to form a first type transistor, the second device region 100b is used to form a second type transistor, and the first type and the second type are different. Specifically, the first type and the second type are different and refer to: the first type and the second type have different conductivity types. In this embodiment, the first type is N-type, and the second type is P-type. Namely, the first device region 100a is an NMOS device region, and the first type transistor is an NMOS transistor; the second device area 100b is a PMOS device area, and the second-type transistor is a PMOS transistor.
In other embodiments, the first type is P-type and the second type is N-type.
In this embodiment, the first device region 100a and the second device region 100b are adjacent regions.
Referring to fig. 8 to 9, in the second device region 100b, a portion of the thickness of the substrate 100 is removed, and a groove 103 is formed in the remaining substrate 100.
The recesses 103 provide spatial locations for subsequent formation of dummy fins and fin material layers.
In this embodiment, the step of forming the groove 103 includes: forming a first mask layer 101 with a mask opening 102 on the top of the substrate 100, wherein the first mask layer 101 is located in the first device area 100a, and the mask opening 102 is located in the second device area 100 b; and etching the substrate 100 with a partial thickness of the second device region 100b along the mask opening 102 by using the first mask layer 101 as a mask, and forming a groove 103 in the second device region 100 b.
The first mask layer 101 provides a process basis for forming a groove in the substrate 100 of the second device region 100 b.
In this embodiment, the process of forming the recess 103 in the second device region 100b includes a dry etching process.
It should be noted that the dry etching process includes an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, and quite accurate pattern conversion can be obtained, so that the precise control of the morphology of the side wall of the groove 103 is facilitated.
Referring to fig. 10, dummy fins 104 are formed on sidewalls of the recess 103, and the dummy fins 104 comprise a dielectric material.
In the embodiment, the dummy fin portion 104 is formed on the sidewall of the groove 103 before the substrate and the fin portion are formed in the subsequent step, so that the process for forming the dummy fin portion 104 is simple, the influence of the formation of the dummy fin portion 104 on the subsequent fin portion is reduced, and the process compatibility is high.
Moreover, by forming the dummy fin 104 on the sidewall of the groove 103, that is, forming the dummy fin 104 at the boundary between the first device region 100a and the second device region 100b, the dummy fin 104 separates the second work function layer formed subsequently in the second device region 100b from the first work function layer in the first device region 100a, and the dummy fin 104 can prevent the easily-diffused ions (for example, easily-diffused metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along the direction parallel to the substrate surface, that is, the probability of inter-diffusion of ions between different work function layers in adjacent device regions is reduced, which is beneficial to ensuring the respective performances of the first work function layer and the second work function layer, thereby improving the performance of the semiconductor structure.
In this embodiment, the step of forming the dummy fin 104 includes: forming a dummy fin material layer (not shown) on the bottom and sidewalls of the recess 103 and the top of the first mask layer 101; and removing the dummy fin material layer at the bottom of the groove 103 and at the top of the first mask layer 101, wherein the residual dummy fin material layer is used as the dummy fin 104.
In this embodiment, the process of forming the dummy fin material layer includes an atomic layer deposition process.
The ald process includes multiple ald cycles, which is beneficial to improving the thickness uniformity of the dummy fin 104 and enabling the dummy fin 104 to cover the substrate 100 and the sidewalls of the mask layer 101. In other embodiments, the dummy fin material layer may be formed by a Chemical Vapor Deposition (CVD) process.
In this embodiment, the pseudo fin material layer at the bottom of the groove 103 and at the top of the mask layer 101 is removed by using an anisotropic dry etching process.
The anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, and quite accurate pattern conversion can be obtained, so that the dummy fin material layer can be removed conveniently, and meanwhile, the appearance and the dimensional accuracy of the side wall of the dummy fin 104 are guaranteed.
In this embodiment, the arrangement direction of the first device region 100a and the second device region 100b is taken as a lateral direction, and the lateral dimension of the dummy fin 104 is 3 nm to 10 nm.
It should be noted that the lateral dimension of the dummy fin 104 should not be too large or too small. If the lateral size of the dummy fin portion is too large, the dummy fin portion may occupy too much space position of the groove 103, which may affect the process effect of forming a fin portion in the second device region 100b, and may easily cause the distance between the dummy fin portion 104 and the adjacent fin portion 109 to be too short, and accordingly, the aspect ratio between the dummy fin portion 104 and the adjacent fin portion 109 may be too large, which may affect the filling effect of the subsequent work function layer, thereby affecting the performance of the semiconductor structure; if the lateral dimension of the dummy fin 104 is too small, the insulation effect of the dummy fin 104 is poor, and it is not possible to completely block the easy-to-diffuse ions (e.g., easy-to-diffuse metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along the direction parallel to the substrate surface, that is, the probability of ion interdiffusion between different work function layers in adjacent device regions is increased, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the lateral dimension of the dummy fin 104 is 3 nm to 10 nm, taking the arrangement direction of the first device region 100a and the second device region 100b as the lateral direction. For example, the dummy fins 104 have a lateral dimension of 5 nm or 7 nm.
In this embodiment, the dummy fins 104 include a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride.
The dielectric material has an insulating effect. That is, the dielectric material can block easily-diffused ions (e.g., easily-diffused metal ions) in the work function layer of any device region from diffusing into the work function layer of another device region along a direction parallel to the substrate surface, so that the probability of ion interdiffusion between different work function layers in adjacent device regions is reduced, and the dummy fin 104 has no conductivity so as not to affect the electrical performance of the transistor.
Referring to fig. 11, after the dummy fins 104 are formed, a fin material layer 105 is formed in the remaining space of the recess 103.
The fin material layer 105 provides a process foundation for subsequent fin formation in the second device region 100 b.
In this embodiment, in the step of forming the fin material layer 105, the material of the fin material layer 105 is different from that of the substrate 100.
In this embodiment, the first type and the second type have different conductive types, and thus the first type transistor and the second type transistor have different materials of the corresponding fin. I.e., the material of the fin material layer 105 is different from the material of the substrate 100 to meet the performance requirements of different types of transistors.
It is noted that, in the step of forming the fin material layer 105, the material of the fin material layer 105 includes silicon, silicon germanium, germanium or a iii-v semiconductor material according to the type and performance requirements of the second-type transistor. As an example, in the embodiment, the second-type transistor is a PMOS transistor, and thus the material of the fin material layer 105 is silicon germanium.
The silicon germanium is used as a material of the channel of the second type transistor, and can improve the migration rate of 100b carriers of the PMOS transistor, so that the electrical performance of the PMOS transistor is improved.
With continued reference to fig. 11, after forming the fin material layer 105, before subsequently forming a substrate and a fin protruding from the substrate, further comprising: well region ion implantation is performed on the fin material layer 105.
By performing well region ion implantation, a well region is formed in the fin material layer 105, and accordingly, a fin portion subsequently formed in the second device region 100b has a well region therein.
It should be noted that, before the fin portion material layer 105 is patterned in the subsequent step to form a fin portion, the top surfaces of the substrate 100 and the fin portion material layer 105 are relatively flat, so that in the process of performing the well region ion implantation, implanted ions are distributed uniformly in the fin portion material layer 105, and the doping depths are consistent, thereby improving the performance of the semiconductor structure; moreover, if well region ion implantation is performed after the fin portion is subsequently formed, the fin portion is easily damaged by the well region ion implantation process, and thus the performance of the semiconductor structure is affected.
In this embodiment, when the second transistor is a PMOS transistor, the implanted ion type is N-type in the process of performing well region ion implantation on the fin material layer 105. In other embodiments, when the second transistor is an NMOS transistor, the implanted ion type is P-type during the well ion implantation process of the fin material layer 105.
It should be noted that, in the process of performing well region ion implantation on the fin material layer 105, the dummy fin 104 can block implanted ions from diffusing into the first device region 100a, and confine the ions in the second device region 100b, so as to achieve isolation between well regions of the first device region 100a and the second device region 100 b.
It should be further noted that, in the process of performing well region ion implantation on the fin material layer 105, the mask layer 101 plays a role in protecting and blocking the top of the substrate 100 in the first device region 100 a.
Referring to fig. 12 to 15, the fin material layer 105 of the substrate 100 of the first device region 100a and the fin material layer 105 of the second device region 100b are patterned, a substrate 108 and a fin 109 protruding from the substrate 108 and spaced apart from the dummy fin 104 are formed in the first device region 100a and the second device region 100b, wherein the fin 109 of the second device region is formed by the fin material layer 105.
Specifically, a substrate 108 and a fin 109 protruding from the substrate 108 are formed on the first device region 100a and the second device region 100b, which provides a process foundation for subsequent processes such as forming a work function layer.
In this embodiment, the steps of forming the substrate 108 and the fin 109 protruding from the substrate 108 include: as shown in fig. 13, a second mask layer 106 is formed on the top of the substrate 100 in the first device region and on the top of the fin material layer 105 in the second device region, and the dummy fin 104 is exposed by the second mask layer 106; as shown in fig. 14, the substrate 100 in the first device region 100a and the fin material layer 105 in the second device region 100b are etched by using the second mask layer 106 as a mask, a protruding portion formed after the etching is used as a fin 109, and the remaining substrate 100 and the fin material layer 105 at the bottom of the fin 109 are used as a substrate 108.
In this embodiment, the remaining base 100 in the first device region 100a is used as a substrate 108, a portion protruding from the substrate 108 of the first device region 100a is used as a fin 109 of the first device region 100a, the remaining fin material layer 105 in the second device region 100b is used as a top substrate 111, a portion protruding from the top substrate 111 is used as a fin 109 of the second device region 100b, the remaining base 100 in the second device region 100b is used as a bottom substrate 120, and the substrate 108 in the second device region 100b includes the top substrate 111 and the bottom substrate 120.
In other embodiments, the entire thickness of the fin material layer may also be etched during the formation of the fin, depending on the amount of etching. Accordingly, the substrate material of the first device region and the second device region is the same.
In this embodiment, an etching selectivity ratio is provided between the substrate 100 and the dummy fin 104, and an etching selectivity ratio is also provided between the fin material layer 105 and the dummy fin 104, so that the dummy fin 104 can be exposed by the second mask layer 106. Accordingly, the presence of the dummy fin 104 has little impact on the process of forming the fin 109.
Referring collectively to fig. 15, fig. 15 is a top view of fig. 14. Here, the substrate is not illustrated for convenience of illustration.
In this embodiment, in the step of forming the fin portion 109, along the extending direction of the fin portion 109, the fin portion 109 includes a channel region 130.
The channel region 130 provides the channel required for transistor operation.
Referring to fig. 12, after forming the fin material 105, before patterning the substrate 100 of the first device region 100a and the fin material layer 105 of the second device region 100b, the method further includes: the fin material layer 105 of the second device region 100b is planarized with the top of the substrate 100 of the first device region 100a as a stop.
It should be noted that, the fin material layer 105 of the second device region 100b is planarized, so that the top of the substrate 100 of the first device region 100a is flush with the top of the fin material layer 105 of the second device region 100b, and thus in the step of patterning the substrate 100 of the first device region 100a and the fin material layer 105 of the second device region 100b, the fin 109 formed in the first device region 100a and the fin 109 formed in the second device region 100b have the same height, thereby providing a good process basis for forming a work function layer conformally covering the fin 109.
In this embodiment, before forming the fin 101, in the process of performing the planarization treatment, the method further includes removing the mask layer 101 and the dummy fin 104 higher than the top of the substrate 100 in the first device region 100 a.
The mask layer 101 and the dummy fin portion 104 higher than the top of the substrate 100 of the first device region 100a are removed, so that a process foundation is laid for forming the substrate 108 and the fin portion 109.
Referring to fig. 16, an isolation layer 112 is formed on the substrate 108 where the fin 109 is exposed, and the isolation layer 112 covers the fin 109 and a portion of the sidewall of the dummy fin 104.
The isolation layer 112 is used to isolate adjacent devices. The material of the isolation layer 112 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 112 is silicon oxide.
Referring to fig. 17-18, fig. 17 is a top view and fig. 18 is a cross-sectional view of fig. 17 taken along the line AB. In the first device region 100a, a first source-drain doping layer 117 is formed in the fin portion 109 on both sides of the channel region 130; in the second device region 100b, second source-drain doping layers 119 are formed in the fin portion 109 on two sides of the channel region 130, and the first source-drain doping layers 117 and the second source-drain doping layers 119 are separated by the dummy fin portion 104.
For convenience of illustration, fig. 17 only illustrates the fin 109, the dummy fin 104, the first source-drain doping layer 117, and the second source-drain doping layer 119.
The first source-drain doping layer 117 serves as a source region or a drain region of the first device region 100a, and when the semiconductor structure works, the first source-drain doping layer 117 provides stress for the channel region 130, so that the mobility of carriers is improved.
The second source-drain doping layer 119 serves as a source region or a drain region of the second device region 100b, and when the semiconductor structure works, the second source-drain doping layer 119 provides stress for the channel region 130, so that the mobility of carriers is improved.
In this embodiment, the first device region 100a is used to form an NMOS transistor, and the first source-drain doping layer 117 is an epitaxial layer doped with N-type ions. The N-type ions are P ions, As ions or Sb ions. N-type ions are doped in the epitaxial layer to replace the positions of silicon atoms in crystal lattices, and the more N-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. As an example, the epitaxial layer corresponding to the first source-drain doping layer 117 is made of SiP or Si.
In this embodiment, the second device region 100b is used to form a PMOS transistor, and the second source-drain doping layer 119 is an epitaxial layer doped with P-type ions. The P-type ions are B ions, Ga ions or In ions. By doping the epitaxial layer with P-type ions, the P-type ions are substituted for the positions of silicon atoms in the crystal lattice, and the more P-type ions are doped, the higher the concentration of majority ions is, and the stronger the conductivity is. As an example, the epitaxial layer corresponding to the second source-drain doping layer 119 is made of SiGe.
In this embodiment, the first source-drain doping layer 117 and the second source-drain doping layer 119 are formed by an epitaxial process. In this embodiment, the first source-drain doping layer 117 and the second source-drain doping layer 119 are sigma-shaped.
In this embodiment, after the dummy gate structure of the fin portion 109 crossing the channel region 130 is formed, the first source-drain doping layer 117 is formed in the fin portion 109 on both sides of the dummy gate structure of the first device region 100a, and the second source-drain doping layer 119 is formed in the fin portion 109 on both sides of the dummy gate structure of the second device region 100 b. The description of the pseudo gate structure is not repeated herein.
With reference to fig. 18, in the process of forming the first source-drain doping layer 117 and the second source-drain doping layer 119, the first source-drain doping layer 117 and the second source-drain doping layer 119 are isolated by the dummy fin portion 104, so that the probability of interconnection between the first source-drain doping layer 117 and the second source-drain doping layer 119 is reduced, and the performance of the semiconductor structure is improved.
Referring to fig. 19, before the subsequent formation of the work function layer, the method further includes: an interlayer dielectric layer 118 is formed in the first device region 100a and the second device region 100 b.
The interlevel dielectric layer 118 is used to isolate adjacent devices. The material of the interlayer dielectric layer 118 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 118 is made of silicon oxide.
In this embodiment, after forming the interlayer dielectric layer 118, the method further includes: and removing the pseudo gate structure. By removing the dummy gate structure, preparation is made for the subsequent formation of the work function layer.
Referring to fig. 20, a gate dielectric layer 113 is formed on top of the isolation layer 112 in the first device region 100a and the second device region 100b to conformally cover the top and sidewalls of the fin 109 and the dummy fins 104.
Specifically, the gate dielectric layer 113 is made of a high-k dielectric material. Wherein, the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the gate dielectric layer 113 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a).
Referring to fig. 20 to 21, in the second device region 100b, a second work function layer 114 is formed across the fin 109, and the second work function layer 114 conformally covers the gate dielectric layer 113.
The second work function layer 114 is used to adjust the threshold voltage of the second transistor. In this embodiment, the material of the second work function layer 214 includes one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN, and TiAlC. The specific material and film structure of the second work function layer 214 depend on the performance of the first type transistor.
In this embodiment, in the second device region 100b, the step of forming the second work function layer 114 crossing the fin 109 includes: forming a second work function layer 114 across the fin 109 in the first and second device regions 100a, 100 b; the second work function layer 114 of the first device region 100a is removed, and the second work function layer 114 of the second device region 100b remains.
Specifically, the second type transistor is a PMOS transistor, the second work function layer 114 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN and TiAlN. In other embodiments, when the second type transistor is an NMOS transistor, the second work function layer 114 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.
It should be noted that, in the process of forming the second work function layer 114 crossing the fin 109 in the first device region 100a and the second device region 100b, the second work function layer 114 also crosses the dummy fin 104, so that the step of removing the second work function layer 114 in the first device region 100a further includes removing the second work function layer 114 conformally covering the dummy fin 104.
Referring to fig. 22, in the first device region 100a, a first work function layer 115 is formed across the fin 109, and the first work function layer 115 conformally covers the gate dielectric layer 113.
The first work function layer 115 is used to adjust the threshold voltage of the first type transistor. In this embodiment, the material of the first work function layer 215 includes one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN, and TiAlC. The specific material and film structure of the first work function layer 215 depend on the performance of the first type transistor.
Specifically, the first type transistor is an NMOS transistor, the first work function layer 115 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC. In other embodiments, when the first type transistor is a PMOS transistor, the second work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN.
In this embodiment, after the second work function layer 114 is formed, the first work function layer 115 is formed. Specifically, in the step of forming the first work function layer 115, the first work function layer 115 further conformally covers the gate dielectric layer 113 on the dummy fin 104 and the second work function layer 114.
It should be noted that the first work function layer 115 can meet the process requirement for adjusting the threshold voltage of the first type transistor, the second work function layer 114 can meet the process requirement for adjusting the threshold voltage of the second type transistor, and in the forming process of the first work function layer 115, the first work function layer 115 is further located in the second device region 100b, and in order to reduce the process steps and the process cost, the step of patterning the first work function layer 115 is omitted, so that the first work function layer 115 further conformally covers the dummy fin 104 and the second work function layer 114 located in the second device region 100 b.
It should be further noted that the second work function layer 114 can meet the process requirement for adjusting the threshold voltage of the second type transistor, and the dummy fin 104 separates the second work function layer 114 located in the second device region 100b from the first work function layer 115 located in the first device region 100a, so that even if the first work function layer 115 further conformally covers the dummy fin 104 and the second work function layer 114 located in the second device region 100b, the probability of ion interdiffusion between different work function layers in adjacent device regions can be still reduced, which is beneficial to ensuring the respective performances of the first work function layer 115 and the second work function layer 114, thereby improving the performance of the semiconductor structure.
Referring to fig. 23, after the first work function layer 115 and the second work function layer 114 are formed, a gate layer 116 covering the first work function layer 115, the second work function layer 114, and the dummy fin 104 is formed.
The gate layer 116 is used for subsequent electrical connection to external structures. The material of the gate layer 116 includes one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC. In this embodiment, the material of the gate layer 116 includes W.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected in the form 30 by one skilled in the art without departing from the spirit and scope of the invention as defined by the claims appended hereto.

Claims (26)

1. A semiconductor structure, comprising:
the transistor comprises a substrate, a first transistor element, a second transistor element and a control circuit, wherein the substrate comprises a first device area and a second device area which are adjacent, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different;
the fin parts are respectively raised on the substrate of the first device area and the substrate of the second device area;
the dummy fin portion is protruded on the substrate at the junction of the first device area and the second device area and is spaced from the fin portion, and the material of the dummy fin portion comprises dielectric material;
the isolation layer is positioned on the substrate with the exposed fin parts and covers partial side walls of the fin parts and the pseudo fin parts;
the gate dielectric layer is positioned in the first device area and the second device area and conformally covers the tops and the side walls of the fin part and the pseudo fin part;
the first work function layer conformally covers the gate dielectric layer in the first device area;
and the second work function layer conformally covers the gate dielectric layer in the second device area.
2. The semiconductor structure of claim 1, wherein the first type transistor is an NMOS transistor and the second type transistor is a PMOS transistor;
the first work function layer is also positioned in the second device area and conformally covers the gate dielectric layer on the pseudo fin portion and the second work function layer.
3. The semiconductor structure of claim 1, further comprising: and the grid layer is positioned in the first device area and the second device area and covers the first work function layer, the second work function layer and the dummy fin part.
4. The semiconductor structure of claim 1, wherein along an extension direction of the fin, the fin includes a channel region;
the semiconductor structure further includes: the first source drain doping layer is positioned in the first device region and positioned in the fin parts on two sides of the channel region; and the second source-drain doping layer is positioned in the second device region, positioned in the fin parts on two sides of the channel region, and the adjacent first source-drain doping layer and the second source-drain doping layer are isolated by the pseudo fin part.
5. The semiconductor structure of claim 1, wherein a material of the fin in the first and second device regions is different.
6. The semiconductor structure of claim 5, wherein the substrate of the second device region comprises a bottom substrate of the same material as the substrate of the first device region and a top substrate on the bottom substrate of the same material as the fin material of the second device region;
the bottom of the dummy fin also extends into the substrate, and the bottom of the dummy fin is flush with the bottom of the top substrate.
7. The semiconductor structure of claim 1, wherein a top of the dummy fin is higher than or flush with a top of the fin.
8. The semiconductor structure of claim 1, wherein a lateral dimension of the dummy fin is 3 nm to 10 nm, taken as a lateral direction perpendicular to an extending direction of the fin.
9. The semiconductor structure of claim 1, wherein a material of the fin comprises silicon, silicon germanium, or a group iii-v semiconductor material.
10. The semiconductor structure of claim 1, wherein the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride.
11. The semiconductor structure of claim 1, wherein a material of the gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a).
12. The semiconductor structure of claim 1, wherein a material of the first work function layer comprises one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN, and TiAlC;
the material of the second work function layer comprises one or more of TiAl, Mo, MoN, AlN, TiN, TaN, TaSiN, TaAlN, TiAlN and TiAlC.
13. The semiconductor structure of claim 3, wherein the material of the gate layer comprises one or more of TiN, TaN, Ta, Ti, TiAl, W, AL, TiSiN, and TiAlC.
14. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first device area and a second device area which are adjacent, the first device area is used for forming a first type transistor, the second device area is used for forming a second type transistor, and the first type and the second type are different;
in the second device area, removing part of the thickness of the substrate, and forming a groove in the rest of the substrate;
forming a dummy fin portion on the side wall of the groove, wherein the dummy fin portion comprises a dielectric material;
after the pseudo fin portion is formed, a fin portion material layer is formed in the residual space of the groove;
patterning the substrate of the first device region and a fin material layer of the second device region, forming a substrate and a fin portion protruding from the substrate and spaced from the dummy fin portion in the first device region and the second device region, wherein the fin portion of the second device region is formed by the fin material layer;
forming an isolation layer on the substrate with the exposed fin parts, wherein the isolation layer covers the fin parts and partial side walls of the pseudo fin parts;
forming a gate dielectric layer which conformally covers the tops and the side walls of the fin part and the pseudo fin part on the top of the isolation layer;
forming a first work function layer crossing the fin portion in the first device area, wherein the first work function layer conformally covers the gate dielectric layer;
and forming a second work function layer crossing the fin part in the second device area, wherein the second work function layer conformally covers the gate dielectric layer.
15. The method of claim 14, wherein the first type transistor is an NMOS transistor and the second type transistor is a PMOS transistor;
forming the first work function layer after forming the second work function layer;
in the step of forming the first work function layer, the first work function layer also conformally covers the gate dielectric layer and the second work function layer.
16. The method of forming a semiconductor structure of claim 14, wherein the step of forming the recess comprises: forming a first mask layer with a mask opening on the top of the substrate, wherein the first mask layer is positioned in the first device area, and the mask opening is positioned in the second device area; etching the substrate with partial thickness of the second device area along the mask opening by taking the first mask layer as a mask, and forming a groove in the second device area;
before forming the fin portion, further comprising: and removing the first mask layer.
17. The method of forming a semiconductor structure of claim 16, wherein after forming the layer of fin material and before patterning the substrate of the first device region and the layer of fin material of the second device region, further comprising: performing planarization treatment on the fin material layer of the second device region by taking the top of the substrate of the first device region as a stop position;
and in the process of carrying out planarization treatment, removing the first mask layer and the dummy fin part higher than the substrate of the first device area.
18. The method of forming a semiconductor structure of claim 14, wherein forming the dummy fin comprises: forming a pseudo fin material layer on the bottom and the side wall of the groove and the top of the substrate; and removing the pseudo fin material layer at the bottom of the groove and at the top of the substrate, wherein the residual pseudo fin material layer is used as the pseudo fin.
19. The method of claim 18, wherein the process of forming the dummy fin material layer comprises an atomic layer deposition process.
20. The method of forming a semiconductor structure of claim 14, wherein forming the substrate and the fin raised above the substrate comprises: forming a second mask layer on the top of the substrate of the first device area and the top of the fin material layer of the second device area, wherein the second mask layer exposes the pseudo fin;
and etching the substrate in the first device area and the fin material layer in the second device area by taking the second mask layer as a mask, wherein a protruding part formed after etching is used as a fin part, and the residual substrate at the bottom of the fin part and the fin material layer are used as substrates.
21. The method of forming a semiconductor structure of claim 14, wherein after forming the layer of fin material, and prior to forming the substrate and the fin raised from the substrate, further comprising: and carrying out well region ion implantation on the fin part material layer.
22. The method of forming a semiconductor structure of claim 14, wherein the dielectric material comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, and silicon oxynitride.
23. The method of forming a semiconductor structure of claim 14, wherein the step of forming the layer of fin material is performed with a material different from the substrate.
24. The method of forming a semiconductor structure of claim 14, wherein the step of forming the fin material layer comprises a material comprising silicon, silicon germanium, or a group iii-v semiconductor material.
25. The method of forming a semiconductor structure of claim 14, wherein in the step of forming the fin, the fin includes a channel region along an extension direction of the fin;
the forming method further includes: forming a first source-drain doping layer in the fin parts on two sides of the channel region in the first device region; and in the second device region, second source-drain doped layers are formed in the fin parts on two sides of the channel region, and the first source-drain doped layers and the second source-drain doped layers are isolated by the pseudo fin parts.
26. The method of forming a semiconductor structure of claim 14, further comprising: and after the first work function layer and the second work function layer are formed, forming a gate layer covering the first work function layer, the second work function layer and the dummy fin portion.
CN202110282878.9A 2021-03-16 2021-03-16 Semiconductor structure and forming method thereof Pending CN115084134A (en)

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