CN105576029A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN105576029A
CN105576029A CN201510731674.3A CN201510731674A CN105576029A CN 105576029 A CN105576029 A CN 105576029A CN 201510731674 A CN201510731674 A CN 201510731674A CN 105576029 A CN105576029 A CN 105576029A
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三室阳一
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Seiko Instruments Inc
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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Abstract

本发明提供一种半导体装置。在制造搭载有LOCOS漏极型MOS晶体管的集成电路的过程中，对形成栅极的多晶硅膜进行图案化时，有时会产生图案形成不良而使栅极发生偏移。本发明提供一种搭载有LOCOS漏极型MOS晶体管的集成电路，其即使产生图案异常，也不会发生耐压的下降，不会导致耐压不良。通过在LOCOS漏极型MOS晶体管的漏极侧的有源区上形成比栅极氧化膜厚的漏极氧化膜，即使栅极到达漏极的有源区，MOS晶体管的耐压也不会下降。

Description

半导体装置
技术领域
本发明涉及具有MOS型半导体元件的半导体装置，特别是涉及具有具备高耐压的MOS型半导体元件的半导体装置。
背景技术
在构成半导体装置的、具有MOS型晶体管结构的MOS型半导体元件中，为了实现高漏极耐压，需要对其漏极附近进行电场弛豫。实现漏极附近的电场弛豫的方法之一有所谓的LOCOS漏极型MOS晶体管，其中，将利用LOCOS法形成的厚氧化膜(场氧化膜)配置于漏极附近。
图2示出了LOCOS漏极型MOS晶体管的截面图。在P型硅衬底1的表面，分开配置有形成源极区的高浓度的N型扩散层5和形成漏极区的中浓度的N型扩散层2。高浓度的N型扩散层5与中浓度的N型扩散层2之间的沟道区形成厚的栅极氧化膜时，电流驱动能力下降，因此在该部分设置有薄的栅极氧化膜6A。在形成漏极区的中浓度的N型扩散层2之上，配置有作为厚氧化膜的LOCOS氧化膜7。从沟道区上的薄的栅极氧化膜6A至LOCOS氧化膜7配置有栅极8。为了与金属层获得连接，邻接于中浓度的N型扩散层2而形成高浓度的N型扩散层4，在高浓度的N型扩散层4的表面上设置有薄的漏极上的氧化膜(以下称为漏极氧化膜)6B。
有时在形成漏极区的中浓度的N型扩散层2和高浓度的N型扩散层4之下进一步设置低浓度的N型扩散层3。低浓度的N型扩散层3也可以以N型阱区的形式形成。LOCOS氧化膜7原本的目的是元件分离，而将其用于高耐压MOS晶体管的漏极而得到的结构是能够在不增加工序的情况下实现高耐压MOS晶体管的方法。需要说明的是，图中，N+的记载表示杂质浓度高于N±。另外，N±是指杂质浓度高于N型阱的浓度。
针对LOCOS漏极型MOS晶体管，进行了降低漏极耐压的偏差等各种各样的钻研(例如参照专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2002-329728号公报
发明内容
发明所要解决的问题
在搭载有LOCOS漏极型MOS晶体管的集成电路的设计上，期望沿漏极附近的LOCOS氧化膜7的沟道的方向的长度尽可能短。但是，若该长度短，则在制造集成电路的过程中，对形成其栅极的多晶硅膜进行图案化时，有时会发生位置偏移，有可能形成不期望的图案。
将这种图案形成不良的情况示于图3。原本，由多晶硅膜形成的栅极8形成至LOCOS氧化膜7的上表面的平坦部为止，但若产生图案形成不良，则有时会超过LOCOS氧化膜7而到达至设置于漏极的高浓度区域4之上的薄的漏极氧化膜6B。附图的符号12表示延伸至薄的漏极氧化膜6B之上的栅极的部分。在漏极区与栅极之间会施加大的电势差，因此，若形成这种结构，则到达漏极的高浓度区域的栅极之下的漏极氧化膜薄，耐压低，因此无法具有该LOCOS漏极型MOS晶体管所要求的原本的耐压，从而导致耐压不良。
因此，本发明的课题在于提供一种包含具有MOS型晶体管结构的MOS型半导体元件的半导体装置，其即使在形成如上所述的不期望的图案的情况下，耐压也不会下降。
用于解决问题的手段
为了解决上述课题，本发明如下构成。即，其结构为：在LOCOS漏极型MOS晶体管的漏极侧的高浓度区域之上配置比栅极氧化膜厚的漏极氧化膜。
发明效果
通过使用上述手段，即使在存在图案缺陷的情况下，到达至漏极的有源区的栅极之下的漏极氧化膜的耐压也不会下降。即使发生图案异常，也不会产生耐压劣化，因此产品合格率稳定。另外，即使产生图案异常，也能够避免连续使用状态下的绝缘耐性的经时劣化，能够降低经时劣化不良。
附图说明
图1是本发明的实施例的LOCOS漏极型MOS晶体管的截面示意图。
图2是现有的LOCOS漏极型MOS晶体管的截面示意图。
图3是在现有的LOCOS漏极型MOS晶体管中产生图案异常时的截面示意图。
图4是示出本发明的实施例的LOCOS漏极型MOS晶体管的制造工序的截面示意图。
符号说明
1P型硅衬底
2中浓度N型扩散层
3低浓度N型扩散层
4漏极侧的高浓度N型扩散层
5源极侧的高浓度N型扩散层
6A栅极氧化膜
6B、9漏极氧化膜
7LOCOS氧化膜
8栅极
10硅氧化膜
11硅氮化膜
具体实施方式
图1是本发明的实施例的LOCOS漏极型MOS晶体管的截面示意图。在P型硅衬底1的表面，分开配置有形成源极区的高浓度的N型扩散层5和形成漏极区的中浓度的N型扩散层2。在高浓度的N型扩散层5与中浓度的N型扩散层2之间的沟道区设置有比较薄的栅极氧化膜6A。其原因在于，若形成厚的栅极氧化膜，则电流驱动能力会下降。与栅极氧化膜6A相连续，在形成漏极区的中浓度的N型扩散层2之上配置有作为厚氧化膜的LOCOS氧化膜7。其原因在于，在漏极区的沟道侧的端部，会对氧化膜施加大的电场，因此，为了能够承受该电场而配置有作为厚氧化膜的LOCOS氧化膜7。并且，从沟道区上的薄的栅极氧化膜6A至LOCOS氧化膜7的平坦部，配置栅极8。
为了与形成配线的金属层获得连接，邻接于形成漏极的中浓度的N型扩散层2而形成高浓度的N型扩散层4，在高浓度的N型扩散层4的表面设置有膜厚比薄的栅极氧化膜6A厚的漏极氧化膜9。在高浓度的N型扩散层4的表面未设置有LOCOS氧化膜，因此形成了漏极的有源区。此处，漏极氧化膜9的厚度设定为在通常的工作中不会被施加于栅极与漏极区之间的最大电势差所破坏的厚度。有时在形成漏极区的中浓度的N型扩散层2和高浓度的N型扩散层4之下进一步设置低浓度的N型扩散层3。低浓度的N型扩散层3也可以以N型阱区的形式形成。
如上所述，本实施例中的特征在于，与LOCOS氧化膜7连续而设置于漏极的高浓度区域4的表面的漏极氧化膜9的膜厚大于设置于沟道区上的薄的栅极氧化膜6A的膜厚。需要说明的是，如图所示，漏极氧化膜9的膜厚与LOCOS氧化膜7相比变薄。
通过设定为这样的结构，即使在栅极8的图案化中发生位置偏移而导致栅极8超过LOCOS氧化膜7而到达设置于漏极的高浓度区域4之上的漏极氧化膜9，由于漏极氧化膜9具有在通常的工作中不会被施加于栅极与漏极区之间的最大电势差所破坏的厚度，因此静电放电的可能性也会减小，能够确保可靠性。
优选栅极与LOCOS氧化膜具有LOCOS氧化膜的沟道方向长度的1/2以上的重叠长度，以使得在LOCOS氧化膜7的沟道方向的长度极短的情况下，即使栅极8的位置偏移也可覆盖沟道区而不会形成偏移区(offset)。即，优选LOCOS氧化膜7的一半以上由栅极8覆盖。
图4示出了制造图1所示的实施例的工序。如图4(a)所示，首先在P型硅衬底1上形成低浓度的N型扩散层3，接着依次形成硅氧化膜10、硅氮化膜11。之后，进行图案化，仅在形成LOCOS氧化膜的部分将硅氮化膜11蚀刻除去，在该部分形成中浓度的N型扩散层。在该状态下，进行LOCOS氧化，形成LOCOS氧化膜。
形成LOCOS氧化膜后，将硅氮化膜以及形成于其下的硅氧化膜10除去，由此得到图4(b)的结构。
之后，如图4(c)所示，在高耐压的MOS型半导体元件的未被LOCOS氧化膜覆盖的区域形成作为漏极氧化膜9的氧化膜。其膜厚按照耐压高于漏极耐压的方式来确定。例如，在漏极耐压为25V的情况下，该厚栅极氧化膜设定为300A左右的膜厚。
之后，如图4(d)所示，仅将漏极氧化膜9中的、位于作为源极侧的有源区的源极区和沟道区之上的氧化膜蚀刻除去，形成比漏极氧化膜9薄的栅极氧化膜6A。其膜厚根据作为目标的电流驱动能力和漏极耐压来确定。接着，形成多晶硅膜，进行图案化，形成栅极，形成高浓度的源极区以及作为漏极区的高浓度的N型扩散层，从而形成图1所示的MOS型半导体元件。

Claims (3)

1.一种半导体装置，其包含MOS晶体管，该MOS晶体管具有设置在沟道区的表面的栅极氧化膜、以及与所述栅极氧化膜连续而配置于漏极侧且膜厚比所述栅极氧化膜厚的LOCOS氧化膜，所述半导体装置的特征在于，
在与所述沟道区相反的方向上超出所述LOCOS氧化膜的、所述MOS晶体管的漏极侧的有源区的表面上，与所述LOCOS氧化膜连续而配置有膜厚比所述栅极氧化膜厚且比所述LOCOS氧化膜薄的漏极氧化膜。
2.如权利要求1所述的半导体装置，其特征在于，所述漏极氧化膜的耐压高于所述漏极的耐压。
3.如权利要求1所述的半导体装置，其特征在于，所述栅极与所述LOCOS氧化膜具有所述LOCOS氧化膜的沟道方向长度的1/2以上的重叠长度。
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