CN105573703A - Double-screen different-image graphic generating system - Google Patents
Double-screen different-image graphic generating system Download PDFInfo
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- CN105573703A CN105573703A CN201510954411.9A CN201510954411A CN105573703A CN 105573703 A CN105573703 A CN 105573703A CN 201510954411 A CN201510954411 A CN 201510954411A CN 105573703 A CN105573703 A CN 105573703A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
- G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
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Abstract
The invention discloses a double-screen different-image graphic generating system. The system comprises a comprehensive programmable device and a DDR3 SDRAM frame memory device which are connected, wherein the comprehensive programmable device comprises an ARM processor, a multi-port DDR3 SDRAM controller, a first DDR3 SDRAM frame memory reading and writing module, a first data conversion module, a second data conversion module, a second DDR3 SDRAM frame memory reading and writing module, a thirddata conversion module, a fourth data conversion module and a timing sequence generation module; the DDR3 SDRAM frame memory device comprises a first buffer module, a second buffer module, a third buffer module, a fourth buffer module, a fifth buffer module and a sixth buffer module. The double-screen different-image graphic generating system is characterized by high circuit integration level, low power consumption and small size; synchronous output of double-screen different-image frames can be achieved, and the double-screen frames can be spliced into a complete frame; data bandwidth is high, and processing speed is high; graphic generation efficiency is high, and dynamic frame display is smooth; compatibility is high, and the system can support various high-resolution frames.
Description
Technical field
The present invention relates to a kind of Grafmaster, particularly relate to a kind of double screen aniseikania Grafmaster.
Background technology
Figure circuit for generating is the supporting vitals of liquid crystal display, formed by multiple digital circuit combination of devices, major function is according to mapping instruction, makes graph parameter, data, uses various digital processing technology, real-time generation graphic picture data, show with liquid crystal display.Along with the widespread use of big screen LCD in airborne passenger cabin, double screen aniseikania graphic hotsopt circuit becomes the vitals in passenger cabin graphic display system.Existing graphic hotsopt circuit generally adopts Digital processing device DSP, programmable logic device (PLD) FPGA and random access frame memory device SRAM as main processing block, digital processing unit runs mapping algorithm program, be responsible for generating graph data, programmable logic device (PLD) has assisted the generation of complex figure data as coprocessor, and random access frame memory device is used for register map graphic data.
Along with the development of technology, big screen LCD is applied gradually in airborne passenger cabin.The screen pixels resolution of big screen LCD is the twice of regular display, and existing double screen graphic hotsopt circuit generally takes repetition overlay model, namely takes two cover graphic hotsopt circuit, often overlaps and drives half screen display respectively.There is following defect in this circuit: circuit scale is huge, integrated level and reliability is not high, figure generation efficiency is low, be difficult to realize across screen synchronous dynamic display.
Summary of the invention
The object of the invention is to solve above-mentioned technical matters, propose that a kind of integrated level is high, strong adaptability, reliability are high, can realize the Grafmaster of double screen aniseikania across screen simultaneous display.
The object of the invention is to propose a kind of double screen aniseikania Grafmaster, comprise connected complex programmable device and DDR3SDRAM frame memory device, described complex programmable device comprises arm processor, multiport DDR3SDRAM controller, one DDR3SDRAM frame deposits module for reading and writing, first data conversion module, second data conversion module, 2nd DDR3SDRAM frame deposits module for reading and writing, 3rd data conversion module, 4th data conversion module, sequence generation module, DDR3SDRAM frame memory device comprises the first buffer module, second buffer module, 3rd buffer module, 4th buffer module, 5th buffer module, 6th buffer module,
Wherein, multiport DDR3SDRAM controller deposits module for reading and writing with arm processor, a DDR3SDRAM frame, the 2nd DDR3SDRAM frame deposits module for reading and writing, DDR3SDRAM frame memory device is connected; One DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the second data conversion module; 2nd DDR3SDRAM frame is deposited module for reading and writing and is connected with the 3rd data conversion module, the 4th data conversion module; Sequence generation module deposits module for reading and writing with arm processor, a DDR3SDRAM frame, the 2nd DDR3SDRAM frame deposits module for reading and writing, the first data conversion module, the second data conversion module, the 3rd data conversion module, the 4th data conversion module are connected.
Further, in described DDR3SDRAM frame memory device, the first buffer module and the 4th buffer module, the second buffer module and the 5th buffer module, the 3rd buffer module and the 6th buffer module form double screen pixel data buffer all between two in groups.
Further, described multiport DDR3SDRAM controller is divided into write to the operation of the first buffer module, the second buffer module, the 3rd buffer module, the 4th buffer module, the 5th buffer module, the 6th buffer module in DDR3SDRAM frame memory device, reads, empties Three models state.
Further, described multiport DDR3SDRAM controller to the write received, read, empty Three models state and arbitrate and prioritization process.
Further, described first data conversion module is used for full zero data to be converted to a DDR3SDRAM Read-write Catrol module acceptable data layout, and described second data conversion module is used for converting the data that a DDR3SDRAM Read-write Catrol module reads from DDR3SDRAM to meet VSEA standard digital RGB video form; Described 3rd data conversion module is used for full zero data to be converted to the 2nd DDR3SDRAM Read-write Catrol module acceptable data layout, and described 4th data conversion module is used for converting the data that the 2nd DDR3SDRAM Read-write Catrol module reads from DDR3SDRAM to meet VSEA standard digital RGB video form.
Beneficial effect of the present invention:
1. the circuit level of system is high, low in energy consumption, volume is little;
2. can realize double screen aniseikania picture synchronization to export, support that double screen picture splicing becomes a width complete picture;
3. data bandwidth is high, and processing speed is fast;
4. figure generation efficiency is high, the display of dynamic menu smoothness;
5. compatible strong, multiple high graphics picture can be supported.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of double screen aniseikania of the present invention Grafmaster.
Embodiment
The invention provides a kind of double screen aniseikania Grafmaster.Be illustrated in figure 1 the structural representation of double screen aniseikania graphic hotsopt circuit of the present invention.It comprises connected complex programmable device and DDR3SDRAM frame memory device, complex programmable device comprises arm processor, multiport DDR3SDRAM controller, a DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the second data conversion module, the 2nd DDR3SDRAM frame deposit module for reading and writing, the 3rd data conversion module, the 4th data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffer module, the second buffer module, the 3rd buffer module, the 4th buffer module, the 5th buffer module, the 6th buffer module.Wherein, multiport DDR3SDRAM controller deposits module for reading and writing with arm processor, a DDR3SDRAM frame, the 2nd DDR3SDRAM frame deposits module for reading and writing, DDR3SDRAM frame memory device is connected; One DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the second data conversion module; 2nd DDR3SDRAM frame is deposited module for reading and writing and is connected with the 3rd data conversion module, the 4th data conversion module; Sequence generation module and a DDR3SDRAM frame deposit module for reading and writing, the 2nd DDR3SDRAM frame deposits module for reading and writing, the first data conversion module, the second data conversion module, the 3rd data conversion module, the 4th data conversion module are connected.
In DDR3SDRAM frame memory device, the first buffer module and the 4th buffer module are one group, the second buffer module and the 5th buffer module be one group, the 3rd buffer module and the 6th buffer module are one group, often organize buffer module and form complete double screen pixel data buffer respectively.
Arm processor, for carrying out drawing algorithm computing, obtain drawing operational data, send write operation request to multiport DDR3SDRAM controller, by multiport DDR3SDRAM controller by the buffer module in drawing operational data write DDR3SDRAM frame memory device.
Sequence generation module, for generation of arm processor, first data conversion module, second data conversion module, 3rd data conversion module, 4th data conversion module, one DDR3SDRAM frame deposits module for reading and writing, 2nd DDR3SDRAM frame deposits all kinds of clock signals needed for module for reading and writing, comprising the line synchronizing signal Hsync meeting VSEA standard, field sync signal Vsync, horizontal blanking signal Hblank, field blanking signal Vblank, enable signal Enable, also comprise a DDR3SDRAM module for reading and writing, 2nd DDR3SDRAM frame deposits module for reading and writing frame starting signal Fsync, arm processor interrupts control signal irq.Fsync signal and irq signal are periodic signal, and identical with the Vsync signal period.Described irq interrupts control signal and carries out drawing computing for controlling arm processor, arm processor often receives an irq signal, then enter interrupt service routine, in interrupt service routine first according on the operator scheme of three groups of buffer modules in DDR3SDRAM in a Vsync signal period, to write, read, the buffer module first address reset corresponding to three kinds of operator schemes switches, also within the current Vsync signal period, namely change the operator scheme of six buffer modules, determine that ARM writes the first address of buffer module in DDR3SDRAM and a DDR3SDRAM frame deposits module for reading and writing and the 2nd DDR3SDRAM frame deposits the reading of module for reading and writing and the buffer module first address corresponding to clear operation, to read and buffer module first address corresponding to clear operation writes a DDR3SDRAM frame by ARM software and deposits module for reading and writing and the 2nd DDR3SDRAM frame deposits corresponding register in module for reading and writing, then arm processor carries out drawing calculation process.One DDR3SDRAM frame deposits module for reading and writing and the 2nd DDR3SDRAM frame deposits module for reading and writing after receiving Fsync enabling signal, reads and null clear operation respectively according to first address to corresponding buffer module.
Multiport DDR3SDRAM controller, for the write received, read, empty three kinds of operator schemes and arbitrate and prioritization process.Write, read, empty three kinds of operator schemes corresponding to three groups of buffer modules in DDR3SDRAM frame memory device.Said write operator scheme is arm processor certain group buffer module write double screen drawing operational data in DDR3SDRAM frame memory device; Read mode is that the first and second DDR3SDRAM frames deposit module for reading and writing certain group buffer module reading draw data from DDR3SDRAM frame memory device; Null clear operation pattern be the first and second DDR3SDRAM frames deposit module for reading and writing in DDR3SDRAM frame memory device certain group buffer module write full zero data.In a certain moment, only have a kind of request of access to meet with a response, also namely only have a buffering to be in accessed state, but three kinds of request of access all meet with a response within a frame period, three groups totally six bufferings all accessed.
First and second DDR3SDRAM frames deposit module for reading and writing, for writing full zero data by multiport DDR3SDRAM controller certain group buffer module module in DDR3SDRAM frame memory device, or from certain group buffer module, read the whole screen picture data of a frame, the Fsync signal that two kinds of operator schemes are sent by sequence generation module starts, often there is a Fsync pulse signal, then start and once access, the whole screen data of a frame that once access is corresponding complete.The Fsync signal period is identical with the Vsync signal period.
DDR3SDRAM frame memory device, for carrying out the buffered of draw data, comprises the first buffer module, the second buffer module, the 3rd buffer module, the 4th buffer module, the 5th buffer module, the 6th buffer module.Wherein first and the 4th buffer module be one group, second and the 5th buffer module be one group, 3rd and the 6th buffer module is one group, the operator scheme often organizing buffer module with Vsync signal for the cycle switches, the first address of each buffer module is set by arm processor, and first address interval exceedes double screen screen pixels sum.Three groups of buffer module correspondences write, read, empty three kinds of operator schemes.In the current Vsync signal period, the mode of operation of three groups of buffer modules is different, and when certain group buffer module is write operation, then in next Vsync cycle, same group of buffer module switches to read operation; When certain group buffer module is read operation, then in next Vsync cycle, same group of buffer module switches to null clear operation; When certain group buffer module is null clear operation, then in next Vsync signal period, same group of buffer module switches to write operation.By this kind of buffer module handover mechanism, to ensure that the buffer module of carrying out read operation in current frame period completes write operation within the previous frame cycle, read up-to-date data from this buffer module; The buffer module of carrying out null clear operation in current frame period completes read operation within the previous frame cycle, empties process to this buffer module; The buffer module of carrying out write operation in current frame period completes null clear operation within the previous frame cycle, to this buffer module write present figure data.
First data conversion module, depositing the receivable data stream format of module for reading and writing for all-zero signal being converted to a DDR3SDRAM frame, after the arbitration of multiport DDR3SDRAM controller, being write the buffer module of corresponding clear operation in DDR3SDRAM frame memory device by a DDR3SDRAM module for reading and writing.
Second data conversion module is used for a DDR3SDRAM frame being deposited module for reading and writing and changes through the multiport DDR3SDRAM controller arbitration stream compression that corresponding read operation buffer module reads from DDR3SDRAM frame memory device the digital RGB video signal meeting liquid crystal display driver' s timing standard into.
3rd data conversion module, depositing the receivable data stream format of module for reading and writing for all-zero signal being converted to the 2nd DDR3SDRAM frame, after the arbitration of multiport DDR3SDRAM controller, being write the buffer module of corresponding clear operation in DDR3SDRAM frame memory device by the 2nd DDR3SDRAM module for reading and writing.
4th data conversion module is used for the 2nd DDR3SDRAM frame being deposited module for reading and writing and changes through the multiport DDR3SDRAM controller arbitration stream compression that corresponding read operation buffer module reads from DDR3SDRAM frame memory device the digital RGB video signal meeting liquid crystal display driver' s timing standard into.
To sum up, the present invention is based on the raw system of double screen aniseikania figure of complex programmable device by the graphic operation result of arm processor in complex programmable logic device write DDR3SDRAM frame memory device, first and second DDR3SDRAM Read-write Catrol modules read the draw data of arm processor write from DDR3SDRAM frame memory device, and empty process to the data of write.Arrange six buffer modules in DDR3SDRAM frame memory device altogether, every two buffer modules form one group of corresponding whole screen pixel data.To the write of in DDR3SDRAM frame memory device three groups bufferings, reading, null clear operation with Vsync signal for the cycle is controlled to switch by arm processor, and arbitrated three kinds of operations through multiport DDR3SDRAM controller within a Vsync signal period.The present invention can significantly reduce hardware circuit scale, improves circuit reliability, can complete real-time generation and the display of double screen aniseikania figure, and can support the synchronous dynamic display across screen picture.
Above abundant description is carried out to technical scheme of the present invention; it should be noted that; the specific embodiment of the present invention is not by the restriction of foregoing description; those of ordinary skill in the art adopts equivalents or equivalent transformation and all technical schemes formed according to Spirit Essence of the present invention in structure, method or function etc., all drops within protection scope of the present invention.
Claims (5)
1. a double screen aniseikania Grafmaster, comprises connected complex programmable device and DDR3SDRAM frame memory device, it is characterized in that:
Described complex programmable device comprises arm processor, multiport DDR3SDRAM controller, a DDR3SDRAM frame deposit module for reading and writing, the first data conversion module, the second data conversion module, the 2nd DDR3SDRAM frame deposit module for reading and writing, the 3rd data conversion module, the 4th data conversion module, sequence generation module, and DDR3SDRAM frame memory device comprises the first buffer module, the second buffer module, the 3rd buffer module, the 4th buffer module, the 5th buffer module, the 6th buffer module;
Wherein, multiport DDR3SDRAM controller deposits module for reading and writing with arm processor, a DDR3SDRAM frame, the 2nd DDR3SDRAM frame deposits module for reading and writing, DDR3SDRAM frame memory device is connected; One DDR3SDRAM frame is deposited module for reading and writing and is connected with the first data conversion module, the second data conversion module; 2nd DDR3SDRAM frame is deposited module for reading and writing and is connected with the 3rd data conversion module, the 4th data conversion module; Sequence generation module deposits module for reading and writing with arm processor, a DDR3SDRAM frame, the 2nd DDR3SDRAM frame deposits module for reading and writing, the first data conversion module, the second data conversion module, the 3rd data conversion module, the 4th data conversion module are connected.
2. a kind of double screen aniseikania Grafmaster according to claim 1, is characterized in that: in described DDR3SDRAM frame memory device, the first buffer module and the 4th buffer module, the second buffer module and the 5th buffer module, the 3rd buffer module and the 6th buffer module form double screen pixel data buffer all between two in groups.
3. a kind of double screen aniseikania Grafmaster according to claim 1, is characterized in that: described multiport DDR3SDRAM controller is divided into write to the operation of the first buffer module, the second buffer module, the 3rd buffer module, the 4th buffer module, the 5th buffer module, the 6th buffer module in DDR3SDRAM frame memory device, reads, empties Three models state.
4. a kind of double screen aniseikania Grafmaster according to claim 1, is characterized in that: described multiport DDR3SDRAM controller to the write received, read, empty Three models state and arbitrate and prioritization process.
5. a kind of double screen aniseikania Grafmaster according to claim 4, it is characterized in that: described first data conversion module is used for full zero data to be converted to a DDR3SDRAM Read-write Catrol module acceptable data layout, described second data conversion module is used for converting the data that a DDR3SDRAM Read-write Catrol module reads from DDR3SDRAM to meet VSEA standard digital RGB video form; Described 3rd data conversion module is used for full zero data to be converted to the 2nd DDR3SDRAM Read-write Catrol module acceptable data layout, and described 4th data conversion module is used for converting the data that the 2nd DDR3SDRAM Read-write Catrol module reads from DDR3SDRAM to meet VSEA standard digital RGB video form.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111752504A (en) * | 2019-03-26 | 2020-10-09 | 舜宇光学（浙江）研究院有限公司 | Multi-screen display method and system for electronic equipment, electronic equipment and computer readable medium |
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| US20110260987A1 (en) * | 2010-04-23 | 2011-10-27 | Hon Hai Precision Industry Co., Ltd. | Dual screen electronic device |
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| CN101540144A (en) * | 2008-03-18 | 2009-09-23 | 深圳安凯微电子技术有限公司 | Method, device and system for refreshing double-screen LCD |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111752504A (en) * | 2019-03-26 | 2020-10-09 | 舜宇光学（浙江）研究院有限公司 | Multi-screen display method and system for electronic equipment, electronic equipment and computer readable medium |
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Application publication date: 20160511 |