CN105551944B - The manufacturing method of power transistor - Google Patents
The manufacturing method of power transistor Download PDFInfo
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- CN105551944B CN105551944B CN201510992629.3A CN201510992629A CN105551944B CN 105551944 B CN105551944 B CN 105551944B CN 201510992629 A CN201510992629 A CN 201510992629A CN 105551944 B CN105551944 B CN 105551944B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000002347 injection Methods 0.000 claims abstract description 31
- 239000007924 injection Substances 0.000 claims abstract description 31
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 238000001259 photo etching Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000000034 method Methods 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims abstract description 9
- 230000008569 process Effects 0.000 claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 230000001413 cellular effect Effects 0.000 claims description 13
- 238000002513 implantation Methods 0.000 claims description 7
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- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
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- 230000003628 erosive effect Effects 0.000 claims 2
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 15
- 150000002500 ions Chemical class 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
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- -1 boron ion Chemical class 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The present invention relates to a kind of manufacturing methods of power transistor, including：Field oxide is formed on substrate；From the p-type field limiting ring for forming termination environment；Active area photoetching and the etching for carrying out field oxide, form N+ field oxide masks；Form gate oxide；Form polysilicon gate；Form p-well；N+ injections being carried out as barrier layer using the N+ field oxides mask and being spread, N+ source regions are formed in p-well；Dielectric layer deposited；Contact hole photoetching and etching are carried out, the N+ field oxides mask is removed, forms the contact hole of N+ source regions；Form front metal layer；Form passivation layer；Carry out the back process of power transistor.The present invention reduces photoetching numbers, shorten the device production period to reduce device production cost, production efficiency is improved in addition, the present invention solves the problems, such as that conventionally manufactured middle N+ photoresists mask may pollute semiconductor surface the yield and reliability that improve product due to removing photoresist not clean.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of manufacturing method of power transistor.
Background technology
The markets such as power semiconductor such as VDMOS, IGBT are huge.Competition day is produced and sold in power semiconductor
Beneficial fierce today, power semiconductor Chevron Research Company (CRC) and manufacturing enterprise all suffer from production high performance device and reduce and produce
The immense pressure of cost.
Cellular generally includes p-well injection in power semiconductor active area, N+ injects and P+ injects these three ions note
Enter.Wherein, p-well injection is usually low dose of boron injection (P- injections), and N+ injections are usually arsenic (or phosphorus) note of large dosage
Enter, P+ injections are usually the boron injection of large dosage.And the dosage of General N+injection is more than the dosage of P+ injections, to ensure N+ source regions
Presence.When carrying out N+ injections, stop N+ with the N+ photoresists of a large amount of fritters usually between the polysilicon gate of active area
Injection makes the place for not being photo-etched glue blocking in active area form N+ source regions.There is no the place (photoresist that N+ injects in active area
Lower section), the electric current that contact hole is collected on source electrode is very faint, therefore, in active area does not have the region that N+ injects to form ballast electricity
Resistance.The main function of steady resistance is to prevent power device from so that device is burnt because electric current is excessive because latch-up occurs.Separately
Outside, the N+ photoresists of a large amount of fritters also reduce the effect of Idss electric leakages because of blocking N+ injections.Therefore, active area is by very much
A cellular composition, each cellular include the unimplanted region the region of a bit of N+ injections, a bit of N+, side polycrystalline,
The substrate and back metal, the dielectric layer of top, metal layer and passivation layer below grid oxygen and these regions below polycrystalline.
However, N+ injections using N+ photoresists make mask, photo-mask process of increase itself is needed, it includes gluing, even
Glue, contraposition, exposure, development, development such as examine at the processing steps, in this way, increase manufacturing cost, also increase needed for manufacture when
Between, keep manufacturing speed slow, production efficiency is low.
Another aspect N+ injection makees mask with N+ photoresists, and photoresist is easy to be hardened after being injected due to N+, and with silicon chip knot
Conjunction degree is tighter, so that photoresist is difficult to totally.When removing photoresist not clean, remaining collodion silk can melt in subsequent pyroprocess
Change and pollute semiconductor device surface, the breakdown voltage of device is made to decline, and increase of leaking electricity, room temperature performance and high temperature reliability
It is deteriorated.Sometimes microscopy is difficult to detect collodion silk, is easy missing inspection.It can increase manufacture if even if detecting its reworked processing of collodion silk
Cost makes the manufacturing cycle of chip extend.
Invention content
Based on this, it is necessary to provide a kind of manufacturing method for the power transistor that can be reduced cost, improve production efficiency.
A kind of manufacturing method of power transistor, the power transistor include the termination environment of periphery and are surrounded by termination environment
Active area, the method includes the steps：Field oxide is formed on substrate；Photoetching and the etching of termination environment field limiting ring are carried out,
And by ion implanting and be diffused in the substrate formed termination environment p-type field limiting ring；Carry out the active area light of field oxide
It carves and etching, part field oxide is etched to the N+ field oxide masks for being stopped to ion when N+ is injected；
Gate oxide is formed on the substrate；Polysilicon gate is formed on the gate oxide；Ion implanting and it is diffused in the lining
P-well is formed in bottom；N+ injections being carried out as barrier layer using the N+ field oxides mask and being spread, N+ source regions are formed in p-well；
Dielectric layer deposited on the substrate, polysilicon gate and N+ field oxide masks；Contact hole photoetching and etching are carried out, by the N+
Field oxide mask removes, and forms the contact hole of the N+ source regions；Metal is filled into the contact hole, on the dielectric layer
Form front metal layer；Passivation layer is formed on the front metal layer；Carry out the back process of power transistor.
The cellular of the active area is bar shaped structure cell, N+ field oxidations described in unit cell in one of the embodiments,
Layer mask and the contact hole of the N+ source regions are located between the polysilicon gate of both sides, the multiple N+ be separated from each other
Oxide layer mask is arranged along the contact hole interval.
The cellular of the active area is rectangular structure cell in one of the embodiments, and the polysilicon gate is extremely square
Mount structure, the contact hole and N+ field oxide masks for surrounding the N+ source regions.
In one of the embodiments, the progress contact hole photoetching and etching the step of in, N+ described in unit cell oxygen
The position for changing layer mask is located inside contact hole.
It is the work using thermal oxide in one of the embodiments, in described the step of forming field oxide on substrate
The temperature of skill, thermal oxide is 1000 DEG C -1100 DEG C, and field oxide thickness is 10000 angstroms -20000 angstroms.
It is the work using thermal oxide in one of the embodiments, in described the step of forming gate oxide on substrate
The temperature of skill, thermal oxide is 800 DEG C -900 DEG C, and gate oxide thickness is 500 angstroms -1200 angstroms.
It the ion implanting and is diffused in the substrate in the step of forming p-well, injection in one of the embodiments,
Dosage is 1E13cm-2~1E14cm-2。
Described in one of the embodiments, using the N+ field oxides mask is that barrier layer carries out N+ injections and diffusion
In step, implantation dosage 1E15cm-2~1E16cm-2。
In one of the embodiments, the progress contact hole photoetching and etching the step of in, using dry method after first wet method
Mode perform etching.
The power transistor is that vertical DMOS field-effect is brilliant in one of the embodiments,
Body pipe or insulated gate bipolar transistor.
The manufacturing method of above-mentioned power transistor, by being dexterously used as the mask of N+ injections with field oxide, in profit
N+ field oxide masks are obtained with the active area of field oxide photoetching/etching, reduce photoetching number, to reduce device life
Produce cost.Due to reducing photoetching number, the present invention can simplify production procedure, shorten the device production period, to increase production
The production flux of product improves production efficiency 14.3% (by 7 photoetching of original a whole set of process)~16.7% and (presses original 6 light
Carve), to help to improve yield, improve the cost performance of product.It is covered in addition, the present invention solves conventionally manufactured middle N+ photoresists
Film may due to remove photoresist it is not clean and the problem of polluted to semiconductor surface, avoid breakdown voltage BVdss, the grid source and drain of device
The failure of electric Igss and drain-source electric leakage Idss, improve the yield and reliability of product.
Description of the drawings
Fig. 1 is the schematic diagram of power transistor active area and termination environment in an embodiment；
Fig. 2 is the flow chart of the manufacturing method of power transistor in an embodiment；
Fig. 3 is the sectional view of power transistor after the completion of step S170 in an embodiment；
Fig. 4 is vertical view of the power transistor of bar shaped structure cell in embodiment after the completion of step S190；
Fig. 5 is vertical view of the power transistor of rectangular structure cell in embodiment after the completion of step S190；
Fig. 6 is the sectional view of device after the completion of step S220 in an embodiment.
Specific implementation mode
To facilitate the understanding of the present invention, below with reference to relevant drawings to invention is more fully described.In attached drawing
Give the preferred embodiment of the present invention.But the present invention can realize in many different forms, however it is not limited to this paper institutes
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
Unless otherwise defined, all of technologies and scientific terms used here by the article and belong to the technical field of the present invention
The normally understood meaning of technical staff is identical.Used term is intended merely to description tool in the description of the invention herein
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the Listed Items of pass.
Semiconductor applications vocabulary used herein is the common technical words of those skilled in the art, such as p-type
And P+ type is easily represented the p-type of heavy dopant concentration by N-type impurity to distinguish doping concentration, the P of doping concentration during p-type represents
Type, P-type represent the p-type that concentration is lightly doped, and N+ types represent the N-type of heavy dopant concentration, the N-type of doping concentration, N- during N-type represents
Type represents the N-type that concentration is lightly doped.
Power transistor can be vertical DMOS field-effect transistor (VDMOSFET), insulation
Grid bipolar transistor (IGBT) constant power device, referring to Fig. 1 comprising the termination environment of 100 periphery of active area 100 and active area
200.Fig. 2 is the flow chart of the manufacturing method of power transistor in an embodiment, is included the following steps：
S110 forms field oxide on substrate.
In the present embodiment, it is that after cleaning N- substrates, field oxide is grown by the way of thermal oxide.The temperature of thermal oxide
It it is 1000 DEG C -1100 DEG C, field oxide thickness is
S120, ion implanting and the p-type field limiting ring for being diffused in formation termination environment in substrate.
In the present embodiment, it is to carry out lithography and etching to field oxide (mainly to carry out termination environment p-type field limiting ring photoetching
And etching), then carry out the boron ion injection and diffusion of termination environment P rings (P-ring).
S130 carries out active area photoetching and the etching of field oxide, is formed for stopping to ion when N+ is injected
N+ field oxide masks.
Etching carries out wet etching (BOE) using buffered hydrogen fluoride solution (BHF) in the present embodiment.In other embodiments
It can also using plasma etching progress dry etching.When active area etches, after leaving required field oxide conduct
N+ injects required N+ field oxides mask in continuous S170 steps.
S140 forms gate oxide on substrate.
In the present embodiment, it is that grid oxygen is grown by the way of thermal oxide, the temperature of thermal oxide is 800 DEG C -900 DEG C, shape
At gate oxide thickness beDry oxygen technique may be used in the growth of grid oxygen, and dry and wet can also be used dry (dry
The dry oxygen of oxygen-wet oxygen -) technique.
S150 forms polysilicon gate on gate oxide.
Depositing polysilicon, and carry out polysilicon phosphorus diffusion (can also be in other embodiments to polysilicon carry out phosphorus from
Son injection), photoetching and etching then are carried out to polysilicon, form polysilicon gate.
S160, ion implanting and is diffused in substrate and forms p-well.
Implanting p-type ion is simultaneously spread, and forms p-well.In the present embodiment, implantation dosage 1E13cm-2/~1E14cm-2；
Other suitable implantation dosages can also be selected in other embodiments.
S170 carries out N+ injections as barrier layer using N+ field oxides mask and spreads, forms N+ source regions in p-well.
When the N+ field oxides mask that etching field oxide is formed in step S130 is used as N-type ion implanting in this step
Barrier layer.After injecting and diffuseing to form N+ source regions, the region by N+ field oxides mask blocks without N+ injections can form town
Leakage resistance prevents power transistor from so that device is burnt because electric current is excessive because latch-up occurs.In the present embodiment, N+ injects
Arsenic ion or phosphonium ion, implantation dosage 1E15cm-2~1E16cm-2.The diffusion temperature of N+ diffusions is 900 degree Celsius -1000 and takes the photograph
Family name's degree.
Fig. 3 is the sectional view of power transistor after the completion of step S170, including polysilicon gate 21, gate oxide 22, N+
Field oxide mask 23, N+ source regions 24, p-well 25 and N- layers 26.In the embodiment that power transistor is VDMOSFET, N- layers
26 be N- epitaxial layers；In the embodiment that power transistor is IGBT, N- layers 26 are N- substrates.
In the present embodiment, further include the steps that P+ injections and diffusion.P+ injections are injection boron ions, and implantation dosage is
5.5E14cm-2~5.5E15cm-2.The diffusion temperature of P+ diffusions is 900 degrees Celsius -1000 degrees Celsius.
S180, the dielectric layer deposited on substrate, polysilicon gate and N+ field oxide masks.
In the present embodiment, it is to use chemical vapor deposition phosphorosilicate glass (PSG) as dielectric layer, thickness isIn another embodiment, to may be non-impurity-doped silica glass (USG) compound with PSG for dielectric layer
Layer, the wherein thickness of USG areIn other embodiments, dielectric layer can also be TEOS (ethyl orthosilicate,
The silicon oxide layer of chemical vapor deposition formation is carried out for gas source) with the composite layer of PSG, the wherein thickness of TEOS is
S190 carries out contact hole photoetching and etching, and N+ field oxide masks are removed, and forms the contact hole of N+ source regions.
In the present embodiment, the mode of dry method performs etching after the first wet method of contact hole etching.It will when contact hole etching
Field oxide blockage as N+ field oxide masks etches away, therefore etch period makees N+ field oxidations with photoresist than traditional
The structure etch period of layer mask wants longer (because the overall thickness of dielectric layer and N+ field oxide masks herein is than tradition
Technology is thicker).Using the etching mode of dry method after first wet method for " dielectric layer+field oxide N+ field oxides mask "
Structure can obtain preferable pattern.In other embodiments, contact hole etching can also use individual dry etching.
Fig. 4 is vertical view of the power transistor of bar shaped structure cell in embodiment after the completion of step S190, including
Polysilicon 11, contact hole 12 and N+ field oxides mask 13.It should be noted that can be by N+ oxygen when due to contact hole etching
Change layer mask 13 to remove, therefore N+ field oxides mask 13 is just not present after actually forming contact hole 12, shown in Fig. 4
The only position of N+ field oxides mask 13, therefore be represented by dashed line.Chain-dotted line part is a cellular, wherein cellular 10
Each 11 width of polysilicon gate containing half of the polysilicon of both sides, the reason is that 11 both sides of polysilicon gate respectively contain there are one p-well,
Conducting channel can form conductive mechanism after occurring, and two p-wells belong to different cellulars 10.N+ field oxides mask in cellular 10
The contact hole 12 of 13 and N+ source regions is located between each polysilicon gate 11 of both sides, between this two polysilicon gates 11
The perpendicular bisector (perpendicular bisector of spacing between namely two polysilicon gates 11) in region is used as X-axis, and interval is set in the X-axis direction
It is equipped with multiple N+ field oxides masks 13 being separated from each other, the length of N+ field oxides mask 13 in the X-axis direction in cellular 10
Less than the length of cellular 10 in the X-axis direction, to ensure that source current is sufficiently large.
Fig. 5 is vertical view of the power transistor of rectangular structure cell in embodiment after the completion of step S190, including
Polysilicon 41, contact hole 42 and N+ field oxides mask 43.N+ field oxides mask 43 can be removed when contact hole etching, because
N+ field oxides mask 43 is just not present after this actually forms contact hole 42, and the only N+ field oxides indicated in Fig. 5 are covered
The position of film 43, is represented by dashed line.Polysilicon gate 41 is frame structure, and 42 He of contact hole of N+ source regions is surrounded on cross section
N+ field oxides mask 43.In the present embodiment, the position of N+ field oxides mask 43 is located at the inside of contact hole 42.
S200 fills metal into contact hole, and front metal layer is formed on dielectric layer.
Front metal layer is formed on dielectric layer using sputtering technology, go forward side by side row metal photoetching and etching.After splash-proofing sputtering metal,
Metal is filled up in contact hole, guides source current into transistor total source electrode.In the present embodiment, the thickness of metal layer is 3 micro-
- 5 microns of rice.
S210 forms passivation layer on front metal layer.
In the present embodiment, deposit silicon nitride is as passivation layer, and carries out passivation layer lithography and etching.In the present embodiment
In, the thickness of silicon nitride isIn other embodiments, passivation layer can also be polyimides, thick
Degree is
S220 carries out the back process of power transistor.
It carries out back thinning, back side injection and annealing, the back process such as back metal.
Fig. 6 is the sectional view (passivation layer is omitted) of device after the completion of step S220.Including polysilicon gate 21, gate oxidation
Layer 22, N+ source regions 24, p-well 25, N- layers 26, drain electrode 27, metal layer on back 28, dielectric layer 31 and front metal layer 32.
Power transistor at work, under the action of cut-in voltage, open grid, electronics by the conducting channel in p-well 25
The areas JFET are reached from N+ source regions 24 through conducting channel, drain electrode 27 and back metal are reached through N- layers 26.
The manufacturing method of above-mentioned power transistor, by being dexterously used as the mask of N+ injections, then profit with field oxide
N+ field oxide masks are obtained with the active area of field oxide photoetching/etching, reduce photoetching number, to reduce device life
Produce cost.Due to reducing photoetching number, the present invention can simplify production procedure, shorten the device production period, to increase production
The production flux of product improves production efficiency 14.3% (by 7 photoetching of original a whole set of process)~16.7% and (presses original 6 light
Carve), to help to improve yield, improve the cost performance of product.It is covered in addition, the present invention solves conventionally manufactured middle N+ photoresists
Film may due to remove photoresist it is not clean and the problem of polluted to semiconductor surface, avoid breakdown voltage BVdss, the grid source and drain of device
The failure of electric Igss and drain-source electric leakage Idss, improve the yield and reliability of product.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of manufacturing method of power transistor, the power transistor includes the termination environment of periphery and is surrounded by termination environment
Active area, which is characterized in that the method includes the steps：
Field oxide is formed on N- substrates；
Photoetching and the etching of termination environment field limiting ring are carried out, and by ion implanting and is diffused in formation termination environment in the substrate
P-type field limiting ring；
Carry out field oxide active area photoetching with etching, part field oxide be etched to for when N+ is injected to ion into
The N+ field oxide masks of row blocking；
Gate oxide is formed over the substrate；
Polysilicon gate is formed on the gate oxide；
It ion implanting and is diffused in the substrate and forms p-well；It the ion implanting and is diffused in the substrate and forms p-well
Step carries out after the step of active area photoetching for carrying out field oxide is with etching；
N+ injections being carried out as barrier layer using the N+ field oxides mask and being spread, N+ source regions are formed in p-well；
The dielectric layer deposited on the substrate, polysilicon gate and N+ field oxide masks；
Contact hole photoetching and etching are carried out, the N+ field oxides mask is removed, the contact hole of the N+ source regions is formed；
Metal is filled into the contact hole, front metal layer is formed on the dielectric layer；
Passivation layer is formed on the front metal layer；
Carry out the back process of power transistor.
2. the manufacturing method of power transistor according to claim 1, which is characterized in that the cellular of the active area is item
The contact hole of shape structure cell, the masks of N+ field oxides described in unit cell and the N+ source regions is located at the polysilicon gate of both sides
Between pole, multiple N+ field oxides masks being separated from each other are arranged along the contact hole interval.
3. according to the manufacturing method of power transistor described in claim 1, which is characterized in that the cellular of the active area is rectangular
Structure cell, the polysilicon gate extremely frame structure, surround the contact hole and N+ field oxide masks of the N+ source regions.
4. according to the manufacturing method of the power transistor described in claim 3, which is characterized in that the progress contact hole photoetching and quarter
In the step of erosion, the position of the masks of N+ field oxides described in unit cell is located inside contact hole.
5. according to the manufacturing method of power transistor described in claim 1, which is characterized in that described to form field oxidation on substrate
It is the technique using thermal oxide, the temperature of thermal oxide is 1000 DEG C -1100 DEG C, and field oxide thickness is in the step of layer
10000 angstroms -20000 angstroms.
6. according to the manufacturing method of power transistor described in claim 1, which is characterized in that described to form gate oxidation on substrate
It is the technique using thermal oxide in the step of layer, the temperature of thermal oxide is 800 DEG C -900 DEG C, gate oxide thickness is 500 angstroms -
1200 angstroms.
7. according to the manufacturing method of power transistor described in claim 1, which is characterized in that the ion implanting and be diffused in institute
It states in the step of forming p-well in substrate, implantation dosage 1E13cm-2~1E14cm-2。
8. according to the manufacturing method of power transistor described in claim 1, which is characterized in that described to be covered with the N+ field oxides
Film is implantation dosage 1E15cm in the step of barrier layer carries out N+ injections and spreads-2~1E16cm-2。
9. according to the manufacturing method of power transistor described in claim 1, which is characterized in that the progress contact hole photoetching and quarter
In the step of erosion, performed etching by the way of dry method after first wet method.
10. according to the manufacturing method of power transistor described in claim 1, which is characterized in that the power transistor is vertical
Double-diffused metal oxide semiconductor field-effect transistor or insulated gate bipolar transistor.
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| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
| CN102931090A (en) * | 2012-08-17 | 2013-02-13 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
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| CN102034707A (en) * | 2009-09-29 | 2011-04-27 | 比亚迪股份有限公司 | Method for manufacturing IGBT |
| CN102142372A (en) * | 2010-12-24 | 2011-08-03 | 江苏宏微科技有限公司 | Preparation method of field blocking type bipolar transistor of insulated gate |
| CN102931090A (en) * | 2012-08-17 | 2013-02-13 | 西安龙腾新能源科技发展有限公司 | Manufacturing method for super junction metal oxide semiconductor field effect transistor (MOSFET) |
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