CN105530004B - The acquisition methods and device of pulse width modulation (PWM) control delay time - Google Patents
The acquisition methods and device of pulse width modulation (PWM) control delay time Download PDFInfo
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Abstract
The invention discloses the acquisition methods and device of a kind of pulse width modulation (PWM) control delay time, which comprises receives the first pwm signal and the second pwm signal, and is controlled according to the first pwm signal PWM counter；Sampling interrupt is generated according to the second pwm signal；It is generated according to the zero-acrross ing moment of PWM counter and executes the moment, and attribute value is generated according to the counting direction of PWM counter；Start counter according to Sampling interrupt, and the first delay time is calculated according to the count value of counter；According to the count value of PWM counter and the maximum count value of PWM counter and count the second delay time of period calculating；PWM, which is generated, according to the first delay time and the second delay time controls delay time.The method of the embodiment of the present invention can permit sampling instant, process processing, not have stringent synchronized relation between PWM counter three, also can accurately obtain PWM control delay time, improve flexibility.
Description
Technical field
The present invention relates to control technology field more particularly to the acquisition methods and device of a kind of PWM control delay time.
Background technique
(such as inversion in the engineering based on PWM (Pulse-Width Modulation, pulse width modulation) control
Device, frequency converter etc.), need clearly to know the time (PWM control delay) that " sampling instant " is arrived between " executing the moment ", and pass through
Certain algorithm goes to compensate this delay time, to obtain better real-time control performance.
As shown in Figure 1, in the detection method of the relevant technologies, it is usually that sampling instant, treatment process and PWM.cnt is same
Step, it is hereby achieved that explicitly controlling delay time.In this way, Tdly is exactly PWM control delay, that is, it is equal to PWM cycle.
Fig. 1 show synchronous sequence in the related technology, wherein Texe is the treatment process time, and Tdly is PWM control delay, is equal to
Tpwm.The execution moment refers to that those have been written into the control amount of PWM comparand register, starts to be handled by PWM module, and in phase
Pwm signal is generated on the pin answered.Normally, the execution moment is fixed at PWM counter (PWM.cnt) zero passage.Treatment process
It refers to since " calculate " to " control amount is written to PWM comparand register " whole process.
Obviously, if sampling instant, process processing, there is no stringent synchronized relation between PWM counter this three,
The above method will be unable to directly accurately obtain Tdly.
Summary of the invention
The present invention is directed to solve at least some of the technical problems in related technologies.For this purpose, of the invention
One purpose is the acquisition methods for proposing that a kind of pulse width modulation (PWM) controls delay time, and this method can permit sampling
Moment, process processing do not have stringent synchronized relation between PWM counter this three, can accurately obtain PWM control delay yet
Time improves flexibility.
Second object of the present invention is to propose a kind of acquisition device of pulse width modulation (PWM) control delay time.
To achieve the goals above, the acquisition methods of the PWM control delay time of first aspect present invention embodiment, including
Following steps: the first pwm signal and the second pwm signal are received, and PWM counter is controlled according to first pwm signal
System；Sampling interrupt is generated according to second pwm signal；It is generated according to the zero-acrross ing moment of the PWM counter and executes the moment, and
Attribute value is generated according to the counting direction of the PWM counter；Start counter according to the Sampling interrupt, and according to the meter
The count value of number device and counting period calculate the first delay time；It is counted according to the count value of the PWM counter and the PWM
The maximum count value of device and counting period calculate the second delay time；And prolonged according to first delay time and described second
When the time generate the PWM and control delay time.
The acquisition methods of PWM according to an embodiment of the present invention control delay time can permit sampling instant, at process
There is no stringent synchronized relation between reason, PWM counter this three, this method also can accurately obtain PWM control delay time,
Improve flexibility.
To achieve the goals above, the acquisition device of the PWM control delay time of second aspect of the present invention embodiment, packet
It includes: receiving module, for receiving the first pwm signal and the second pwm signal, and according to first pwm signal to PWM counter
It is controlled；Generation module is interrupted, for generating Sampling interrupt according to second pwm signal；Attribute value generation module, is used for
It is generated according to the zero-acrross ing moment of the PWM counter and executes the moment, and attribute is generated according to the counting direction of the PWM counter
Value；First computing module, for starting counter according to the Sampling interrupt, and according to the count value and counting of the counter
Period calculates the first delay time；Second computing module, for according to the count value of the PWM counter and PWM counting
The maximum count value of device and counting period calculate the second delay time；And delay time computing module, for according to described the
One delay time and second delay time generate the PWM and control delay time.
The acquisition device of PWM according to an embodiment of the present invention control delay time can permit sampling instant, at process
There is no stringent synchronized relation between reason, PWM counter this three, which also can accurately obtain PWM control delay time,
Improve flexibility.
Detailed description of the invention
Fig. 1 is the time diagram at a certain moment in dsp chip operational process in the related technology；
Fig. 2 is the flow chart of the acquisition methods of PWM control delay time according to an embodiment of the invention；
Fig. 3 is the time diagram at a certain moment in dsp chip operational process according to an embodiment of the invention；
Fig. 4 is the flow chart of setting state flag bit according to an embodiment of the invention；
Fig. 5 is the flow chart of generation PWM control delay time according to an embodiment of the invention；
Fig. 6 is the structural schematic diagram of the acquisition device of PWM control delay time according to an embodiment of the invention；
Fig. 7 is the structural schematic diagram of the acquisition device of PWM control delay time in accordance with another embodiment of the present invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
Below with reference to the accompanying drawings 2- Fig. 7 describes the acquisition methods and device of the PWM control delay time of the embodiment of the present invention.
Fig. 2 is the flow chart of the acquisition methods of PWM control delay time according to an embodiment of the invention.Such as Fig. 2 institute
Show, the acquisition methods of the PWM control delay time of the embodiment of the present invention, comprising the following steps:
S101 receives the first pwm signal and the second pwm signal, and is controlled according to the first pwm signal to PWM counter
System.
Below with the PMSM based on FOC (Field-Oriented Control is magnetic field steering control) algorithm
(Permanent Magnet Synchronous Motor) is controlled for engineering.Wherein, DSP (Digital Signal
Processor digital signal processor) chip select TI company TMS320F28335.
Specifically, using EPWM1, EPWM2, EPWM3 of dsp chip generate synchronous pwm signal (i.e. the first pwm signal,
That is the EPWM A in Fig. 3), PWM frequency changes with operating condition.An ADC is triggered every 100us using the EPWM4 of dsp chip
(Analog-to-Digital Converter, analog-digital converter) sampling, i.e. the second pwm signal (i.e. EPWM in Fig. 3
B)。
More specifically, receive the first pwm signal and the second pwm signal, and according to the first pwm signal to PWM counter into
Row control, for example, control PWM counter is opened.
S102 generates Sampling interrupt according to the second pwm signal.
Specifically, Sampling interrupt is generated according to the second pwm signal, i.e. EPWM4, which allows to generate ADC sampling, to be completed to interrupt
(ADC_ISR, that is, sampling instant).
S103 is generated according to the zero-acrross ing moment of PWM counter and is executed the moment, and raw according to the counting direction of PWM counter
At attribute value.
Specifically, as shown in figure 3, the execution moment is set in the zero-acrross ing moment of PWM counter.Attribute value is denoted as DIR, when
When PWM counter counts up, DIR=1 is enabled, when PWM counter counts downwards, enables DIR=0.In addition, PWM counter
Maximum count value (vertex) is set as TBPRD.The counting period of PWM counter is Tp (for example, the count value of PWM counter becomes from 1
To the time used in 2).
Be illustrated in figure 3 asynchronous time diagram, wherein Ta be " sampling instant " arrive " treatment process start time " when
Between be spaced；Texe is " the execution time for the treatment of process " interval；Tw is that " PWM comparand register writes the moment " arrives " executing the moment "
Time interval；Tb is the time interval for arriving " treatment process start time " " executing the moment ".Execute the moment, refer to those by
The control amount of PWM comparand register is written, starts to generate pwm signal by PWMM resume module, and on corresponding pin.Usually
Ground, this moment are fixed at the zero passage of PWM counter (PWM.cnt).Treatment process, refer to since " calculate " to " to
Control amount is written in PWM comparand register " whole process.Wherein, it is generated using the CpuTimer0 module of dsp chip every 100us
One Interruption, and function (TIMER_ISR) middle execution treatment process of breaking wherein.
In addition, enabled interrupt nesting function, and the priority that ADC_ISR is arranged is greater than TIMER_ISR.
S104 starts counter according to Sampling interrupt, and calculates first according to the count value of counter and counting period and prolong
When the time.
In an embodiment of the present invention, the first delay time is time of the sampling instant to treatment process start time.
Specifically, use the CpuTimer1 module in dsp chip as timing module (HwTimer), i.e. counter, use
In calculating the first delay time.Wherein, the counting period of counter is Tc.
More specifically, starting to execute the moment in treatment process, the current count value of counter is saved, then according to counter
Current count value calculate the first delay time.
In one embodiment of the invention, it is calculated by the following formula the first delay time: Ta=HwTimer.Cnt*
Tc, wherein Ta is the first delay time, and HwTimer.Cnt is the count value of counter, and Tc is the counting period of counter.
S105 calculates second according to the count value of PWM counter and the maximum count value of PWM counter and counting period and prolongs
When the time.
In an embodiment of the present invention, the second delay time is treatment process start time to the time for executing the moment.
Specifically, it is calculated by the following formula the second delay time:
Wherein, as DIR=1, Tb=(DIR*TBPRD+TBPRD-PWM.Cnt) * Tp, as DIR=0, Tb=
PWM.Cnt*Tp, wherein Tb is the second delay time, and DIR is attribute value, and the value of DIR is 0 or 1, wherein DIR=1 indicates PWM
Counter counts up, and DIR=0 indicates that PWM counter counts downwards, and TBPRD is the maximum count value of PWM counter,
PWM.Cnt is the count value of PWM counter, and Tp is the counting period of PWM counter.
S106 generates PWM according to the first delay time and the second delay time and controls delay time.
In one embodiment of the invention, PWM control delay is generated according to the first delay time and the second delay time
Time specifically includes:
S1, judge whether the second delay time is less than or equal to the execution time for the treatment of process；
S2, if it is, by the value of the second delay time plus PWM counter counting waves periodic quantity, continue to hold
Row S1；
S3, if it is not, then PWM control delay time be equal to the sum of the first delay time and the second delay time.
Specifically, first determine whether the second delay time Tb is less than or equal to Texe (when the execution for the treatment of process
Between), if it is not, then PWM controls delay time Tdly=Ta+Tb；If it is, enabling Tb=Tb+Tpwm, then proceed to judge Tb
Whether Texe is less than or equal to, if so, continuing to enable Tb=Tb+Tpwm, until Tb > Texe, then according to Tdly=Ta+Tb
Obtain Tdly.Wherein, as shown in figure 3, Tpwm is the periodic quantity of the counting waves of PWM counter.
The acquisition methods of the PWM control delay time of the embodiment of the present invention, can permit sampling instant, process processing, PWM
There is no stringent synchronized relation between this three of counter, this method also can accurately obtain PWM control delay time, improve
Flexibility.
In one embodiment of the invention, in order to guarantee it is correct execute sequence, introduce a state flag bit
(0) StFlg is initialized as, after generating Sampling interrupt according to the second pwm signal, further includes: reading state flag bit；Sentence
Whether disconnected state flag bit is zero；If state flag bit is zero, 1 is revised as by counter zero setting, and by status indicator position.
Specifically, as shown in figure 4, first ADC_ISR (i.e. Sampling interrupt) is waited to generate, state flag bit is first determined whether at this time
It whether is 0；If state flag bit is zero, enabling HwTimer.Cnt (count value of counter) is zero, and by state flag bit
It is revised as 1.
In one embodiment of the invention, prolong according to the first delay time and the generation PWM control of the second delay time
When the time after, further includes: by Status Flag position zero.
Specifically, as shown in figure 5, first determining whether Status Flag is 1 in process processing；If it is, according to working as
Preceding HwTimer.Cnt calculates the first delay time Ta, i.e., Ta is calculated by formula " Ta=HwTimer.Cnt*Tc ".It connects down
Come, Tb is calculated according to formula " Tb=(DIR*TBPRD+TBPRD-PWM.Cnt) * Tp " for the first time.If Tb≤Texe, then repeatedly
Tb=Tb+Tpwm is executed, until Tb > Texe.Then, Tdly is obtained according to " Tdly=Ta+Tb ", finally, by state flag bit
Set 0.
In order to realize above-described embodiment, the present invention also proposes a kind of acquisition device of PWM control delay time.
Fig. 6 is the structural schematic diagram of the acquisition device of PWM control delay time according to an embodiment of the invention.Such as figure
Shown in 6, the acquisition device of the PWM control delay time of the embodiment of the present invention, comprising: receiving module 100 interrupts generation module
200, attribute value generation module 300, the first computing module 400, the second computing module 500 and delay time computing module 600.
Wherein, receiving module 100 is used to receive the first pwm signal and the second pwm signal, and according to the first pwm signal pair
PWM counter is controlled.
Below for controlling engineering based on the PMSM of FOC algorithm.Wherein, dsp chip selects TI company
TMS320F28335。
Specifically, using EPWM1, EPWM2, EPWM3 of dsp chip generate synchronous pwm signal (i.e. the first pwm signal,
That is the EPWM A in Fig. 3), PWM frequency changes with operating condition.An ADC is triggered every 100us using the EPWM4 of dsp chip
(Analog-to-Digital Converter, analog-digital converter) sampling, i.e. the second pwm signal.
More specifically, receiving module 100 receives the first pwm signal and the second pwm signal, and according to the first pwm signal pair
PWM counter is controlled, for example, control PWM counter is opened.
Generation module 200 is interrupted to be used to generate Sampling interrupt according to the second pwm signal.
Specifically, it interrupts generation module 200 and Sampling interrupt is generated according to the second pwm signal, is i.e. EPWM4 allows to generate ADC
Sampling is completed to interrupt (ADC_ISR, that is, sampling instant).
Attribute value generation module 300, which is used to be generated according to the zero-acrross ing moment of PWM counter, executes the moment, and is counted according to PWM
The counting direction of number device generates attribute value.
Specifically, as shown in figure 3, the execution moment is set in the zero-acrross ing moment of PWM counter.Attribute value is denoted as DIR, when
When PWM counter counts up, DIR=1 is enabled, when PWM counter counts downwards, enables DIR=0.In addition, PWM counter
Maximum count value (vertex) is set as TBPRD.The counting period of PWM counter is Tp.
Be illustrated in figure 3 asynchronous time diagram, wherein Ta be " sampling instant " arrive " treatment process start time " when
Between be spaced；Texe is " the execution time for the treatment of process " interval；Tw is that " PWM comparand register writes the moment " arrives " executing the moment "
Time interval；Tb is the time interval for arriving " treatment process start time " " executing the moment ".Execute the moment, refer to those by
The control amount of PWM comparand register is written, starts to generate pwm signal by PWMM resume module, and on corresponding pin.Usually
Ground, this moment are fixed at the zero passage of PWM counter (PWM.cnt).Treatment process, refer to since " calculate " to " to
Control amount is written in PWM comparand register " whole process.Wherein, it is generated using the CpuTimer0 module of dsp chip every 100us
One Interruption, and function (TIMER_ISR) middle execution treatment process of breaking wherein.
In addition, enabled interrupt nesting function, and the priority that ADC_ISR is arranged is greater than TIMER_ISR.
First computing module 400 is used to start counter according to Sampling interrupt, and according to the count value and counting of counter
Period calculates the first delay time.
In an embodiment of the present invention, the first delay time is time of the sampling instant to treatment process start time.
Specifically, use the CpuTimer1 module in dsp chip as timing module (HwTimer), i.e. counter, use
In calculating the first delay time.Wherein, the counting period of counter is Tc.
More specifically, starting to execute the moment in treatment process, the current count value of counter is saved, then first calculates mould
Block 400 calculates the first delay time according to the current count value of counter.
In one embodiment of the invention, the first computing module 400 is calculated by the following formula the first delay time: Ta
=HwTimer.Cnt*Tc, wherein Ta is the first delay time, and HwTimer.Cnt is the count value of counter, and Tc is counter
The counting period.
Second computing module 500 is used for according to the count value of PWM counter and the maximum count value and counting of PWM counter
Period calculates the second delay time.
In an embodiment of the present invention, the second delay time is treatment process start time to the time for executing the moment.
In one embodiment of the invention, the second computing module 500 is calculated by the following formula the second delay time:
Wherein, as DIR=1, Tb=(DIR*TBPRD+TBPRD-PWM.Cnt) * Tp, as DIR=0, Tb=
PWM.Cnt*Tp, wherein Tb is the second delay time, and DIR is attribute value, and the value of DIR is 0 or 1, wherein DIR=1 indicates PWM
Counter counts up, and DIR=0 indicates that PWM counter counts downwards, and TBPRD is the maximum count value of PWM counter,
PWM.Cnt is the count value of PWM counter, and Tp is the counting period of PWM counter.
Delay time computing module 600 is used to generate PWM control delay according to the first delay time and the second delay time
Time.
In one embodiment of the invention, delay time computing module 600 is specifically used for: judging that the second delay time is
The no execution time less than or equal to treatment process, if it is not, then PWM control delay time is equal to the first delay time and the
The sum of two delay times, if it is, by the value of the second delay time plus the periodic quantity of the counting waves of PWM counter, directly
It is greater than the execution time for the treatment of process to the second delay time.
Specifically, delay time computing module 600 first determines whether the second delay time Tb is less than or equal to Texe
(the execution time for the treatment of process), if it is not, then PWM controls delay time Tdly=Ta+Tb；If it is, enabling Tb=Tb+
Tpwm then proceedes to judge whether Tb is less than or equal to Texe, if so, continue to enable Tb=Tb+Tpwm, until Tb > Texe,
Then Tdly is obtained according to Tdly=Ta+Tb.
The acquisition device of the PWM control delay time of the embodiment of the present invention, can permit sampling instant, process processing, PWM
There is no stringent synchronized relation between this three of counter, which also can accurately obtain PWM control delay time, improve
Flexibility.
In one embodiment of the invention, in order to guarantee it is correct execute sequence, introduce a state flag bit
(0) StFlg is initialized as, as shown in fig. 7, the acquisition device of PWM control delay time, further includes: read module 700, judgement
Module 800 and modified module 900.
Wherein, read module 700 is used for after interrupting generation module 200 according to the second pwm signal generation Sampling interrupt
Reading state flag bit；Judgment module 800 is for judging whether state flag bit is zero；Modified module 900 is used in state mark
By counter zero setting when will position is zero, and status indicator position is revised as 1.
Specifically, first ADC_ISR (i.e. Sampling interrupt) is waited to generate, at this time the reading state mark first of read module 700
Position, judgment module 800 judge whether state flag bit is 0；If state flag bit is zero, modified module 900 ifs, is enabled
HwTimer.Cnt (count value of counter) is zero, and state flag bit is revised as 1.
In one embodiment of the invention, modified module 900 is also used to: in delay time computing module 600 according to
After one delay time and the second delay time generate PWM control delay time, by Status Flag position zero.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include at least one this feature.In the description of the present invention, the meaning of " plurality " is at least two, such as two, three
It is a etc., unless otherwise specifically defined.
Any process described otherwise above or method description are construed as in flow chart or herein, and expression includes
It is one or more for realizing specific logical function or process the step of executable instruction code module, segment or portion
Point, and the range of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discussed suitable
Sequence, including according to related function by it is basic simultaneously in the way of or in the opposite order, Lai Zhihang function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
Expression or logic and/or step described otherwise above herein in flow charts, for example, being considered use
In the order list for the executable instruction for realizing logic function, may be embodied in any computer-readable medium, for
Instruction execution system, device or equipment (such as computer based system, including the system of processor or other can be held from instruction
The instruction fetch of row system, device or equipment and the system executed instruction) it uses, or combine these instruction execution systems, device or set
It is standby and use.For the purpose of this specification, " computer-readable medium ", which can be, any may include, stores, communicates, propagates or pass
Defeated program is for instruction execution system, device or equipment or the dress used in conjunction with these instruction execution systems, device or equipment
It sets.The more specific example (non-exhaustive list) of computer-readable medium include the following: there is the electricity of one or more wirings
Interconnecting piece (electronic device), portable computer diskette box (magnetic device), random access memory (RAM), read-only memory
(ROM), erasable edit read-only storage (EPROM or flash memory), fiber device and portable optic disk is read-only deposits
Reservoir (CDROM).In addition, computer-readable medium can even is that the paper that can print described program on it or other are suitable
Medium, because can then be edited, be interpreted or when necessary with it for example by carrying out optical scanner to paper or other media
His suitable method is handled electronically to obtain described program, is then stored in computer storage.
It should be appreciated that each section of the invention can be realized with hardware, software, firmware or their combination.Above-mentioned
In embodiment, software that multiple steps or method can be executed in memory and by suitable instruction execution system with storage
Or firmware is realized.It, and in another embodiment, can be under well known in the art for example, if realized with hardware
Any one of column technology or their combination are realized: having a logic gates for realizing logic function to data-signal
Discrete logic, with suitable combinational logic gate circuit specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
Those skilled in the art are understood that realize all or part of step that above-described embodiment method carries
It suddenly is that relevant hardware can be instructed to complete by program, the program can store in a kind of computer-readable storage medium
In matter, which when being executed, includes the steps that one or a combination set of embodiment of the method.
It, can also be in addition, each functional unit in each embodiment of the present invention can integrate in a processing module
It is that each unit physically exists alone, can also be integrated in two or more units in a module.Above-mentioned integrated mould
Block both can take the form of hardware realization, can also be realized in the form of software function module.The integrated module is such as
Fruit is realized and when sold or used as an independent product in the form of software function module, also can store in a computer
In read/write memory medium.
Storage medium mentioned above can be read-only memory, disk or CD etc..Although having been shown and retouching above
The embodiment of the present invention is stated, it is to be understood that above-described embodiment is exemplary, and should not be understood as to limit of the invention
System, those skilled in the art can be changed above-described embodiment, modify, replace and become within the scope of the invention
Type.
Claims (14)
1. a kind of acquisition methods of pulse width modulation (PWM) control delay time, which comprises the following steps:
The first pwm signal and the second pwm signal are received, and PWM counter is controlled according to first pwm signal；
Sampling interrupt is generated according to second pwm signal；
It is generated according to the zero-acrross ing moment of the PWM counter and executes the moment, and generated according to the counting direction of the PWM counter
Attribute value；
Start counter according to the Sampling interrupt, and according to the count value of the counter and counts the first delay of period calculating
Time；
Second is calculated according to the count value of the PWM counter and the maximum count value of the PWM counter and counting period to prolong
When the time；And
The PWM, which is generated, according to first delay time and second delay time controls delay time.
2. the acquisition methods of PWM control delay time as described in claim 1, which is characterized in that wherein, first delay
Time is time of the sampling instant to treatment process start time, and second delay time is the treatment process start time
To the time for executing the moment.
3. the acquisition methods of PWM control delay time as claimed in claim 2, which is characterized in that be calculated by the following formula
First delay time:
Ta=HwTimer.Cnt*Tc,
Wherein, Ta is first delay time, and HwTimer.Cnt is the count value of the counter, and Tc is the counter
The counting period.
4. the acquisition methods of PWM control delay time as claimed in claim 2, which is characterized in that be calculated by the following formula
Second delay time:
Wherein, as DIR=1, Tb=(DIR*TBPRD+TBPRD-PWM.Cnt) * Tp,
As DIR=0, Tb=PWM.Cnt*Tp,
Wherein, Tb is second delay time, and DIR is the attribute value, and the value of DIR is 0 or 1, wherein DIR=1 indicates institute
PWM counter is stated to count up, DIR=0 indicates that the PWM counter counts downwards, TBPRD be the PWM counter most
Counter value, PWM.Cnt are the count value of the PWM counter, and Tp is the counting period of the PWM counter.
5. the acquisition methods of PWM control delay time as claimed in claim 2, which is characterized in that described according to described first
Delay time and second delay time generate the PWM and control delay time, specifically include:
S1, judge whether second delay time is less than or equal to the execution time of the treatment process；
S2, if it is, by the value of second delay time plus the PWM counter counting waves periodic quantity, after
It is continuous to execute S1；
S3, if it is not, then PWM control delay time be equal to first delay time and second delay time it
With.
6. the acquisition methods of PWM as described in claim 1 control delay time, which is characterized in that described according to described the
Two pwm signals generate after Sampling interrupt, further includes:
Reading state flag bit；
Judge whether the state flag bit is zero；
If the state flag bit is zero, 1 is revised as by the counter zero setting, and by the state flag bit.
7. the acquisition methods of PWM as claimed in claim 6 control delay time, which is characterized in that described according to described the
One delay time and second delay time generate after the PWM control delay time, further includes:
By the Status Flag position zero.
8. a kind of acquisition device of pulse width modulation (PWM) control delay time characterized by comprising
Receiving module counts PWM for receiving the first pwm signal and the second pwm signal, and according to first pwm signal
Device is controlled；
Generation module is interrupted, for generating Sampling interrupt according to second pwm signal；
Attribute value generation module executes the moment for generating according to the zero-acrross ing moment of the PWM counter, and according to the PWM
The counting direction of counter generates attribute value；
First computing module, for starting counter according to the Sampling interrupt, and according to the count value and meter of the counter
One number time calculates the first delay time；
Second computing module, by according to the count value of the PWM counter and the maximum count value of the PWM counter and based on
One number time calculates the second delay time；And
Delay time computing module is controlled for generating the PWM according to first delay time and second delay time
Delay time processed.
9. the acquisition device of PWM control delay time as claimed in claim 8, which is characterized in that wherein, first delay
Time is time of the sampling instant to treatment process start time, and second delay time is the treatment process start time
To the time for executing the moment.
10. the acquisition device of PWM control delay time as claimed in claim 9, which is characterized in that the first computing module passes through
Following formula calculates first delay time:
Ta=HwTimer.Cnt*Tc,
Wherein, Ta is first delay time, and HwTimer.Cnt is the count value of the counter, and Tc is the counter
The counting period.
11. the acquisition device of PWM control delay time as claimed in claim 9, which is characterized in that the second computing module passes through
Following formula calculates second delay time:
Wherein, as DIR=1, Tb=(DIR*TBPRD+TBPRD-PWM.Cnt) * Tp,
As DIR=0, Tb=PWM.Cnt*Tp, wherein Tb is second delay time, and DIR is the attribute value, DIR's
Value is 0 or 1, wherein DIR=1 indicates that the PWM counter counts up, and DIR=0 indicates that the PWM counter is counted downwards
Number, TBPRD are the maximum count value of the PWM counter, and PWM.Cnt is the count value of the PWM counter, and Tp is described
The counting period of PWM counter.
12. the acquisition device of PWM control delay time as claimed in claim 9, which is characterized in that the delay time calculates
Module is specifically used for:
Judge whether second delay time is less than or equal to the execution time of the treatment process, if it is not, then described
PWM controls delay time and is equal to the sum of first delay time and second delay time, if it is, by described second
The value of delay time adds the periodic quantity of the counting waves of the PWM counter, until second delay time is greater than described
The execution time for the treatment of process.
13. the acquisition device of PWM control delay time as claimed in claim 8, which is characterized in that further include:
Read module, for reading shape after the interruption generation module generates Sampling interrupt according to second pwm signal
State flag bit；
Judgment module, for judging whether the state flag bit is zero；
Modified module, for being repaired when the state flag bit is zero by the counter zero setting, and by the state flag bit
It is changed to 1.
14. the acquisition device of PWM control delay time as claimed in claim 13, which is characterized in that the modified module, also
For:
The PWM is generated according to first delay time and second delay time in the delay time computing module to control
After delay time processed, by the Status Flag position zero.
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| CN112904771A (en) * | 2021-01-19 | 2021-06-04 | 厦门欧万精密科技有限公司 | DSP hardware sampling delay compensation method and device based on PWM synchronization mechanism |
| CN113206657B (en) * | 2021-03-24 | 2022-09-16 | 珠海泰为电子有限公司 | PWM signal generation method and device of PFC circuit, storage medium and electronic equipment |
| CN113568339B (en) * | 2021-07-15 | 2023-03-21 | 许继电气股份有限公司 | Converter fixed time delay control method and device |
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| US5793234A (en) * | 1995-05-22 | 1998-08-11 | Lg Semicon Co., Ltd. | Pulse width modulation circuit |
| CN1205465A (en) * | 1997-03-25 | 1999-01-20 | 日本电气株式会社 | Pulse width modulation control which data transfer is inhibited by overflow signal |
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| KR100935440B1 (en) * | 2007-05-09 | 2010-01-06 | 삼성전자주식회사 | PWM data processing apparatus for reducing current consumption by controlling data offset, and Method thereof |
| JP5165463B2 (en) * | 2008-05-28 | 2013-03-21 | ルネサスエレクトロニクス株式会社 | PWM control apparatus and pulse waveform control method |
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| US5793234A (en) * | 1995-05-22 | 1998-08-11 | Lg Semicon Co., Ltd. | Pulse width modulation circuit |
| CN1205465A (en) * | 1997-03-25 | 1999-01-20 | 日本电气株式会社 | Pulse width modulation control which data transfer is inhibited by overflow signal |
| CN101796712A (en) * | 2007-09-25 | 2010-08-04 | 株式会社大亨 | Pwm signal generator, and inverter equipped with this PWM signal generator |
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