CN105518853A - 嵌入式电子封装和相关联的方法 - Google Patents

嵌入式电子封装和相关联的方法 Download PDF

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CN105518853A
CN105518853A CN201480049617.0A CN201480049617A CN105518853A CN 105518853 A CN105518853 A CN 105518853A CN 201480049617 A CN201480049617 A CN 201480049617A CN 105518853 A CN105518853 A CN 105518853A
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lcp
semiconductor die
main body
conductive pole
interconnection layer
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CN105518853B (zh
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路易斯·约瑟夫·小伦代克
迈克尔·R·韦瑟斯庞
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L3 Hershey Technology Co
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Harris Corp
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Abstract

电子封装包含半导体裸片(60)、从所述半导体裸片向外延伸的导电柱(62)以及液晶聚合物(LCP)主体(74)，所述液晶聚合物主体包围所述半导体裸片且具有在其中接纳所述导电柱中的对应导电柱的开口(77)。第一互连层(80)在所述LCP主体上且接触所述开口。导电主体(82)在所述开口中以将所述导电柱连接到所述第一互连层。

Description

嵌入式电子封装和相关联的方法
技术领域
本发明涉及封装电子组件的领域，并且更具体来说，涉及封装嵌入式半导体裸片以及相关方法。
背景技术
封装电子组件的基本目的是为了保护组件且同时通过封装从组件中提供电气互连。可制造性和保护是关键问题。由于持续增长的市场需求，电子封装不断地朝向较小尺寸和减小的占用面积而同时仍保持环境稳固发展。尽管这些电子封装是小型化的，但是它们仍然是高度功能性的。
嵌入式电子封装集成需要具有相容的处理温度、相容的材料特性以及有利的电特性的介电材料。当前，若干嵌入式技术已经展示为使用层合板和聚合物电路板。
因特尔公司(IntelCorporation)已经研发出无焊内建层，其不使用焊接凸点来将半导体裸片附接到封装线。内建层围绕半导体裸片形成或内建。内建层通常单独地制造且随后粘合在一起。ImberaElectronicsOY已经研发出集成模块板(IMB)，其中待嵌入的组件具有在所述组件的两侧上的接触端子，因此节约空间。通用电气公司(GeneralElectricCompany)具有ChipsFirstBuild-UpTM，其中使用无焊过程。弗劳恩霍夫IZM(FraunhoferIZM)基于标准电路板设备和技术使用层合嵌入式裸片“聚合物内芯片”封装方法，其中半导体裸片粘合到衬底、与介电质层合，且连接到外部电路。卡西欧计算机有限公司(CasioComputerCo.Ltd.)使用晶片级封装(WLP)，其中所述封装直接在晶片上完成且随后通过切割而单体化以用于组装。裸片的所有封装和测试操作由整个晶片制造和晶片级测试替代。
上述方法均无法利用液晶聚合物材料(LCP)，所述液晶聚合物材料自从在2003年变得可商购后已经获得相当大的注意。LCP材料具有非常低的透湿性且可以提供近气密密封而不会相对较厚。此外，LCP材料的介电特性在暴露于湿气下时不会发生改变。
在Thompson等人的标题为《多层LCP衬底中的MMIC的封装(PackagingofMMICsinMultilayerLCPSubstrates)》的文章中揭示了用于保护半导体裸片的LCP封装。如图1中所说明，电子封装20包含使用具有用于半导体裸片的经切开空腔50的层合工艺嵌入在LCP层30到42之间的半导体裸片22。
LCP核心层30、34、38和42是4密耳厚，而LCP粘合层32、36和40是2密耳厚。如在所述文章中所论述，低熔解温度(285℃)LCP粘合层32、36和40用于粘附大体上较厚较高熔解温度(315℃)LCP核心层30、34、38和42以产生均质的LCP电子封装20。
即使鉴于上述技术，出现的无线通信和传感器应用也需要超薄的、柔性的、耐化学的、近气密的且买得起的嵌入式电子封装。当涉及例如生物医学感测和成像时尤其如此。因此，仍需要改进将半导体裸片嵌入在电子封装中的技术。
发明内容
鉴于前述背景，本发明的目标因此是提供一种低剖面电子封装，其具有相对较简单地产生的嵌入式半导体裸片。
根据本发明的此目标、特征和优点以及其它目标、特征和优点通过一种电子封装提供，所述电子封装包括半导体裸片、从半导体裸片向外延伸的多个导电柱以及液晶聚合物(LCP)主体，所述液晶聚合物主体包围半导体裸片且具有在其中的多个开口，所述开口接纳多个导电柱中的对应导电柱，同时使对应的间隙与导电柱的顶部相邻。第一互连层可以在LCP主体上，且多个导电主体可以在对应的间隙中以将多个导电柱连接到第一互连层。
所述电子封装可以进一步包括在LCP主体上在其与第一互连层相反的一侧上的第二互连层。多个导电通孔可以延伸穿过LCP主体以连接第一和第二互连层。
LCP主体有利地允许电子封装为低剖面且具有高灵活性的以用于应用在共形电路中。半导体裸片可以是近气密密封的，且LCP主体的介电特性在暴露于湿气下时仍相对不变。并且，因为LCP封装与人体生物相容，所以所述电子封装具有广泛范围的手术植入应用。
所述电子封装的又另一个优点是它可以用作用于更加复杂的架构的构建块，其中LCP主体可以一个在另一个上面的方式堆叠，同时仍提供经堆叠层中的半导体裸片之间的电气接口。这在半导体裸片并不处于丝焊或倒装芯片配置的情况下实现。替代地，在LCP主体已经围绕半导体裸片形成之后，导电主体有利地将导电柱连接到第一互连层，且导电通孔有利地将第一和第二互连层连接在一起。导电柱和导电通孔可以使用电镀形成。因此，电子封装以减少的成本相对较简单地产生。
LCP主体可以在半导体裸片的所有侧上包围半导体裸片且与其连续接触。另外，LCP主体可以侧向包围导电柱中的每一个且与其连续接触。
第一互连层、导电柱以及导电主体可以各自包含例如铜。半导体裸片可以包括例如射频(RF)集成电路。
另一个方面涉及一种用于制造电子封装的方法，其包括：提供半导体裸片，其具有多个向外延伸的导电柱；以及形成LCP主体，其包围半导体裸片且具有在其中的多个开口，所述开口接纳多个导电柱中的对应导电柱，同时使对应的间隙与导电柱的顶部相邻，且所述LCP主体具有在LCP主体上的第一互连层。所述方法可以进一步包括在对应的间隙中形成多个导电主体以将多个导电柱连接到第一互连层。
附图说明
图1是根据现有技术的电子封装的截面视图。
图2是根据本发明的电子封装的截面视图。
图3是图2中的区域A的放大截面视图。
图4是图2中的电子封装的分解截面视图，其说明具有裸片接纳空腔的第一LCP主体区段、半导体裸片以及第二LCP主体区段。
图5是没有导电柱和导电通孔的在图2中说明的电子封装的截面视图。
图6是具有在于第一互连层上形成互连轨迹(trace)之前处于适当的位置处的导电柱和导电通孔的在图2中说明的电子封装的截面视图。
图7是说明用于制造图2中说明的电子封装的方法的流程图。
具体实施方式
现在将参考附图在下文中更加全面地描述本发明，在这些附图中示出了本发明的优选实施例。然而，本发明可以按许多不同形式实施，并且不应被解释为限于本文所阐述的实施例。更准确地说，提供这些实施例是为了使得本发明将是透彻并且完整的，并且这些实施例将把本发明的范围完整地传达给所属领域的技术人员。相同数字始终指代相同元件。
首先参考图2和3，电子封装50包括半导体裸片60、从半导体裸片向外延伸的多个导电柱62以及包围半导体裸片60的液晶聚合物(LCP)主体70。LCP主体70具有在其中的多个开口77，所述开口接纳多个导电柱62中的对应导电柱，同时使对应的间隙与导电柱的顶部相邻。第一互连层80在LCP主体70上。多个导电主体82在对应的间隙中以将导电柱62连接到第一互连层80。
如下文将更详细地解释，LCP主体70包含第一LCP主体区段72和第二LCP主体区段74，所述第二LCP主体区段在熔合接口76处与第一LCP主体区段接合。作为实例，LCP主体50的总厚度可以在8到12密耳的范围内。取决于半导体裸片60的厚度和既定应用，LCP主体70的厚度将相应地改变，如所属领域的技术人员容易地了解。
除电子封装50为低剖面且具有高灵活性之外，半导体裸片60可以是近气密密封的，且LCP主体70的介电特性在暴露于湿气下时仍相对较稳定。并且，因为LCP主体70与人体生物相容，所以电子封装50具有广泛范围的手术植入应用，例如具有医师可访问远程监控***的无线起搏器或可植入视网膜假体。
电子封装50进一步包含在LCP主体上在其与第一互连层80相反的一侧上的第二互连层90。导电通孔100延伸穿过LCP主体70以连接第一和第二互连层80、90。此配置有利地准许将电子封装50用作用于更加复杂架构的构建块，其中LCP主体70可以一个在另一个上面的方式堆叠，同时仍提供经堆叠层中的半导体裸片60之间的电气接口。组装成本减少且制造的容易性得到改进，因为提供了与半导体裸片60之间的电气接口，而不必使半导体裸片处于丝焊或倒装芯片配置。
现在参考其余图式，包含图7中说明的流程图300，将论述制造所说明的电子封装50的步骤。从开始(框302)起，具有多个向外延伸的导电柱62的半导体裸片60提供在304框处且如通过图4中的电子封装50的分解视图所说明。导电柱62是例如铜，且用于对准和随后的互连目的。其它金属可以用于替代铜或可以与铜一起使用，如所属领域的技术人员容易地了解。半导体裸片60可以是例如射频(RF)集成电路。
第一LCP主体区段72包含具有裸片接纳空腔79的第一LCP层112，提供在框306处。尽管第一LCP层112说明为单一LCP层，但多个LCP层通过被使用。在框308处，半导体裸片60定位在裸片接纳空腔79中，其中多个导电柱62延伸远离裸片接纳空腔。
第二LCP主体区段74提供在框310处且包含第二LCP层114，且第一互连层80在第二LCP层上，其中多个开口或通孔77延伸穿过第一互连层和第二LCP层两者。激光可以用于形成开口77。第一互连层80是例如铜。其它金属可以用于替代铜或可以与铜一起使用，如所属领域的技术人员容易地了解。如同第一LCP层112一样，第二LCP层114可以形成有单一或多个LCP层。
在框312处，第二LCP主体区段74中的开口77与导电柱62对准。从半导体裸片60向外延伸的导电柱62有利地用于对准和互连目的。参考图5，在314框处，第一和第二LCP主体区段72、74随后接合在一起，其中第二LCP主体区段中的多个开口77接纳导电柱62中的对应导电柱以使对应的间隙97与导电柱62的顶部相邻。导电柱62因此凹进开口77中。
第一和第二LCP主体区段72、74与其间包含的半导体裸片60层合，使得LCP主体70在半导体裸片60的所有侧上包围所述半导体裸片且与其连续接触。并且，LCP主体70侧向包围导电柱62中的每一个且与其连续接触。
在第一和第二LCP主体区段72、74中的LCP层112、114连同半导体裸片60的层合在约285℃到315℃的温度范围内实现，如所属领域的技术人员容易地了解。如图5中所说明，形成熔合接口76，其中LCP层112、114接合在一起。
在框316处，第二互连层90形成于第一LCP主体区段72中的LCP层112上，且在LCP层112的与第二LCP主体区段74中的LCP层114相反的一侧上。第二互连层90也是铜。然而，其它金属可以用于替代铜或可以与铜一起使用，如所属领域的技术人员容易地了解。第二互连层90可以在第一和第二LCP层112、114的层合之前形成，而非在所述层合之后形成。举例来说，框306还可以包含提供第一LCP主体区段72以将LCP层112和第二互连层90包含在其上。
在第一和第二LCP主体区段72、74的层合之后，在框318处且如图5中所说明，使用通过第一和第二LCP主体区段72、74的激光形成通孔或贯通孔99。另外，激光还可以用于清洁、铣削和重新界定第二LCP主体区段74中的开口77中的对应的间隙。
在320框处且如图6中所说明，导电主体82形成于对应的间隙97中以将导电柱62连接到第一互连层80，且形成导电通孔100，其延伸穿过第一和第二LCP主体区段72、74以连接第一和第二互连层80、90。如上文所提到，导电柱62和第一和第二互连层80、90是铜。导电主体82和导电通孔100使用电镀铜形成。在电镀之后，如图2中所说明的互连轨迹130经蚀刻界定以完成电子封装50，如所属领域的技术人员容易地了解。所述方法在框322处结束。
所属领域的技术人员将想到本发明的许多修改及其它实施例，其具有前述描述和相关联的图式中所呈现的教示内容的益处。因此，应理解，本发明不限于所揭示的具体实施例并且意图将修改和实施例包含于所附权利要求书的范围内。

Claims (10)

1.一种电子封装，其包括：
半导体裸片；
多个导电柱，其从所述半导体裸片向外延伸；
液晶聚合物(LCP)主体，其包围所述半导体裸片且具有在其中的多个开口，所述开口接纳所述多个导电柱中的对应导电柱，同时使对应的间隙与所述导电柱的顶部相邻；
在所述LCP主体上的第一互连层；以及
在所述对应的间隙中的多个导电主体，其用于将所述多个导电柱连接到所述第一互连层。
2.根据权利要求1所述的电子封装，其进一步包括：
在所述LCP主体上在其与所述第一互连层相反的一侧上的第二互连层；以及
多个导电通孔，其延伸穿过所述LCP主体以连接所述第一和第二互连层。
3.根据权利要求1所述的电子封装，其中所述LCP主体在所述半导体裸片的所有侧上包围所述半导体裸片且与其连续接触，并且其中所述LCP主体侧向包围所述多个导电柱中的每一个且与其连续接触。
4.根据权利要求1所述的电子封装，其中所述第一互连层、所述多个导电柱以及所述多个导电主体各自包括铜。
5.根据权利要求1所述的电子封装，其中所述LCP主体包括：
第一LCP主体区段，其具有接纳所述半导体裸片的裸片接纳空腔；以及
第二LCP主体区段，其具有在其中的所述多个开口且在熔合接口处与所述第一LCP主体区段接合。
6.一种用于制造电子封装的方法，其包括：
提供半导体裸片，其具有多个向外延伸的导电柱；
形成液晶聚合物(LCP)主体，其包围所述半导体裸片且具有在其中的多个开口，所述开口接纳所述多个导电柱中的对应导电柱，同时使对应的间隙与所述导电柱的顶部相邻，且所述液晶聚合物主体具有在所述LCP主体上的第一互连层；以及
在所述对应的间隙中形成多个导电主体以将所述多个导电柱连接到所述第一互连层。
7.根据权利要求6所述的方法，其中形成所述LCP主体包括：
提供第一LCP主体区段，其具有接纳所述半导体裸片的裸片接纳空腔，所述半导体裸片具有延伸远离所述裸片接纳空腔的所述多个向外延伸的导电柱；
提供第二LCP主体区段，其包括LCP层，所述LCP层具有在其上的所述第一互连层，且具有延伸穿过所述第一互连层和所述LCP层两者的所述多个开口；
使所述第二LCP主体区段中的所述多个开口与所述多个导电柱对准；以及
在熔合接口处将所述第一和第二LCP主体区段接合在一起。
8.根据权利要求6所述的方法，其进一步包括
在所述LCP主体上在其与所述第一互连层相反的一侧上形成第二互连层；以及
形成多个导电通孔，其延伸穿过所述LCP主体以连接所述第一和第二互连层。
9.根据权利要求6所述的方法，其中所述LCP主体经形成以在所述半导体裸片的所有侧上包围所述半导体裸片且与其连续接触，并且其中所述LCP主体经形成以侧向包围所述多个导电柱中的每一个且与其连续接触。
10.根据权利要求6所述的方法，其中所述第一互连层和所述多个导电柱各自包括铜，并且其中所述多个导电主体各自包括电镀铜。
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US20200111765A1 (en) * 2018-10-09 2020-04-09 Medtronic, Inc. Electronic assembly and method of forming same
FR3089423B1 (fr) * 2018-12-07 2020-12-18 Commissariat Energie Atomique Dispositif médical implantable à architecture améliorée
JP7353255B2 (ja) * 2020-10-30 2023-09-29 三菱電機株式会社 半導体装置用の筐体の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050087356A1 (en) * 2002-11-08 2005-04-28 Robert Forcier Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US20090085190A1 (en) * 2007-09-28 2009-04-02 Juergen Simon Semiconductor Device and Method for Making Same
US20100140772A1 (en) * 2008-12-08 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound
US20110241215A1 (en) * 2010-04-02 2011-10-06 Sankman Robert L Embedded semiconductive chips in reconstituted wafers, and systems containing same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49131863U (zh) 1973-03-10 1974-11-13
JPS60127270A (ja) * 1983-12-09 1985-07-06 株式会社日立製作所 セラミックス複合部材の製造法
US5353498A (en) 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
US5866952A (en) 1995-11-30 1999-02-02 Lockheed Martin Corporation High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate
US6396148B1 (en) 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
JP2002231762A (ja) 2001-02-01 2002-08-16 Toppan Forms Co Ltd Ｉｃチップの実装方法とｉｃチップ実装体
US6952046B2 (en) 2002-06-19 2005-10-04 Foster-Miller, Inc. Electronic and optoelectronic component packaging technique
JP2004111676A (ja) * 2002-09-19 2004-04-08 Toshiba Corp 半導体装置、半導体パッケージ用部材、半導体装置の製造方法
US8345433B2 (en) 2004-07-08 2013-01-01 Avx Corporation Heterogeneous organic laminate stack ups for high frequency applications
CN101080860A (zh) 2004-10-18 2007-11-28 艾吉尔莱特股份有限公司 微电子封装及方法
TWI241695B (en) 2004-11-19 2005-10-11 Ind Tech Res Inst Structure of an electronic package and method for fabricating the same
US7247556B2 (en) 2005-02-28 2007-07-24 Agere Systems Inc. Control of wafer warpage during backend processing
US8335084B2 (en) 2005-08-01 2012-12-18 Georgia Tech Research Corporation Embedded actives and discrete passives in a cavity within build-up layers
US20070107932A1 (en) 2005-11-09 2007-05-17 Jauniskis Linas A Moisture resistant chip package
WO2007141506A2 (en) 2006-06-09 2007-12-13 Ge Healthcare Limited Electrochemically desorbing or adsorbing cryptate [18 f] fluoride complexes
US8508036B2 (en) 2007-05-11 2013-08-13 Tessera, Inc. Ultra-thin near-hermetic package based on rainier
US8618652B2 (en) * 2010-04-16 2013-12-31 Intel Corporation Forming functionalized carrier structures with coreless packages
US8143530B1 (en) 2010-09-17 2012-03-27 Endicott Interconnect Technologies, Inc. Liquid crystal polymer layer for encapsulation and improved hermiticity of circuitized substrates
US8472207B2 (en) * 2011-01-14 2013-06-25 Harris Corporation Electronic device having liquid crystal polymer solder mask and outer sealing layers, and associated methods
KR101253514B1 (ko) 2011-10-27 2013-04-11 아페리오(주) 열팽창수축률 차이로 인한 기판 휨 문제 해결방법 및 이를 적용한 전자부품 내장형 인쇄회로기판
US20140264808A1 (en) * 2013-03-15 2014-09-18 Andreas Wolter Chip arrangements, chip packages, and a method for manufacturing a chip arrangement

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050087356A1 (en) * 2002-11-08 2005-04-28 Robert Forcier Build-up structures with multi-angle vias for chip to chip interconnects and optical bussing
US20090085190A1 (en) * 2007-09-28 2009-04-02 Juergen Simon Semiconductor Device and Method for Making Same
US20100140772A1 (en) * 2008-12-08 2010-06-10 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Vertical Interconnect Structure in Substrate for IPD and Baseband Circuit Separated by High-Resistivity Molding Compound
US20110241215A1 (en) * 2010-04-02 2011-10-06 Sankman Robert L Embedded semiconductive chips in reconstituted wafers, and systems containing same

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US9892984B2 (en) 2018-02-13
US9443789B2 (en) 2016-09-13

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