CN105516041B - Adaptive digital demodulating system under a kind of low signal-to-noise ratio - Google Patents
Adaptive digital demodulating system under a kind of low signal-to-noise ratio Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
- H04L27/2272—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals using phase locked loops
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Abstract
The present invention provides adaptive digital demodulating systems under a kind of low signal-to-noise ratio, it include: Digital Down Converter Module, rate detection module, carrier phase-locked loop road, lock-in detection module, matched filtering module, bit synchronization ring moulds block and data decision module, it is under the unfavorable conditions that low signal-to-noise ratio and high dynamic coexist, it realizes quickly, low error rate and low-loss demodulating system, and the memory space of a large amount of hardware is saved while using lower complexity, invention is under multi-rate modes, detection rates that can be quick self-adapted simultaneously carry out carrier auxiliary, carrier phase-locked loop road uses the loop bandwidth of gradual change, as loop bandwidth is gradually shortened in the increase of loop renewal time, improve the lock speed and loop stability of loop, finally cooperate Gardener time synchronization method, it completes under low signal-to-noise ratio high dynamic Demodulating system.
Description
Technical field
The present invention relates to digital transponder technical field, in particular to adaptive digital demodulation system under a kind of low signal-to-noise ratio
System.
Background technique
With the continuous development of communication technology of satellite, higher and higher want is proposed to the demodulation techniques under low signal-to-noise ratio
It asks, especially the TTC & DT Systems in deep space field, has the characteristics that extremely remote, overlength time delay, pole weak signal, noise jamming
It is very serious, in order to which effectively remote small-signal is extracted from noise, it is desirable that receiving device has very high spirit
Sensitivity and raising signal-to-noise ratio ability under the conditions of Arctic ice area to be demodulated, simultaneously because Doppler frequency shift in space link
Presence, it is desirable that receive system dynamic with higher, can fast and accurately carry out carrier phase estimation and recovery.
The difficult point of low signal-to-noise ratio demodulation is carrier auxiliary, although carrier synchronization theoretical research comparative maturity, engineer application
It is very universal, but under the unfavorable conditions that low signal-to-noise ratio and high dynamic coexist, realize quick, low error rate and low-loss demodulation
System, but also the memory space of complexity and hardware is taken into account, difficulty with higher and challenge.
There is presently no can be under multi-rate modes, can be realized more can fast and accurately be carried out in the field
Adaptive detection rates and the demodulating system for carrying out carrier auxiliary.
Summary of the invention
The purpose of the present invention is to provide adaptive digital demodulating systems under a kind of low signal-to-noise ratio, to solve existing number
Demodulating system under multi-rate modes, cannot fast and accurately carry out adaptive detection rates and carry out carrier auxiliary
Problem.
To achieve the above object, the present invention provides adaptive digital demodulating systems under a kind of low signal-to-noise ratio, comprising:
Digital Down Converter Module for receiving signal to be demodulated, and signal to be demodulated is carried out to reduce sample rate processing simultaneously
The baseband signal transmitted;
Rate detection module, the transmission rate for the baseband signal that self-adapting detecting Digital Down Converter Module obtains;
Carrier phase-locked loop road, baseband signal and rate detection module for being obtained according to Digital Down Converter Module obtain
Transmission rate the carrier auxiliary of rate is fixed, obtain accurate baseband signal;
Lock-in detection module, for being integrated to I tributary signal, the Q tributary signal in the accurate baseband signal
It handles and judges whether to lock the accurate baseband signal according to integral result, and export lock indication signal;
Matched filtering module, for the baseband signal of demodulation to be averaged, is averaged after receiving the locking signal
Signal input bit synchronization ring moulds block afterwards synchronizes processing, obtains synchronization signal;
Data decision module, for being made decisions to the synchronization signal and exporting the bit sequence after demodulation.
Preferably, further including clock module, the clock module is used to detect mould for the Digital Down Converter Module, rate
Block and bit synchronization ring moulds block provide standard clock signal.
Preferably, the Digital Down Converter Module includes CIC extracting unit, bandpass filter, multiplier, low-pass filtering
Device, received signal to be demodulated reduce sample rate by the CIC extracting unit, reduce the reception signal of sample rate described in
The carrier multiplication that multiplier and local oscillation signal generate, the signal after multiplication pass through several low-pass filters respectively and are filtered simultaneously
Export the baseband signal of several groups rate to be detected.
Preferably, the quantity of the low-pass filter is equal to the kind number of the transmission rate of baseband signal, each low pass
The bandwidth of filter is the bandwidth of corresponding baseband signal.
Preferably, when the rate kind number that originator is sent is more, the bandwidth pair of the baseband signal with neighboring transmission rate
A low-pass filter should be used, it is filtered to the baseband signals of adjacent bandwidths by the low-pass filter.
Preferably, the rate detection module includes bandpass filter, low-pass filter, the first amplitude evaluation unit,
Two amplitude evaluation units, the first power calculation unit, the second power calculation unit and comparison decision unit;
Baseband signal inputs the bandpass filter and low-pass filter, the signal after the band-pass filter respectively
Amplitude calculating is carried out by the first amplitude evaluation unit, and the first performance number, institute are acquired by first power calculation unit again
It states the filtered signal of low-pass filter and carries out amplitude calculating again by second power by the second amplitude evaluation unit
Computing unit acquires the second performance number, and first performance number inputs the decision unit with second performance number and compares
Judgement;
If first performance number is greater than second performance number, the rate of the baseband signal inputted is as current detection
The bit rate in channel, the decision unit output is 1 at this time, and otherwise the decision unit output is 0.
Preferably, the carrier phase-locked loop road includes a variable bandwidth loop filter, the variable bandwidth loop filtering
Loop noise bandwidth is gradually shortened with the cumulative of renewal time of loop in device, so that the carrier phase-locked loop road quickly obtains accurately
Baseband signal.
Preferably, the lock-in detection module in the accurate baseband signal I tributary signal, Q tributary signal into
I branch integrated value and Q branch integrated value are obtained after row Integral Processing, when I branch integrated value is greater than Q branch integrated value and I branch
When integrated value is greater than scheduled lock-in threshold, then lock indication signal is exported.
Preferably, the bit synchronization ring moulds block is specially a symbol synchronization loop, the symbol synchronization loop includes
Gardner phase discriminator and clock adjusting module, solution adjusting data input the clock adjustment after inputting the Gardner phase discriminator again
Module, clock adjusting module output signal input the Gardner phase discriminator with solution adjusting data again simultaneously and synchronize judgement simultaneously
Export synchronization signal.
Preferably, the filter in system for filtering is higher order filter, the higher order filter is by parallel
Look-up tables'implementation, and by the way that multiple groups look-up table results added is realized narrowband high-grade filting.
The present invention gives adaptive digital demodulating systems under a kind of low signal-to-noise ratio, can be adaptive under multi-rate modes
The detection rates answered simultaneously carry out carrier auxiliary;Carrier phase-locked loop road uses the loop bandwidth of gradual change, with loop renewal time
Increase loop bandwidth is gradually shortened, improve the lock speed and loop stability of loop;Cooperate Gardener timing same again
Algorithm is walked, so that demodulating system loss is reached minimum, completes the demodulating system under low signal-to-noise ratio high dynamic.
The system realizes quick, low error rate and low-loss under the unfavorable conditions that low signal-to-noise ratio and high dynamic coexist
Demodulating system, and use lower complexity while, saves the memory space of a large amount of hardware,
Detailed description of the invention
Fig. 1 is adaptive digital demodulating system composed structure schematic diagram under low signal-to-noise ratio of the present invention;
Fig. 2 is Digital Down Converter Module composition schematic diagram provided by the invention;
Fig. 3 is rate detection module composition schematic diagram provided by the invention;
Fig. 4 is carrier phase-locked loop road provided by the invention composition schematic diagram;
Fig. 5 is bit synchronization ring moulds block concrete composition schematic diagram provided by the invention;
Fig. 6 A is higher order filter equivalent schematic provided by the invention;
Fig. 6 B is higher order filter concrete composition schematic diagram provided by the invention.
Specific embodiment
In order to better illustrate the present invention, hereby with a preferred embodiment, and attached drawing is cooperated to elaborate the present invention, specifically
It is as follows:
As shown in Figure 1, adaptive digital demodulating system under low signal-to-noise ratio provided by the invention, comprising:
Digital Down Converter Module 10 for receiving signal to be demodulated, and signal to be demodulated is carried out to reduce sample rate processing
And the baseband signal transmitted;
Rate detection module 20, the transmission speed for the baseband signal that self-adapting detecting Digital Down Converter Module 10 obtains
Rate;
Carrier phase-locked loop road 30, baseband signal and rate detection module for being obtained according to Digital Down Converter Module 10
The carrier auxiliary of rate is fixed in obtained transmission rate, obtains accurate baseband signal;
Lock-in detection module 40, for being accumulated to I tributary signal, the Q tributary signal in the accurate baseband signal
Divide and handle and judge whether to lock the accurate baseband signal according to integral result, and exports lock indication signal;
Matched filtering module 50, for the baseband signal of demodulation to be averaged, is made even after receiving the locking signal
Signal input bit synchronization ring moulds block 60 after synchronizes processing, obtains synchronization signal;
Data decision module 70, for being made decisions to the synchronization signal and exporting the bit sequence after demodulation.
Clock module 80, clock module 80 are used to be that the Digital Down Converter Module 10, rate detection module 20 and position are same
It walks ring moulds block 60 and standard clock signal is provided.
The system further includes timing adjustment module 90, for being carried out according to the synchronous situation of bit sync module to clock module
Timing adjustment.
As shown in Fig. 2, Digital Down Converter Module 10 include CIC extracting unit 11, bandpass filter 12, multiplier 131 and
Multiplier 132,1~N of low-pass filter, received signal to be demodulated reduce sample rate by CIC extracting unit 11, reduce sampling
The carrier multiplication for receiving signal and being generated by multiplier 13 and local oscillation signal of rate, the signal after multiplication pass through low-pass filter 1
~N filters the baseband signal for reverting to transmission.
Wherein, the quantity of low-pass filter can be set to, Mei Gesuo identical as the quantity of the transmission rate of baseband signal
The bandwidth for stating low-pass filter is the bandwidth of corresponding baseband signal.If the rate that may be sent of starting is more, in order to save
Hardware resource is saved, the adjacent signal to be detected of transmission rate uses a low-pass filter after down coversion, by the low-pass filter
The baseband signal of adjacent bandwidths is filtered.
Specifically, in the present embodiment, setting detectable character rate has M*N kind, then the number of low-pass filter is
M*N, when hardware resource is limited, low-pass filter needed for the adjacent detection rates of every M kind can be realized with one, then low pass filtered
The number of wave device is N.In order to guarantee the performance of filter, the quantity for sharing detection should not be more.Guarantee each channel by extracting
(K value removes frequency-change sampling rate and transmission to K times of the rate that the data sampling rate of output can detect for the channel in the present invention
The ratio of maximum possible bit rate, therefore the channel for detecting more low bit rate rate can realize that output data is detection code speed by extracting
K times of rate of symbol sampler rate), i.e., subsequent rate detection and demodulation signal processing are completed under K times of symbol sampler rate.By
Fig. 1 can be seen that in the case where M=2, the signal to be detected of every 2 kinds of neighboring transmission rates shares a low-pass filter, altogether
The rate that can detecte has 2*N kind, port number N, and each channel has 2 road I, Q data to be detected.
As shown in figure 3, rate detection module 20 includes bandpass filter 21, low-pass filter 22, the first amplitude pro form bill
First 23, second amplitude evaluation unit 24, the first power calculation unit 25, the second power calculation unit 26 and comparison decision unit
27;
The I circuit-switched data signal and Q circuit-switched data signal of baseband signal input bandpass filter 21 and low-pass filter 22 respectively,
The filtered signal of bandpass filter 21 carries out amplitude by the first amplitude evaluation unit 23 and calculates again by first power meter
It calculates unit 25 and acquires the first performance number, the filtered signal of low-pass filter 22 is carried out by the second amplitude evaluation unit 24
Amplitude, which calculates, acquires the second performance number by the second power calculation unit 26 again, and the first performance number is sentenced with second performance number input
Certainly unit 27 compares judgement;
If the first performance number is greater than the second performance number, then it is assumed that the rate of the baseband signal of input is current detection channel
Bit rate, the at this time output of decision unit 27 are 1, and otherwise the output of decision unit 27 is 0.
As shown in figure 4, carrier phase-locked loop road 30 include a variable bandwidth loop filter, variable bandwidth loop filter with
Loop noise bandwidth is gradually shortened in the cumulative of the renewal time of loop, so that the carrier phase-locked loop road quickly obtains accurate base
Band signal.
Carrier phase-locked loop road overall structure is referring to fig. 4, wherein sets carrier-suppressed double sideband signal are as follows: s (t)=m (t) cos
ωcT, then
After low-pass filtered device,
Multiplier output:If phase difference θ very little,
The signal contains the phase difference of carrier wave and voltage controlled oscillator output signal, therefore can be exchanged into through loop filter
The control voltage of voltage controlled oscillator, to generate oscillator signal of the carrier wave with frequency.
According to the multi gear loop noise bandwidth Wn that demodulation signal-to-noise ratio settings are descending, from the above equation, we can see that Wn has been determined
It obtains respective loops filter coefficient Ga, Gb and chooses different loop filters then with the increase of phase-locked loop renewal time
The phase-locked loop that loop noise bandwidth is gradually shortened can be realized in coefficient.
Lock-in detection module 40 carries out Integral Processing to I tributary signal, the Q tributary signal in above-mentioned accurate baseband signal
After obtain I branch integrated value and Q branch integrated value, be greater than when I branch integrated value is greater than Q branch integrated value and I branch integrated value
When scheduled lock-in threshold, then lock indication signal is exported.
Specifically, in the present invention, when loop-locking, down coversion exports the I branch of complex baseband signal only comprising direct current point
Amount, and Q branch includes remote signal or pseudo-code signal, the principle of loop-locking detection is the mistake of phase discriminator after capture
The mean value of difference goes to zero, and the road-load wave energy of I is maximum.Therefore, it can be exported with the integral of I, Q branch and carry out loop detection locking
Judgement.Constant is related with signal-to-noise ratio when wherein integrating, by estimating plus correcting when available random process analysis procedure analysis or reality are debugged
It arrives.
In lock detecting method in the present invention, if lock-in threshold is θth(θth<15°)。
If the update loop cycle (estimate is 2 times of the longest loop-locking time) that the lock-in detection period is N times, the first half
Period is the loop-locking time, the latter half period start to carry out I branch and Q tributary signal integral it is cumulative obtain acc_I and
Acc_Q makes decisions in period foot couple accumulated value, if acc_I/tan θth> acc_Q, and acc_I is greater than lock-in threshold, locking
Thresholding is noise power-value when no signal is sent into, then is judged to locking.
As shown in figure 5, bit synchronization ring moulds block 60 is specially a symbol synchronization loop, which includes
Gardner phase discriminator 61 and clock adjusting module 62, solution adjusting data input Gardner phase discriminator 61 by demodulation data module 63
Input clock adjusts module 62 again afterwards, and 62 output signal of clock adjusting module inputs Gardner phase demodulation with solution adjusting data again simultaneously
Device 61 synchronizes judgement and exports synchronization signal.
As shown in fig. 6, the filter in system for filtering is higher order filter, which is used for by simultaneously
What the method that row look-up table is added was realized, and by the way that multiple groups look-up table results added is carried out narrowband high-grade filting.In order to realize
The low latency of filter, and economizing on resources as far as possible, the present invention first with according to filter bandwidth and degree of suppression setting it is reasonable
Then order uses parallel search table additive process (structure such as Fig. 6 A), can be using the data of input as address in ROM
Signal searches the multiply-add value of input data and filter factor, directly exports filtered calculated result by ROM, and function is equivalent
In 6B, which saves the resource occupation of filter as far as possible.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those skilled in the art in the technical scope disclosed by the present invention, to deformation or replacement that the present invention is done, should be covered
Within protection scope of the present invention.Therefore, protection scope of the present invention should be subject to the scope of protection of the claims.
Claims (10)
1. adaptive digital demodulating system under a kind of low signal-to-noise ratio characterized by comprising
Signal to be demodulated for receiving signal to be demodulated, and reduce sample rate and handles and obtain by Digital Down Converter Module
The baseband signal of transmission;
Rate detection module, the transmission rate for the baseband signal that self-adapting detecting Digital Down Converter Module obtains;
Carrier phase-locked loop road, the biography that baseband signal and rate detection module for being obtained according to Digital Down Converter Module obtain
The carrier auxiliary of rate is fixed in defeated rate, obtains accurate baseband signal;
Lock-in detection module, for carrying out Integral Processing to I tributary signal, the Q tributary signal in the accurate baseband signal
And judge whether to lock the accurate baseband signal according to integral result, and export lock indication signal;
Bit synchronization ring moulds block synchronizes processing for the signal after being averaged to matched filtering module, obtains synchronization signal;
Matched filtering module, for the baseband signal of demodulation to be averaged, is averaged after receiving the lock indication signal
Signal input bit synchronization ring moulds block afterwards synchronizes processing, obtains synchronization signal;
Data decision module, for being made decisions to the synchronization signal and exporting the bit sequence after demodulation.
2. adaptive digital demodulating system under low signal-to-noise ratio according to claim 1, which is characterized in that further include clock mould
Block, the clock module is for when providing standard for the Digital Down Converter Module, rate detection module and bit synchronization ring moulds block
Clock signal.
3. adaptive digital demodulating system under low signal-to-noise ratio according to claim 1, which is characterized in that the number is lower to be become
Frequency module includes CIC extracting unit, bandpass filter, multiplier, low-pass filter, and received signal to be demodulated passes through described
CIC extracting unit reduces sample rate, reduces the carrier wave for receiving signal and generating by the multiplier and local oscillation signal of sample rate
It is multiplied, the signal after multiplication passes through the base band that several low-pass filters are filtered and export several groups rate to be detected respectively
Signal.
4. adaptive digital demodulating system under low signal-to-noise ratio according to claim 3, which is characterized in that the low-pass filtering
The quantity of device is equal to the kind number of the transmission rate of baseband signal, and the bandwidth of each low-pass filter is corresponding base band
The bandwidth of signal.
5. adaptive digital demodulating system under low signal-to-noise ratio according to claim 3, which is characterized in that sent when originator
When rate kind number is more, the bandwidth of the baseband signal with neighboring transmission rate is corresponding using a low-pass filter, low by this
Bandpass filter is filtered the baseband signal of adjacent bandwidths.
6. adaptive digital demodulating system under low signal-to-noise ratio according to claim 1, which is characterized in that the rate detection
Module includes bandpass filter, low-pass filter, the first amplitude evaluation unit, the second amplitude evaluation unit, the first power calculation
Unit, the second power calculation unit and comparison decision unit;
Baseband signal inputs the bandpass filter and low-pass filter respectively, and the signal after the band-pass filter passes through
The first amplitude evaluation unit carries out amplitude calculating and acquires the first performance number by first power calculation unit again, described low
The filtered signal of bandpass filter carries out amplitude by the second amplitude evaluation unit and calculates again by second power calculation
Unit acquires the second performance number, and first performance number inputs the comparison decision unit with second performance number and compares
Judgement;
If first performance number is greater than second performance number, the rate of the baseband signal inputted is as current detection channel
Bit rate, comparison decision unit output at this time is 1, and otherwise the comparison decision unit output is 0.
7. adaptive digital demodulating system under low signal-to-noise ratio according to claim 1, which is characterized in that the carrier wave locking phase
Loop include a variable bandwidth loop filter, the variable bandwidth loop filter with loop renewal time it is cumulative gradually
Shorten loop noise bandwidth, so that the carrier phase-locked loop road quickly obtains accurate baseband signal.
8. adaptive digital demodulating system under low signal-to-noise ratio according to claim 1, which is characterized in that the lock-in detection
Module obtains I branch integrated value after carrying out Integral Processing to I tributary signal, the Q tributary signal in the accurate baseband signal
And Q branch integrated value, when I branch integrated value is greater than Q branch integrated value and I branch integrated value is greater than scheduled lock-in threshold,
Then export lock indication signal.
9. adaptive digital demodulating system under low signal-to-noise ratio according to claim 1, which is characterized in that the bit synchronization ring
Module is specially a symbol synchronization loop, and the symbol synchronization loop includes Gardner phase discriminator and clock adjusting module, demodulation
Data input after the Gardner phase discriminator inputs the clock adjusting module again, clock adjusting module output signal again with solution
Adjusting data inputs the Gardner phase discriminator simultaneously and synchronizes judgement and export synchronization signal.
10. adaptive digital demodulating system under low signal-to-noise ratio according to claim 1, which is characterized in that be used in system
The filter of filtering is higher order filter, and the higher order filter is realized by parallel search table, and by by multiple groups
Look-up table results added realizes narrowband high-grade filting.
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CN107040486B (en) * | 2017-03-28 | 2019-11-26 | 西安电子科技大学 | A kind of QPSK demodulating system and method that any bit rate is adaptive |
CN106936742B (en) * | 2017-05-02 | 2020-01-31 | 西安电子科技大学 | Multi-gear rate self-adaptive demodulation system and method based on neural network |
CN108989260B (en) * | 2018-08-01 | 2020-08-04 | 清华大学 | Improved all-digital timing synchronization method and device based on Gardner |
CN109981510A (en) * | 2019-02-15 | 2019-07-05 | 北京空间飞行器总体设计部 | A kind of very low bit rate remote control reliable receiving method being applicable in deep space communication |
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