CN105514125B - 一种阵列基板、其制备方法及显示面板 - Google Patents
一种阵列基板、其制备方法及显示面板 Download PDFInfo
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Abstract
本发明公开了一种阵列基板、其制备方法及显示面板,包括衬底基板,依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层,绝缘层具有过孔区域、位于过孔区域外侧的半保留区域、以及包围半保留区域和过孔区域所在的区域的完全保留区域。由于过孔区域周围是半保留区域,降低了过孔周围绝缘层的厚度,可以保证在过孔坡度固定的情况下减小过孔的尺寸,从而提高开口率,并且可以降低过孔边缘残留绝缘层材料的影响。另外,由于绝缘层的高度段差分为两段,从而可以降低绝缘层整体厚度造成的段差影响。
Description
技术领域
本发明涉及显示技术领域,尤指一种阵列基板、其制备方法及显示面板。
背景技术
在薄膜晶体管液晶显示器(Thin Film Transistor Liquid Crystal Display,TFT-LCD)生产工艺中,由于有机绝缘膜层容易形成较厚的膜层而具有可以减小阵列基板中的信号干扰、减小寄生电容、降低基板负载从而降低功耗等优点,因此有机绝缘膜层被广泛应用。通常,有机绝缘膜层设置于两个导电膜层之间,例如设置于源漏电极层和像素电极层之间。为了使像素电极与薄膜晶体管的漏极电性连接,需要在有机绝缘膜层上形成过孔(Via Hole)。
如图1a所示为现有技术中有机绝缘膜层的应用结构示意图,衬底基板10上设置有由有源层11、栅极(图中未示出)、源极(图中未示出)和漏极12组成的薄膜晶体管,数据线13、栅线14和像素电极15,像素电极15与漏极12之间设置有有机绝缘膜层16,像素电极15通过贯穿有机绝缘膜层16的过孔V与漏极12电性连接,数据线13、源极以及漏极12同层设置;如图1b所示(为图1a沿A-A’方向的剖面结构示意图),由于有机绝缘膜层16较厚,数据线13和像素电极15之间的寄生电容较小,因此画面品质好,如图1c所示(为图1a沿B-B’方向的剖面结构示意图),由于有机绝缘膜层16较厚,导致过孔V较深(可达2μm),从而容易发生使过孔V侧面搭接的像素电极15发生断裂、以及由于有机绝缘膜层16的段差大导致的后续取向膜摩擦取向不均匀等不良问题。
发明内容
有鉴于此,本发明实施例提供了一种阵列基板、其制备方法及显示面板,用于改善由于现有阵列基板中绝缘层的过孔深所产生的不良问题。
因此,本发明实施例提供的一种阵列基板,包括衬底基板,依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层,所述绝缘层具有过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域;其中,
所述过孔区域为贯穿所述绝缘层的过孔,且所述第二导电层通过所述过孔与所述第一导电层电性连接;
所述绝缘层的所述半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的所述完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离。
较佳地,在本发明实施例提供的上述阵列基板中,所述半保留区域完全包围所述过孔区域。
较佳地,在本发明实施例提供的上述阵列基板中,所述绝缘层的材料为有机材料。
较佳地,在本发明实施例提供的上述阵列基板中,所述绝缘层的材料为感光性有机材料。
较佳地,在本发明实施例提供的上述阵列基板中,所述半保留区域的宽度为1μm~6μm。
较佳地,在本发明实施例提供的上述阵列基板中,所述绝缘层的所述半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于或等于所述绝缘层的所述完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离的一半。
较佳地,在本发明实施例提供的上述阵列基板中,所述绝缘层在所述完全保留区域的厚度为2μm~3μm。
较佳地,在本发明实施例提供的上述阵列基板中,所述第一导电层为所述阵列基板上的薄膜晶体管的漏极,所述第二导电层为像素电极。
相应地,本发明实施例还提供了一种显示面板,包括本发明实施例提供的上述任一种阵列基板。
相应地,本发明实施例还提供了一种上述任一种阵列基板的制备方法,包括:
在所述衬底基板上形成所述第一导电层的图形;
在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形;其中,所述绝缘层具有过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域;所述过孔区域为贯穿所述绝缘层的过孔,所述绝缘层的所述半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的所述完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离;
在形成有所述绝缘层的衬底基板上形成所述第二导电层的图形;其中所述第二导电层通过所述过孔与所述第一导电层电性连接。
较佳地,在本发明实施例提供的上述制备方法中,在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形,具体为:
通过一次构图工艺在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形。
较佳地,在本发明实施例提供的上述制备方法中,当所述绝缘层的材料为感光性有机材料时,通过一次构图工艺在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形,具体为:
在形成有所述第一导电层的衬底基板上形成绝缘层膜层,且所述绝缘层膜层的材料为感光性有机材料;
利用一为半色调掩模板或灰色调掩模板的第一掩膜板对所述绝缘层膜层进行曝光显影,在与所述第一掩模板的第一区域对应的所述绝缘层膜层的区域处形成所述绝缘层的所述完全保留区域的图形,在与所述第一掩模板的第二区域对应的所述绝缘层膜层的区域处形成所述绝缘层的所述半保留区域的图形;在与所述第一掩模板的第三区域对应的所述绝缘层膜层的区域处形成所述绝缘层的所述过孔区域的图形;其中,
当所述感光性有机材料为正性感光材料时,所述第一掩模板的第一区域为遮光区域,第二区域为部分透光区域,第三区域为完全透光区域;
当所述感光性有机材料为负性感光材料时,所述第一掩模板的第一区域为完全透光区域,第二区域为部分透光区域,第三区域为遮光区域。
本发明实施例提供的上述阵列基板、其制备方法及显示面板,包括衬底基板,依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层,绝缘层具有过孔区域、位于过孔区域外侧的半保留区域、以及包围半保留区域和过孔区域所在的区域的完全保留区域。由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度,因此可以不仅可以降低第二导电层在过孔边缘发生断裂的概率,并且可以避免过孔边缘残留绝缘层材料。另外,由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离,因此使得绝缘层的高度段差分为两段,从而可以降低绝缘层整体厚度造成的段差影响。并且,由于半保留区域仅是设置在绝缘层的过孔区域外侧,其它区域仍为完全保留区域,因此不会增加其它区域第一导电层与第二导电层之间寄生电容。
附图说明
图1a为现有的有机绝缘膜层的应用结构示意图;
图1b为图1a沿A-A’方向的剖面结构示意图;
图1c为图1a沿B-B’方向的剖面结构示意图;
图2a和图2b分别为本发明实施例提供的阵列基板的俯视结构示意图;
图3a为图2a所示阵列基板沿A-A’方向的剖面结构示意图;
图3b为图2b所示阵列基板沿A-A’方向的剖面结构示意图;
图4a为本发明实施例提供的阵列基板的具体结构示意图;
图4b为图4a所示阵列基板沿A-A’方向的剖面结构示意图;
图4c为图4a所示阵列基板沿B-B’方向的剖面结构示意图;
图5为本发明实施例提供的阵列基板的剖面结构示意图;
图6为本发明实施例提供的一种阵列基板的制备方法的流程图。
具体实施方式
为了使本发明的目的,技术方案和优点更加清楚,下面结合附图,对本发明实施例提供的阵列基板、其制备方法及显示面板的具体实施方式进行详细地说明。
附图中各层薄膜厚度和形状不反映阵列基板的真实比例,目的只是示意说明本发明内容。
本发明实施例提供的一种阵列基板如图2a和图2b所示,包括衬底基板100,依次位于衬底基板100上的第一导电层101、绝缘层102和第二导电层103,绝缘层102具有过孔区域I、位于过孔区域I外侧的半保留区域M、以及包围半保留区域M和过孔区域I所在的区域的完全保留区域O;其中
过孔区域I为贯穿绝缘层102的过孔,且第二导电层103通过该过孔与第一导电层101电性连接;
如图3a和图3b所示,绝缘层102的半保留区域M的上表面与第一导电层101的上表面之间的垂直距离h1小于绝缘层102的完全保留区域O的上表面与第一导电层101的上表面之间的垂直距离h2,即绝缘层102在半保留区域M的厚度小于完全保留区域O的厚度。
本发明实施例提供的上述阵列基板,包括衬底基板,依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层,绝缘层具有过孔区域、位于过孔区域外侧的半保留区域、以及包围半保留区域和过孔区域所在的区域的完全保留区域。由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度,因此可以不仅可以降低第二导电层在过孔边缘发生断裂的概率,并且可以避免过孔边缘残留绝缘层材料。另外,由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离,因此使得绝缘层的高度段差分为两段,从而可以降低绝缘层整体厚度造成的段差影响。并且,由于半保留区域仅是设置在绝缘层的过孔区域外侧,其它区域仍为完全保留区域,因此不会增加其它区域第一导电层与第二导电层之间寄生电容。
在具体实施时,在本分发明实施例提供的上述阵列基板中,为了最大限度的降低第二导电层在过孔边缘发生断裂的概率,如图2b所示,半保留区域M完全包围过孔区域I。但是由于设置半保留区域可能会降低阵列基板的开口率,因此从开口率的角度考虑,如图2a所示,半保留区域M半包围过孔区域I。在具体实施时,可以根据实际情况中所需的开口率和第二导电层在过孔边缘发生断裂的概率的比重确定半保留区域的大小。
在具体实施时,在发明实施例提供的上述阵列基板中,半保留区域的宽度控制在1μm~6μm之间。这是因为,当半保留区域的宽度太宽时,可能会超出现有阵列基板中黑矩阵遮挡的范围,从而降低阵列基板的开口率,当半保留区域的宽度太窄时,目前的制作工艺可能不能实现,并且产生的减小断差带来的效果也会大打折扣。
较佳地,在本发明实施例提供的上述阵列基板中,绝缘层的材料为有机材料,这是因为有机材料形成的绝缘层在工艺上容易实现较厚的厚度,当然在具体实施时,绝缘层的材料也可以为无机材料,在此不作限定。
进一步地,在本发明实施例提供的上述阵列基板中,绝缘层的材料为感光性有机材料。这样,在制备绝缘层的图形时,不需要单独再涂覆光刻胶层,利用绝缘层自身的感光性复用光刻胶层,可以降低制备成本。
在具体实施是,在半保留区域面积固定的情况下,半保留区域的厚度越小,第二导电层在过孔边缘发生断裂的概率也就越小,因此,较佳地,在本发明实施例提供的上述阵列基板中,本发明实施例提供的上述阵列基板中,绝缘层的半保留区域的上表面与第一导电层的上表面之间的垂直距离小于或等于绝缘层的完全保留区域的上表面与第一导电层的上表面之间的垂直距离的一半。
在本发明实施例提供的上述阵列基板中,绝缘层在完全保留区域的厚度一般为2μm~3μm,在此不作限定。
本发明实施例提供的上述阵列基板适用于任何两导电层之间需要通过位于该两导电层之间的绝缘层的过孔电连接的结构,但是针对绝缘层厚度较厚的结构效果尤为显著。
在具体实施时,在本发明实施例提供的上述阵列基板中,第一导电层为阵列基板上的薄膜晶体管的漏极,第二导电层为像素电极,在此不作限定。
一般地,在具体实施时,在本发明实施例提供的上述阵列基板中,还包括数据线、栅线、源极、栅极、有源层、栅极绝缘层、钝化层、公共电极等膜层和结构,由于这些膜层和结构均与现有技术中相同,因此在此不作详述。
在具体实施时,在本发明实施例提供的上述阵列基板中,公共电极可以位像素像素电极上方,也可以位于像素电极的下方,在此不作限定。
下面通过一个具体实施例说明本发明实施例提供的上述阵列基板,如图4a至图4c所示,衬底基板100上依次设置有同层设置的栅线110和栅极111,栅极绝缘层112,有源层113,同层设置的源极(图中未示出)、漏极114和数据线115,绝缘层102,以及像素电极116,其中,绝缘层102具有过孔区域I、包围过孔区域I的环状的半保留区域M、以及包围半保留区域M的完全保留区域O,过孔区域I为贯穿绝缘层102的过孔,绝缘层102的半保留区域M的上表面与第一导电层101的上表面之间的垂直距离小于绝缘层102的完全保留区域O的上表面与第一导电层101的上表面之间的垂直距离,即绝缘层102在半保留区域M的厚度小于完全保留区域O的厚度,且像素电116通过该过孔与漏极114电性连接。如图4b所示(为图4a沿A-A’方向的剖面结构示意图),由于绝缘层102较厚,位于绝缘层102两侧的导电层(例如数据线115与像素电极116)之间的寄生电容较小,因此画面品质好,如图4c所示(为图4a沿B-B’方向的剖面结构示意图),虽然绝缘层102较厚,由于过孔区域I周围是半保留区域M,降低了过孔周围绝缘层102的厚度,因此,不仅可以降低像素电极116在过孔边缘发生断裂的概率,并且可以避免过孔边缘残留绝缘层102材料。另外,由于在过孔区域I与完全保留区域O之间设置有半保留区域M,且半保留区域M的厚度小于完全保留区域O的厚度,因此使得绝缘层102的高度段差分为两段,从而可以降低绝缘层102整体厚度造成的段差影响。
在上述阵列基板中,由于在绝缘层的过孔区域外侧设置了半保留区域,虽然半保留区域会降低像素电极发生断裂的概率,但是所半保留区域位于液晶像素区域,则会在显示时影响液晶分子的翻转,因此出于避免影响液晶分子的翻转,将半保留区域设置为半包围过孔区域,且半保留区域位于过孔区域的远离像素区域的一侧。
进一步地,在上述阵列基板中,在工艺上黑矩阵一般与过孔区域边缘之间有3μm的工艺范围,即黑矩阵会超出过孔区域边缘3μm,因此为了保证半保留区域不超出黑矩阵的覆盖范围,半保留区域的宽度不超过3μm。
上述阵列基板是以像素电极直接通过绝缘层与漏极电连接为例进行说明的,但是不限于此,发明实施例提供的上述阵列基板也适用于将公共电极设置于像素电极与绝缘层之间的阵列基板。
具体地,如图5所示,在绝缘层102与像素电极116之间设置有公共电极117,公共电极117与像素电极116之间设置有钝化层118,公共电极117和钝化层118在与绝缘层102的过孔区域I对应的区域处均设置有过孔,像素电极116与漏极114通过贯穿钝化层118、公共电极117和绝缘层102的过孔实现电连接。
进一步地,在上述阵列基板中,为了避免公共电极117与像素电极116发生短路,公共电极117与绝缘层102的过孔区域I的外侧一般需要有3μm的距离,这时在工艺上黑矩阵一般与公共电极117边缘之间有3μm的工艺范围,即黑矩阵要至少覆盖公共电极117的宽度为3μm,因此这种情况下,为了保证半保留区域不超出黑矩阵的覆盖范围,半保留区域的宽度不超过6μm。
基于同一发明构思,本发明实施例还提供了一种显示面板,包括本发明实施例提供的上述任一种阵列基板。由于该显示面板解决问题的原理与前述一种阵列基板相似,因此该显示面板的实施可以参见前述阵列基板的实施,重复之处不再赘述。
基于同一发明构思,本发明实施例还提供了上述任一种阵列基板的制备方法,如图6所示,可以包括以下步骤:
S601、在衬底基板上形成第一导电层的图形;
S602、在形成有第一导电层的衬底基板上形成绝缘层的图形;其中,绝缘层具有过孔区域、位于过孔区域外侧的半保留区域、以及包围半保留区域和过孔区域所在的区域的完全保留区域,过孔区域为贯穿绝缘层的过孔,且绝缘层的半保留区域的上表面与第一导电层的上表面之间的垂直距离小于绝缘层的完全保留区域的上表面与第一导电层的上表面之间的垂直距离;
S603、在形成有绝缘层的衬底基板上形成第二导电层的图形;其中第二导电层通过该过孔与第一导电层电性连接。
本发明实施例提供的上述阵列基板的制备方法,绝缘层具有过孔区域、位于过孔区域外侧的半保留区域、以及包围半保留区域和过孔区域所在的区域的完全保留区域。由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度,因此可以不仅可以降低第二导电层在过孔边缘发生断裂的概率,并且可以避免过孔边缘残留绝缘层材料。另外,由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离,因此使得绝缘层的高度段差分为两段,从而可以降低绝缘层整体厚度造成的段差影响。并且,由于半保留区域仅是设置在绝缘层的过孔区域外侧,其它区域仍为完全保留区域,因此不会增加其它区域第一导电层与第二导电层之间寄生电容。
在具体实施时,在本发明实施例提供的上述制备方法中,在形成有第一导电层的衬底基板上形成绝缘层的图形,具体为:
通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层的图形。
需要说明的是,在本发明实施例提供的上述阵列基板的制备方法中,构图工艺可只包括光刻工艺,或,可以包括光刻工艺以及刻蚀步骤,同时还可以包括打印、喷墨等其他用于形成预定图形的工艺;光刻工艺是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。在具体实施时,可根据本发明中所形成的结构选择相应的构图工艺。
在具体实施时,在本发明实施例提供的上述制备方法中,通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层的图形,具体为:
在形成有第一导电层的衬底基板上形成绝缘层膜层;
在绝缘层上形成光刻胶层;
采用利用一为半色调掩模板或灰色调掩模板的第一掩膜板对光刻胶层进行曝光显影后,在光刻胶层上定义出绝缘层的图形,以该具有绝缘层的图形的光刻胶层为掩膜,对绝缘层进行刻蚀,在与第一掩模板的第一区域对应的绝缘层膜层的区域处形成绝缘层的完全保留区域的图形,在与第一掩模板的第二区域对应的绝缘层膜层的区域处形成绝缘层的半保留区域的图形;在与第一掩模板的第三区域对应的绝缘层膜层的区域处形成绝缘层的过孔区域的图形;其中,当光刻胶层的材料为正性光刻胶时,第一掩模板的第一区域为遮光区域,第二区域为部分透光区域,第三区域为完全透光区域;当光刻胶层的材料为负性光刻胶时,第一掩模板的第一区域为完全透光区域,第二区域为部分透光区域,第三区域为遮光区域。
这样通过一次构图工艺就形成绝缘层的图形,可以减少掩膜板(Mask)次数,从而降低成本。当然,在具体实施时,也可以通过两次构图工艺形成绝缘层的图形,在此不作限定。
具体低,当通过两次供图工艺形成绝缘层的图形时,在本发明实施例提供的上述制备方法中,在形成有第一导电层的衬底基板上形成绝缘层的图形,具体为:
在形成有第一导电层的衬底基板上形成绝缘层膜层;
利用一第二掩膜板对绝缘层膜层进行一次构图,形成绝缘层的过孔区域的图形和绝缘层的第一保留区域的图形;
利用一第三掩膜板对绝缘层膜层进行二次构图,在绝缘层的第一保留区域的图形中形成绝缘层的半保留区域的图形和完全保留区域的图形。
在具体实施时,不管是采用一次掩膜板,还是采用两次掩膜板,一般均需要利用光刻胶进行构图。但是,在本发明实施例提供的上述阵列基板中,当绝缘层的材料为感光性有机材料时,由于绝缘层自身的感光性能,因此可以利用绝缘层复用为光刻层的作用,从而不仅可以在对绝缘层进行构图时避免光刻胶的使用,而且可以简化工艺。
因此,较佳地,在本发明实施例提供的上述制备方法中,当绝缘层的材料为感光性有机材料时,通过一次构图工艺在形成有第一导电层的衬底基板上形成绝缘层的图形,具体为:
在形成有第一导电层的衬底基板上形成绝缘层膜层,且绝缘层膜层的材料为感光性有机材料;
利用一为半色调掩模板或灰色调掩模板的第一掩膜板对绝缘层膜层进行曝光显影,在与第一掩模板的第一区域对应的绝缘层膜层的区域处形成绝缘层的完全保留区域的图形,在与第一掩模板的第二区域对应的绝缘层膜层的区域处形成绝缘层的半保留区域的图形;在与第一掩模板的第三区域对应的绝缘层膜层的区域处形成绝缘层的过孔区域的图形;其中,
当感光性有机材料为正性感光材料时,第一掩模板的第一区域为遮光区域,第二区域为部分透光区域,第三区域为完全透光区域;
当感光性有机材料为负性感光材料时,第一掩模板的第一区域为完全透光区域,第二区域为部分透光区域,第三区域为遮光区域。
一般地,在具体实施时,在本发明实施例提供的上述制备方法中,还包括形成数据线、栅线、源极、栅极、有源层、栅极绝缘层、钝化层、公共电极等图形的步骤,由于这些步骤在工艺上与现有技术中相同,因此在此不作详述。
下面通过以图4a所示阵列基板为例具体说明本发明实施例提供的上述阵列基板的制备过程,具体包括以下步骤:
(1)在衬底基板上通过一次构图工艺形成栅极和栅线的图形;
(2)沉积栅极绝缘层,在具体实施时,栅极绝缘层的材料通常为SiNx;
(3)通过一次构图工艺形成有源层的图形;
(4)通过一次构图工艺形成数据线、源极和漏极的图形;
(5)通过一次构图工艺形成绝缘层的图形,该绝缘层的材料为感光性有机材料;
其中,绝缘层具有过孔区域、包围该过孔区域的环状的半保留区域、以及包围该半保留区域的完全保留区域,过孔区域为贯穿绝缘层的过孔,且绝缘层的半保留区域的上表面与第一导电层的上表面之间的垂直距离小于绝缘层的完全保留区域的上表面与第一导电层的上表面之间的垂直距离;
在具体实施时,通过一次构图工艺形成绝缘层的图形具体为:先形成绝缘层膜层,再利用一为半色调掩模板或灰色调掩模板的第一掩膜板对绝缘层膜层进行曝光显影,在与第一掩模板的第一区域对应的绝缘层膜层的区域处形成绝缘层的完全保留区域的图形,在与第一掩模板的第二区域对应的绝缘层膜层的区域处形成绝缘层的半保留区域的图形;在与第一掩模板的第三区域对应的绝缘层膜层的区域处形成绝缘层的过孔区域的图形;其中,当感光性有机材料为正性感光材料时,第一掩模板的第一区域为遮光区域,第二区域为部分透光区域,第三区域为完全透光区域;当感光性有机材料为负性感光材料时,第一掩模板的第一区域为完全透光区域,第二区域为部分透光区域,第三区域为遮光区域。
进一步地,完全保留区域的绝缘层的厚度控制在2μm左右,半保留区域的绝缘层的厚度控制在小于或等于1μm。
具体地,半保留区域的绝缘层的宽度和厚度都可以通过第一掩膜板的第二区域的透光率和总曝光量进行控制。
(6)通过一次构图工艺形成有像素电极的图形,像素电极通过绝缘层中的过孔与漏极电性连接。
当然在具体实施时,在步骤(6)之后,还可以包括在像素电极上方形成钝化层的图形,在钝化层上形成公共电极的图形等步骤,在此不作限定。
本发明实施例提供的上述阵列基板、其制备方法及显示面板,包括衬底基板,依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层,绝缘层具有过孔区域、位于过孔区域外侧的半保留区域、以及包围半保留区域和过孔区域所在的区域的完全保留区域。由于过孔区域外侧的半保留区域可以降低过孔周围绝缘层的厚度,因此可以不仅可以降低第二导电层在过孔边缘发生断裂的概率,并且可以避免过孔边缘残留绝缘层材料。另外,由于半保留区域的上表面与第一导电层的上表面之间的垂直距离小于完全保留区域的上表面与第一导电层的上表面之间的垂直距离,因此使得绝缘层的高度段差分为两段,从而可以降低绝缘层整体厚度造成的段差影响。并且,由于半保留区域仅是设置在绝缘层的过孔区域外侧,其它区域仍为完全保留区域,因此不会增加其它区域第一导电层与第二导电层之间寄生电容。
显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。
Claims (11)
1.一种阵列基板,包括衬底基板,依次位于所述衬底基板上的第一导电层、绝缘层和第二导电层,其特征在于,所述绝缘层具有过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域;其中,
所述过孔区域为贯穿所述绝缘层的过孔,且所述第二导电层通过所述过孔与所述第一导电层电性连接;
所述绝缘层的所述半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的所述完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离;
所述半保留区域为在平行于所述衬底基板的方向上半包围所述过孔区域,且所述半保留区域位于所述过孔区域的远离像素区域的一侧。
2.如权利要求1所述的阵列基板,其特征在于,所述绝缘层的材料为有机材料。
3.如权利要求2所述的阵列基板,其特征在于,所述绝缘层的材料为感光性有机材料。
4.如权利要求1所述的阵列基板,其特征在于,所述半保留区域的宽度为1μm~6μm。
5.如权利要求1所述的阵列基板,其特征在于,所述绝缘层的所述半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于或等于所述绝缘层的所述完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离的一半。
6.如权利要求1所述的阵列基板,其特征在于,所述绝缘层在所述完全保留区域的厚度为2μm~3μm。
7.如权利要求1-6任一项所述的阵列基板,其特征在于,所述第一导电层为所述阵列基板上的薄膜晶体管的漏极,所述第二导电层为像素电极。
8.一种显示面板,其特征在于,包括如权利要求1-7任一项所述的阵列基板。
9.一种如权利要求1-7任一项所述的阵列基板的制备方法,其特征在于,包括:
在所述衬底基板上形成所述第一导电层的图形;
在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形;其中,所述绝缘层具有过孔区域、位于所述过孔区域外侧的半保留区域、以及包围所述半保留区域和所述过孔区域所在的区域的完全保留区域;所述过孔区域为贯穿所述绝缘层的过孔,所述绝缘层的所述半保留区域的上表面与所述第一导电层的上表面之间的垂直距离小于所述绝缘层的所述完全保留区域的上表面与所述第一导电层的上表面之间的垂直距离;所述半保留区域为半包围所述过孔区域,且所述半保留区域位于所述过孔区域的远离像素区域的一侧;
在形成有所述绝缘层的衬底基板上形成所述第二导电层的图形;其中所述第二导电层通过所述过孔与所述第一导电层电性连接。
10.如权利要求9所述的制备方法,其特征在于,在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形,具体为:
通过一次构图工艺在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形。
11.如权利要求10所述的制备方法,其特征在于,当所述绝缘层的材料为感光性有机材料时,通过一次构图工艺在形成有所述第一导电层的衬底基板上形成所述绝缘层的图形,具体为:
在形成有所述第一导电层的衬底基板上形成绝缘层膜层,且所述绝缘层膜层的材料为感光性有机材料;
利用一为半色调掩模板或灰色调掩模板的第一掩模板对所述绝缘层膜层进行曝光显影,在与所述第一掩模板的第一区域对应的所述绝缘层膜层的区域处形成所述绝缘层的所述完全保留区域的图形,在与所述第一掩模板的第二区域对应的所述绝缘层膜层的区域处形成所述绝缘层的所述半保留区域的图形;在与所述第一掩模板的第三区域对应的所述绝缘层膜层的区域处形成所述绝缘层的所述过孔区域的图形;其中,
当所述感光性有机材料为正性感光材料时,所述第一掩模板的第一区域为遮光区域,第二区域为部分透光区域,第三区域为完全透光区域;
当所述感光性有机材料为负性感光材料时,所述第一掩模板的第一区域为完全透光区域,第二区域为部分透光区域,第三区域为遮光区域。
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- 2016-02-02 CN CN201610072900.6A patent/CN105514125B/zh not_active Expired - Fee Related
- 2016-05-05 US US15/501,424 patent/US20180046045A1/en not_active Abandoned
- 2016-05-05 WO PCT/CN2016/081146 patent/WO2017133097A1/zh active Application Filing
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