CN105514025B - The method that the air gap is formed between conducting wire - Google Patents
The method that the air gap is formed between conducting wire Download PDFInfo
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- CN105514025B CN105514025B CN201410503278.0A CN201410503278A CN105514025B CN 105514025 B CN105514025 B CN 105514025B CN 201410503278 A CN201410503278 A CN 201410503278A CN 105514025 B CN105514025 B CN 105514025B
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Abstract
The present invention provides a kind of method that the air gap is formed between conducting wire, the conductor structure surface being included on substrate forms silicon nitride liner, the ultra-thin lining of polysilicon for covering the silicon nitride liner is re-formed, photoresist of the top surface less than the top surface of conductor structure is then formed in the raceway groove between conductor structure.Then, covering photoresist and the oxide layer on the surface of the ultra-thin lining of polysilicon, and oxide layer described in anisotropic etching are conformally formed, oxide spacer is formed with the conductor structure side wall above photoresist.Afterwards, the photoresist is removed, to expose the ultra-thin lining of the polysilicon in raceway groove, and using the oxide spacer as mask, removes the ultra-thin lining of the polysilicon exposed.Then, oxide spacer is removed, reoxidizes the ultra-thin lining of remaining polysilicon, the top that it is made to be changed into silicon oxide layer and closes the raceway groove.
Description
Technical field
The invention relates to a kind of technology for improving the parasitic capacitance between conducting wire, and in particular to one kind in conducting wire
Between formed the air gap (air gap) method.
Background technology
The development of semiconductor subassembly has been reached below tens nanometer even to this day, but with the line of semiconductor lead structure
Away from significantly reducing, raised parasitic capacitance (parasitic capacitance) but brings undesirable influence.
Therefore, current improvement project has the spatial deposition between two conductor structures compared with the material of low-k (k) value
Material (such as oxide) substitutes silicon nitride, but such mode cannot meet component that develop to 30 nanometers of generations later
Design.So there is the space between two conductor structures recently, the air gap is formed to substitute the research of oxide, because air
Dielectric constant (k) value it is minimum.Formation for the air gap, some research are that non-conformal (non-is deposited on conducting wire
Conformal) dielectric material or closed on conducting wire using grain size more than the nano-particle of line-spacing between conducting wire
Space.
However, being likely to form the inconsistent the air gap of height with upper type or nano-particle is inserted between conducting wire
The problem of.
The content of the invention
The present invention provides a kind of method that the air gap is formed between conducting wire, can form consistent the air gap.
A kind of in the present invention is formed between conducting wire in the method for the air gap, is provided one and has been formed on several and leads
The substrate of cable architecture, wherein each conductor structure includes at least conductor layer and the cap rock at the top of the conductor layer.In institute
The surface for stating conductor structure forms silicon nitride liner, the formation ultra-thin lining of polysilicon on the conductor structure, described in covering
Silicon nitride liner.Then, photoresist is filled up in the raceway groove between the conductor structure, then removes part photoresist, make photoetching
The top surface of glue is less than the top surface of conductor structure.Afterwards, oxide layer is conformally formed on conductor structure, covers photoresist and polycrystalline
The surface of the ultra-thin lining of silicon.Then, oxide layer described in anisotropic etching, with the conductor structure side wall above photoresist
Oxide spacer is formed, photoresist is removed afterwards, to expose the ultra-thin lining of the polysilicon in raceway groove.Then, with oxidation
Object clearance wall is mask, removes the ultra-thin lining of the polysilicon exposed, then oxide spacer is removed, and makes remaining polysilicon
Ultra-thin lining exposes.Then, the ultra-thin lining of the polysilicon is aoxidized, it is made to be changed into silicon oxide layer and closes the upper of the raceway groove
Portion.
In one embodiment of this invention, the method for above-mentioned removal part photoresist includes controlling the top surface of the photoresist
More than conductor layer.
In one embodiment of this invention, the method for above-mentioned removal part photoresist includes controlling the top surface of the photoresist
Between the 10%~50% of depth of cover.
In one embodiment of this invention, the thickness of the ultra-thin lining of above-mentioned polysilicon is below 10 nanometers.
In one embodiment of this invention, the method for the ultra-thin lining of polysilicon that above-mentioned removal exposes is lost including wet type
It carves.
In one embodiment of this invention, the method for above-mentioned removal part photoresist is included first to the photoresist
Mechanical lapping is learned, until exposing its top surface, then photoresist described in etch-back.
In one embodiment of this invention, the method for oxide layer is conformally formed on above-mentioned conductor structure includes atomic layer
Sedimentation (atomic layer deposition, ALD).
In one embodiment of this invention, the method for the above-mentioned ultra-thin lining of oxidation polysilicon includes free-radical oxidation method
(radical oxidation) or low temperature wet oxidation process (low-temperature wet oxidation).
It in one embodiment of this invention, can also be to the ultra-thin lining of polysilicon before the above-mentioned ultra-thin lining of oxidation polysilicon
Layer carries out epitaxial growth (epitaxial growth), to increase its thickness.
In one embodiment of this invention, after above-mentioned epitaxial growth is carried out, the ultra-thin lining of polysilicon it is described
Thickness can increase by 1.5 times~2 times.
It, can essence by controlling the top surface of photoresist based on above-mentioned, the method for the invention that the air gap is formed between conducting wire
The really height of control the air gap, and the oxidation of the ultra-thin lining of polysilicon by conductor structure top can be completed between air
The sealing of gap achievees the effect that reduce parasitic capacitance.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed that attached drawing is coordinated to make
Carefully it is described as follows.
Description of the drawings
Figure 1A to Fig. 1 J is a kind of manufacturing process section that the air gap is formed between conducting wire of one embodiment of the invention
Schematic diagram；
Fig. 2 is another technique diagrammatic cross-section of the embodiment of the present invention.
Reference sign：
100：Substrate；
102：Conductor structure；
104：Conductor layer；
106：Cap rock；
108a、116a：Top surface；
108b：Side wall；
110：Silicon nitride liner；
112、112a：The ultra-thin lining of polysilicon；
114：Raceway groove；
116：Photoresist；
118：Scope；
120：Oxide layer；
120a：Oxide spacer；
122：Silicon oxide layer；
124：The air gap；
200：Polysilicon epitaxial layer；
S1、S2、S3：Distance；
t1、t2、t3、t4：Thickness.
Specific embodiment
Attached drawing is refer to herein, more fully to know from experience idea of the invention, the present invention is shown in annexed drawings
Embodiment.But many various forms also can be used to put into practice in the present invention, and should not be construed as limited to beneath described
Embodiment.In fact, it is only to make the present invention more will be detailed and complete to provide embodiment, and fully convey the scope of the invention to
Those of ordinary skill in the art.
In the accompanying drawings, for clarity the size and relative size in each layer and region may be made the description exaggerated.
Figure 1A to Fig. 1 J is a kind of manufacturing process section that the air gap is formed between conducting wire of one embodiment of the invention
Schematic diagram.
Figure 1A is refer to, is formed with several wires structure 102 on the substrate 100, since this figure is shown with section, so
Such as strip of conductor structure 102 simultaneously extends linear structure on the substrate 100, but the present invention is not limited thereto.Each conducting wire knot
Structure 102 includes at least conductor layer 104 and the cap rock 106 positioned at 104 top of conductor layer.Conductor layer 104 can be individual layer
Or multilayered structure, and the part contacted with substrate 100 can set gate oxide.The material of cap rock 106 is then such as silicon nitride etc
Non-conductive material can protect conductor layer 104 during subsequent technique.At this point, the distance between conductor structure 102 S1 is line-spacing
(line space)；For example, the present embodiment was applicable in the semiconductor technology nanometer generation, so distance S1 is about tens of
Ran, such as less than 40 nanometers.
Then, Figure 1B is refer to, in forming silicon nitride liner 110, only several nanometers of thickness, therefore can be complete on substrate 100
Coat the top surface 108a and side wall 108b of the structure in Figure 1B.At this point, distance S2 can shortening further than distance S1 in Figure 1A.
Then, Fig. 1 C are refer to, the ultra-thin lining 112 of polysilicon is formed, covers the silicon nitride liner 110.In this implementation
In example, the so-called ultra-thin lining 112 of polysilicon refers to ultrathin membranes of the thickness t1 below 10 nanometers, and the size of thickness t1 is basic
The upper distance S1 depending on Figure 1A, preferably about between 3nm~5nm, and its forming method is for example using silane (silane)
Raw material or the use faster disilane of reaction rate (disilane) are raw material, to form fine and close and flat ultrathin membrane.
After the ultra-thin lining 112 of polysilicon is formed, the width (i.e. distance S3) of raceway groove 114 can further reduce.
Then, Fig. 1 D are refer to, fill up photoresist 116 in the raceway groove 114 between conductor structure 102, such as with coating
Mode photoresist 116 is formed on substrate 100.
Then, Fig. 1 E are refer to, remove part photoresist 116, the top surface 116a of photoresist 116 is made to be less than top surface 108a.
Moreover, because the position of top surface 116a will influence the height for the air gap being subsequently formed, photoetching can be further controlled
The top surface 116a of glue 116 is in conductor layer more than 104.For example, the top surface 116a of the photoresist 116 can be controlled in cap rock
In scope 118 between the 10%~50% of 106 thickness t2.As for remove part photoresist 116 method for example to Fig. 1 D's
Photoresist 116 carries out chemical mechanical grinding, until exposing ultra-thin 112 top surface of lining of polysilicon, then photoresist described in etch-back
116。
Afterwards, Fig. 1 F be refer to, oxide layer 120 is conformally formed on conductor structure 102, by photoresist 116 with it is more
The surface covering of the ultra-thin lining 112 of crystal silicon.Form method such as atomic layer deposition method (the atomic layer of oxide layer 120
Deposition, ALD), and the temperature of depositing operation is for example between 60 DEG C~80 DEG C.
Then, Fig. 1 G, the oxide layer 120 of anisotropic etching Fig. 1 F, with the conducting wire knot above photoresist 116 be refer to
102 side wall 108b of structure forms oxide spacer 120a, and exposes the top of the ultra-thin lining 112 of polysilicon and part photoresist
116。
Then, Fig. 1 H are refer to, all photoresists 116 are removed, reveal the ultra-thin lining 112 of the polysilicon in raceway groove 114
Go out, then using oxide spacer 120a as mask, it is ultra-thin that example removes the polysilicon exposed with the mode of such as Wet-type etching etc
Lining 112, until exposing the silicon nitride liner 110 in the raceway groove 114 under oxide spacer 120a.Since Wet-type etching is
Isotropic etching, so the ultra-thin lining 112a of the polysilicon covered by oxide spacer 120a can be inside contracted slightly.
Then, Fig. 1 I are refer to, the oxide spacer in Fig. 1 H is removed, makes the ultra-thin lining 112a of remaining polysilicon
Expose.
Then, Fig. 1 J are refer to, the ultra-thin lining 112a of polysilicon of oxidation Fig. 1 I makes it be changed into silicon oxide layer 122, by
Volume can expand about 1.6 times after oxidation, so silicon oxide layer 122 can close the top of raceway groove, and between conductor structure 102
Form the air gap 124.Aoxidize the method such as free-radical oxidation method (radical of the ultra-thin lining 112a of polysilicon
Oxidation) or low temperature wet oxidation process (low-temperature wet oxidation), to make at a lower temperature
The ultra-thin lining 112a of polysilicon is completely transformed into silicon oxide layer 122, but the present invention is not limited thereto.
From Fig. 1 J, other structures presence is had no between conductor structure 102 in addition to silicon nitride liner 110, so
Even if semiconductor line away from tapering into, still ensures that the effective distance of the air gap 124, and in the present embodiment, by
The height of top surface 116a is controlled when removing part photoresist 116, can make in subsequent steps out position with it is highly consistent
The air gap 124.
In addition, if the ultra-thin lining 112a of polysilicon in Fig. 1 I is as shown in Fig. 2, its thickness t3 may after oxidation still
It can not close the space between cap rock 106, therefore first can carry out epitaxial growth by lining 112a ultra-thin to polysilicon, by into growing
The polysilicon epitaxial layer 200 come increases integral thickness.The step of can carrying out Fig. 1 J afterwards.Carrying out the epitaxial growth phase
Between, because the structures such as substrate 100 and conductor layer 104 are all covered by silicon nitride liner 110, epitaxial layer can't be grown.And
After epitaxial growth, the thickness t4 of the ultra-thin lining of polysilicon for example increases by 1.5 times~2 times, but the present invention is not limited thereto.
In conclusion the method for the present invention can control the height of the air gap by photoresist, and it is located at by oxidation and is led
The ultra-thin lining of polysilicon on cable architecture top, to help the sealing of the air gap.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe is described in detail the present invention with reference to foregoing embodiments, it will be understood by those of ordinary skill in the art that：Its according to
Can so modify to the technical solution recorded in foregoing embodiments either to which part or all technical characteristic into
Row equivalent substitution；And these modifications or replacement, the essence of appropriate technical solution is not made to depart from various embodiments of the present invention technology
The scope of scheme.
Claims (9)
- A kind of 1. method that the air gap is formed between conducting wire, which is characterized in that including：Substrate is provided, is formed with plurality of wires structure on the substrate, wherein each conductor structure is included at least and led Body layer and the cap rock at the top of the conductor layer；Silicon nitride liner is formed in the surface of the conductor structure；In forming the ultra-thin lining of polysilicon on the conductor structure, the silicon nitride liner, the ultra-thin lining of polysilicon are covered Thickness below 10 nanometers；Photoresist is filled up in raceway groove between the conductor structure；The part photoresist is removed, the top surface of the photoresist is made to be less than the top surface of the conductor structure；Oxide layer is conformally formed on the conductor structure, covers the table of the photoresist and the ultra-thin lining of the polysilicon Face；Oxide layer described in anisotropic etching forms oxide gap with the conductor structure side wall above the photoresist Wall；The photoresist is removed, to expose the ultra-thin lining of the polysilicon in the raceway groove；Using the oxide spacer as mask, the ultra-thin lining of the polysilicon exposed is removed；The oxide spacer is removed, to expose the ultra-thin lining of the polysilicon；AndThe ultra-thin lining of the polysilicon is aoxidized, the top that it is made to be changed into silicon oxide layer and closes the raceway groove.
- 2. the method according to claim 1 that the air gap is formed between conducting wire, which is characterized in that remove the part light The method of photoresist includes controlling the top surface of the photoresist more than the conductor layer.
- 3. the method according to claim 2 that the air gap is formed between conducting wire, which is characterized in that remove the part light The method of photoresist includes controlling the top surface of the photoresist between the 10%~50% of the thickness of the cap rock.
- 4. the method according to claim 1 that the air gap is formed between conducting wire, which is characterized in that remove the institute exposed Stating the method for the ultra-thin lining of polysilicon includes Wet-type etching.
- 5. the method according to claim 1 that the air gap is formed between conducting wire, which is characterized in that remove the part light The method of photoresist includes：Chemical mechanical grinding is carried out to the photoresist, the top surface until exposing the ultra-thin lining of polysilicon；AndPhotoresist described in etch-back.
- 6. the method according to claim 1 that the air gap is formed between conducting wire, which is characterized in that in the conductor structure On be conformally formed the oxide layer method include atomic layer deposition method.
- 7. the method according to claim 1 that the air gap is formed between conducting wire, which is characterized in that aoxidize the polysilicon The method of ultra-thin lining includes free-radical oxidation method or low temperature wet oxidation process.
- 8. the method according to claim 1 that the air gap is formed between conducting wire, which is characterized in that aoxidizing the polycrystalline Before the ultra-thin lining of silicon, further include and epitaxial growth is carried out to the ultra-thin lining of the polysilicon, to increase the ultra-thin lining of the polysilicon The thickness of layer.
- 9. the method according to claim 8 that the air gap is formed between conducting wire, which is characterized in that carrying out the extension After growth, the thickness of the ultra-thin lining of polysilicon increases by 1.5 times~2 times.
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| CN113013100A (en) * | 2019-12-20 | 2021-06-22 | 台湾积体电路制造股份有限公司 | Method for forming semiconductor device |
| US11901220B2 (en) | 2019-12-20 | 2024-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bilayer seal material for air gaps in semiconductor devices |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201304068A (en) * | 2011-07-04 | 2013-01-16 | Hynix Semiconductor Inc | Semiconductor device with buried bit line and method for fabricating the same |
| TW201409714A (en) * | 2012-08-29 | 2014-03-01 | Taiwan Semiconductor Mfg | Semiconductor device and methods for forming the same |
| CN103903994A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Semiconductor device including air gaps and method of fabricating the same |
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| US8642252B2 (en) * | 2010-03-10 | 2014-02-04 | International Business Machines Corporation | Methods for fabrication of an air gap-containing interconnect structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201304068A (en) * | 2011-07-04 | 2013-01-16 | Hynix Semiconductor Inc | Semiconductor device with buried bit line and method for fabricating the same |
| TW201409714A (en) * | 2012-08-29 | 2014-03-01 | Taiwan Semiconductor Mfg | Semiconductor device and methods for forming the same |
| CN103903994A (en) * | 2012-12-26 | 2014-07-02 | 爱思开海力士有限公司 | Semiconductor device including air gaps and method of fabricating the same |
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