CN106449389B - Embedded flash memory structure and preparation method thereof - Google Patents
Embedded flash memory structure and preparation method thereof Download PDFInfo
- Publication number
- CN106449389B CN106449389B CN201610922247.8A CN201610922247A CN106449389B CN 106449389 B CN106449389 B CN 106449389B CN 201610922247 A CN201610922247 A CN 201610922247A CN 106449389 B CN106449389 B CN 106449389B
- Authority
- CN
- China
- Prior art keywords
- layer
- barrier layer
- flash memory
- floating gate
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 230000004888 barrier function Effects 0.000 claims abstract description 103
- 238000007667 floating Methods 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 claims abstract description 30
- 230000000717 retained effect Effects 0.000 claims abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 39
- 229920005591 polysilicon Polymers 0.000 claims description 39
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- 239000011248 coating agent Substances 0.000 claims description 21
- 238000000576 coating method Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 18
- 230000008021 deposition Effects 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims 2
- 230000008878 coupling Effects 0.000 abstract description 13
- 238000010168 coupling process Methods 0.000 abstract description 13
- 238000005859 coupling reaction Methods 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000012212 insulator Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention discloses a kind of embedded flash memory structure and preparation method thereof, the production method includes: to provide a substrate, forms a FGS floating gate structure on the substrate；The FGS floating gate structure is etched, forms a groove in the FGS floating gate structure；A barrier layer is deposited, the barrier layer covers side wall and the bottom of the groove；A first medium layer is formed on the barrier layer of the bottom portion of groove；The barrier layer is removed, the barrier layer under the first medium layer is retained；An erasing grid structure is formed on the barrier layer remained.The embedded flash memory structure formed in this way can reduce the coupling ratio of the erasing grid and floating gate, improve the efficiency of erasing of the embedded flash memory structure；It can also enough improving " smile effect " in device, the performance of device is improved.
Description
Technical field
The present invention relates to a kind of technical field of manufacturing semiconductors, more particularly to a kind of embedded flash memory structure and its production
Method.
Background technique
The advantages that flash memory is convenient with its, and storage density is high, good reliability is as the hot spot studied in non-volatility memorizer.
Since first flash memory products appearance of the 1980s, with the development of technology with each electronic product to storage
Demand, flash memory are widely used in mobile phone, and notebook, palm PC and USB flash disk etc. are mobile in communication apparatus, and nowadays flash memory has accounted for
According to most of market share of non-volatile semiconductor memory, become non-volatile semiconductor memory with fastest developing speed.
It is well known that the direct shadow of size of the coupling ratio between the erasing grid (EG) and floating gate (FG) of embedded flash memory structure
Ring the efficiency of erasing of embedded flash memory structure.In the prior art, one layer finer and close two is deposited between floating gate and erasing grid
Silica, on the one hand which is used as tunneling oxide layer, on the other hand also as the separation layer between EG and FG, this side
Formula improves the efficiency of erasing of embedded flash memory structure to a certain extent, still, the erasing grid that make by this way and floating
The coupling ratio of grid is difficult to continue to reduce.Therefore, how to continue to reduce the coupling ratio for wiping grid and floating gate to improve embedded flash memory
Structure efficiency of erasing becomes a great problem that those skilled in the art face.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of embedded flash memory structures and preparation method thereof, can be improved
The efficiency of erasing of flash memory structure improves the isolation method between erasing grid and floating gate by optimization technique, reduces erasing to realize
The coupling ratio of grid and floating gate and the efficiency of erasing for improving flash memory structure.
In order to solve the above technical problems, a kind of production method of embedded flash memory structure provided by the invention, comprising:
One substrate is provided, forms a FGS floating gate structure on the substrate；
The FGS floating gate structure is etched, forms a groove in the FGS floating gate structure；
A barrier layer is deposited, the barrier layer covers side wall and the bottom of the groove；
A first medium layer is formed on the barrier layer of the bottom portion of groove；
The barrier layer is removed, the barrier layer under the first medium layer is retained；
An erasing grid structure is formed on the barrier layer remained.
Further, the forming step of the FGS floating gate structure includes: to be sequentially depositing floating gate from bottom to top on the substrate
Dielectric layer and control gate polysilicon layer between polysilicon layer, grid.
Further, in the step of etching the FGS floating gate structure, forming a groove in the FGS floating gate structure, comprising:
Dielectric layer is sequentially etched between control gate polysilicon layer, the grid to the upper surface of the floating gate polysilicon layer to form first
Opening；Continue to etch the bottom of first opening until through the floating gate polysilicon layer to form the second opening, described the
The cross-sectional width of two openings is less than the cross-sectional width of first opening, and the first opening and the second opening form described recessed
Slot.
Optionally, in the production method of the embedded flash memory structure, in the floating gate polysilicon layer and the base
One first tunnel oxide skin(coating) is also deposited between bottom.
Preferably, in the production method of the embedded flash memory structure, the upper surface of the first medium layer is lower than
The upper surface of the floating gate polysilicon layer.
Optionally, a barrier layer is being deposited, in the step of barrier layer covers side wall and the bottom of the groove, including
A second dielectric layer is deposited, the second dielectric layer covers side wall and the bottom of the groove；It sinks in the second dielectric layer
The product barrier layer.
It further, further include described in removal before depositing the erasing grid structure after removing the barrier layer
Second dielectric layer.
Optionally, in the production method of the embedded flash memory structure, the barrier layer is removed by wet etching
With the second dielectric layer.
Preferably, in the production method of the embedded flash memory structure, the second medium is removed using hydrofluoric acid
Layer.
Further, in the production method of the embedded flash memory structure, when removing the second dielectric layer, also
Including removing the first medium layer.
Optionally, in the production method of the embedded flash memory structure, the first medium layer and second dielectric layer
It is oxide skin(coating).
It optionally, include: one oxidation of deposition the step of forming a first medium layer on the barrier layer of the bottom portion of groove
Object, the oxide cover the barrier layer and fill the full groove；The oxide is etched, the bottom portion of groove is retained
The oxide on barrier layer, to form the first medium layer.
Preferably, in the step of deposition one wipes grid structure on the barrier layer remained, it is included in and retains
Come the barrier layer on and the groove one second tunnel oxide skin(coating) of deposited on sidewalls, in the second tunnel oxide
An erasing gate polysilicon layer is formed on layer.
Preferably, in the production method of the embedded flash memory structure, the barrier layer is silicon nitride layer.
Optionally, in the production method of the embedded flash memory structure, the nitrogen is removed using phosphoric acid wet etching
SiClx layer.
Another side according to the present invention, the present invention also provides a kind of embedded flash memory structures, comprising:
One substrate；
One FGS floating gate structure, the FGS floating gate structure are located on the substrate；
One groove, the groove are located in the FGS floating gate structure；
One erasing grid structure, the erasing grid structure are located on the substrate and are located in the groove；And
One barrier layer, between the erasing grid structure and the substrate, the barrier layer prevents the substrate and institute
Erasing grid structure is stated to be oxidized.
Further, in the embedded flash memory structure, the FGS floating gate structure include on the substrate from down toward
On the floating gate polysilicon layer, dielectric layer and the control gate polysilicon layer between grid that stack gradually.
Optionally, it in the embedded flash memory structure, is also wrapped between the substrate and the floating gate polysilicon layer
Include one first tunnel oxide skin(coating).
Preferably, in the embedded flash memory structure, the upper surface on the barrier layer is lower than the floating gate polysilicon
The upper surface of layer.
Further, in the embedded flash memory structure, the erasing grid structure includes one positioned at the barrier layer
On the second tunnel oxide skin(coating) and one be located at the second tunnel oxide skin(coating) on erasing gate polysilicon layer.
Preferably, in the embedded flash memory structure, the material on the barrier layer is silicon nitride.
Compared with prior art, the invention has the following advantages:
The present invention in the groove in the FGS floating gate structure by depositing a barrier layer, then in the resistance of the bottom portion of groove
A first medium layer is formed in barrier, removes the barrier layer, retains the barrier layer under the first medium layer, finally,
Erasing grid structure is re-formed on the barrier layer remained.The embedded flash memory structure formed in this way,
It is isolated between EG and FG by the barrier layer, the coupling ratio of EG and FG can be reduced, improves the embedded flash memory
The efficiency of erasing of structure；Moreover, including a barrier layer between the erasing grid structure and the substrate, the barrier layer can be with
It prevents the substrate and the erasing grid structure to be oxidized, " smile effect " in device can be improved, improve the performance of device.
Further, the material on the barrier layer is silicon nitride, and silicon nitride can reduce EG and FG for EG and FG to be isolated
Coupling ratio, improve the efficiency of erasing of the embedded flash memory structure.
Detailed description of the invention
Fig. 1 is the flow chart of the production method of embedded flash memory structure in the embodiment of the present invention；
Structure Fig. 2 to Figure 10 corresponding for each step in embedded flash memory construction manufacturing method in the embodiment of the present invention
Schematic diagram.
Specific embodiment
Inventor in the course of the research, in the prior art, be isolated between EG and FG using silica by discovery, but
In the case where the finite thickness system of silica, have no idea again to further decrease the coupling ratio of EG and FG；Meanwhile corresponding
Thermal oxide during, oxygen can pass through the silica and polycrystalline pasc reaction, to form thicker oxide layer, emhasizer
" smile effect " of part, to influence the performance of device.Therefore, inventor considers to improve between EG and FG by optimization technique
Isolation, to further decrease the coupling ratio of EG and FG, improve the efficiency of erasing of device to improve embedded flash memory structure,
And " smile effect " for mitigating device, improves the performance of device.
Based on the studies above and discovery, inventor provides a kind of production method of embedded flash memory structure, comprising:
S1, a substrate is provided, forms a FGS floating gate structure on the substrate；
S2, the etching FGS floating gate structure, form a groove in the FGS floating gate structure；
S3, one barrier layer of deposition, the barrier layer covers side wall and the bottom of the groove；
S4, a first medium layer is formed on the barrier layer of the bottom portion of groove；
S5, the removal barrier layer, retain the barrier layer under the first medium layer；
S6, an erasing grid structure is formed on the barrier layer remained.
Correspondingly, another side according to the present invention, the present invention also provides a kind of embedded flash memory structures, comprising:
One substrate；
One FGS floating gate structure, the FGS floating gate structure are located on the substrate；
One groove, the groove are located in the FGS floating gate structure；
One erasing grid structure, the erasing grid structure are located on the substrate and are located in the groove；And
One barrier layer, between the erasing grid structure and the substrate, the barrier layer prevents the substrate and institute
Erasing grid structure is stated to be oxidized.
The present invention in the groove in the FGS floating gate structure by depositing a barrier layer, then in the resistance of the bottom portion of groove
A first medium layer is formed in barrier, removes the barrier layer, retains the barrier layer under the first medium layer, finally,
Erasing grid structure is re-formed on the barrier layer remained.The embedded flash memory structure formed in this way,
It is isolated between EG and FG by the barrier layer, the coupling ratio of EG and FG can be reduced, improves the embedded flash memory
The efficiency of erasing of structure；Moreover, including a barrier layer between the erasing grid structure and the substrate, the barrier layer can be with
It prevents the substrate and the erasing grid structure to be oxidized, " smile effect " in device can be improved, improve the performance of device.
A kind of embedded flash memory structure of the invention and preparation method thereof is carried out below in conjunction with flow chart and schematic diagram
More detailed description, which show the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can modify herein
The present invention of description, and still realize advantageous effects of the invention.Therefore, following description should be understood as this field skill
Art personnel's is widely known, and is not intended as limitation of the present invention.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
A kind of insertion of the invention is discussed in detail in the embodiment of embedded flash memory structure exemplified below and preparation method thereof
The content of formula flash memory structure and preparation method thereof, it is understood that, the contents of the present invention are not restricted to following embodiment,
He is by the improvement of the conventional technical means of those of ordinary skill in the art also within thought range of the invention.
Fig. 1 is please referred to Figure 10, wherein Fig. 1 is the stream of the production method of embedded flash memory structure described in the present embodiment
Cheng Tu, Fig. 2 then illustrate the corresponding structural schematic diagram of each step in the production method to Figure 10.As shown in Figure 1, described
The specific steps of production method include:
Step S1 provides a substrate 10, and a FGS floating gate structure 11 is formed in the substrate 10.Specifically, as shown in Fig. 2,
It is sequentially depositing dielectric layer between the first tunnel oxide skin(coating) 110, floating gate polysilicon layer 111, grid from bottom to top in the substrate 10
112 and control gate polysilicon layer 113.In the present embodiment, the substrate 10 is silicon substrate, certainly, in other embodiments, institute
Stating substrate 10 can also be Ge substrate, SiGe substrate, SiC substrate, SOI (silicon-on-insulator, Silicon On Insulator)
Substrate or GOI (germanium on insulator, Germanium On Insulator) substrate etc., can also be includes other elements semiconductor
Or the substrate of compound semiconductor, such as glass substrate or III-V compound substrate (such as gallium nitride substrate or GaAs lining
Bottom etc.), it can also be laminated construction, such as Si/SiGe etc. can be with other epitaxial structures, such as SGOI (germanium on insulator
Silicon) etc..Dielectric layer 112 can be ONO (oxidenitride oxide) layer 112 between the grid.
Step S2 etches the FGS floating gate structure 11, forms a groove in the FGS floating gate structure 11.It is detailed, in step
After S1, firstly, depositing a hard mask layer 12 on the control gate polysilicon layer 113, as shown in Figure 2；Then, pass through photoetching
And etching technics, it is sequentially etched dielectric layer 112 between the hard mask layer 12, the control gate polysilicon layer 113, grid and is floated to described
The upper surface of gate polysilicon layer 111 forms an opening A1, as shown in Figure 3；Next, continuing to etch first opening bottom A1
Portion is until run through the floating gate polysilicon layer 111 (upper surface of the i.e. described first tunnel oxide skin(coating) 110), to form described the
Two opening A2, the cross-sectional width of the second opening A2 are less than the cross-sectional width of the first opening A1, the first opening A1
The groove is constituted with the second opening A2, as shown in Figure 4.Described in the step first opening A1 and second opening A2 formation be
It is realized using lithography and etching technique well known to those of ordinary skill in the art, this will not be repeated here.
Step S3 deposits a barrier layer 14, and the barrier layer 14 covers side wall and the bottom of the groove.Preferably, such as
Shown in Fig. 5, a second dielectric layer 13 is first deposited, the second dielectric layer 13 covers side wall and the bottom of the groove, certainly, sinks
The long-pending second dielectric layer 13 also covers the hard mask layer 12；Then, the resistance is deposited in the second dielectric layer 13
Barrier 14.Preferably, in the present embodiment, the material of the second dielectric layer 13 can be silica, and the barrier layer 14 is
Silicon nitride layer 14.
Step S4 forms a first medium layer 15 ' on the barrier layer of the bottom portion of groove.Fig. 6 and Fig. 7 are please referred to, it is excellent
Choosing, the material of the first medium layer 15 ' is oxide, specifically, the forming step of the first medium layer 15 ' is as follows:
Firstly, deposition monoxide 15, the oxide 15 covers the barrier layer 14 and fills the full groove；Then, then to institute
It states oxide 15 to carry out back being carved into required thickness, i.e., retains the certain thickness oxide in the bottom portion of groove, with
Form the first medium layer 15 '.In addition, the upper surface of the first medium layer 15 ' is no more than the floating gate polysilicon layer 111
Upper surface, the oxide can be silica.
Step S5 removes the barrier layer 14, retains the barrier layer 14 ' under the first medium layer 15 '.It is preferred that
, in the present embodiment, the material on the barrier layer 14 is silicon nitride, therefore, can pass through barrier layer described in wet etching
14, further, the barrier layer 14 is removed with hot phosphoric acid.Because having described on the barrier layer of the bottom portion of groove
The protection of one dielectric layer 15 ', so, by the above process after, the barrier layer 14 ' under the first medium layer 15 ' will retain
Get off (upper surface that the upper surface on the barrier layer 14 ' remained is lower than the floating gate polysilicon layer 111), such as Fig. 8
It is shown.
Next, continuing through wet etching removes the second dielectric layer 13, preferably, described in being removed using hydrofluoric acid
Second dielectric layer 13.Similarly, the second dielectric layer 13 ' under the barrier layer 14 ' remained can also remain.Together
When, because the first medium layer 15 ' and second dielectric layer 13 are oxide skin(coating), then, removing the second dielectric layer 13
While, the first medium layer 15 ' can be also removed, and form structure as shown in Figure 9.
Step S6 above forms an erasing grid structure 16 on the barrier layer 14 ' remained.In general, the erasing grid
The forming step of structure 16 are as follows: above and on the side wall of the groove first deposit one second on the barrier layer 14 ' remained
Then tunnel oxide skin(coating) 160 forms an erasing gate polysilicon layer 161 on the second tunnel oxide skin(coating) 160, is formed
Final device architecture, as shown in Figure 10.Certainly, corresponding etching technics is further related in the step, needing to obtain has centainly
The erasing gate polysilicon layer 161 of thickness, this be not emphasis and those skilled in the art of the invention it should be understood that
This inconvenience repeats.
Then, as shown in Figure 10, the embedded flash memory structure formed in the present embodiment includes: a substrate 10；One is located at institute
State the FGS floating gate structure 11 in substrate 10, wherein the FGS floating gate structure 11 includes first stacked gradually from bottom to top in substrate
Dielectric layer 112 and control gate polysilicon layer 113 between tunnel oxide skin(coating) 110, floating gate polysilicon layer 111, grid；One groove, it is described
Groove is located in the FGS floating gate structure 11；One erasing grid structure 16, the erasing grid structure 16 be located on the substrate 10 and
In the groove；One silicon nitride layer 14 ', between the erasing grid structure 16 and the substrate 10, the silicon nitride
Layer 14 ' is applied not only to the FGS floating gate structure 11 and wipes being isolated for grid structure 16 with described, can also prevent institute in subsequent heat treatment
State substrate 10 and the phenomenon that the erasing grid structure 16 is oxidized.The erasing grid structure 16 includes being located at the silicon nitride 14 '
On the second tunnel oxide skin(coating) 160 and the erasing gate polysilicon layer 161 on the second tunnel oxide skin(coating) 160.
In the present embodiment, by depositing a silicon nitride layer 14 in the groove in the FGS floating gate structure 11, then described
The first medium layer 15 ' is formed on the silicon nitride layer of bottom portion of groove, is removed the silicon nitride layer 14, is retained the first medium
The silicon nitride layer 14 ' under layer 15 ', finally, above forming erasing grid structure 16 in the silicon nitride layer 14 ' remained.
The embedded flash memory structure formed in this way is isolated between FG by the silicon nitride layer 14 ' in EG, can
To reduce the coupling ratio of EG and FG, the efficiency of erasing of embedded flash memory structure is improved；Moreover, in the erasing grid structure 16 and institute
Stating includes the silicon nitride layer 14 ' between substrate 10, and the silicon nitride layer 14 ' can prevent the substrate 10 and the erasing grid
Structure 16 is oxidized, and can be improved " smile effect " in device, be improved the performance of device.
To sum up, the present invention in the groove in the FGS floating gate structure by depositing a barrier layer, then in the groove-bottom
A first medium layer is formed on the barrier layer in portion, removes the barrier layer, retains the barrier layer under the first medium layer,
Finally, re-forming erasing grid structure on the barrier layer remained.The embedded flash memory formed in this way
Structure is isolated between EG and FG by the barrier layer, and the coupling ratio of EG and FG can be reduced, and is improved described embedded
The efficiency of erasing of flash memory structure；Moreover, including a barrier layer, the barrier layer between the erasing grid structure and the substrate
The substrate and the erasing grid structure can be prevented to be oxidized, " smile effect " in device can be improved, improve device
Performance.
Further, the material on the barrier layer is silicon nitride, and silicon nitride can reduce EG and FG for EG and FG to be isolated
Coupling ratio, improve the efficiency of erasing of the embedded flash memory structure.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification and " the
The descriptions such as two " are used only for distinguishing various components, element, step etc. in specification, without being intended to indicate that various components, member
Logical relation or ordinal relation between element, step etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
Claims (14)
1. a kind of production method of embedded flash memory structure, which is characterized in that the production method includes:
One substrate is provided, forms a FGS floating gate structure on the substrate；
The FGS floating gate structure is etched, forms a groove in the FGS floating gate structure；
A barrier layer is deposited, the barrier layer covers side wall and the bottom of the groove；
A first medium layer is formed on the barrier layer of the bottom portion of groove；
The barrier layer is removed, the barrier layer under the first medium layer is retained；On the barrier layer remained
Form an erasing grid structure；
In addition to the barrier layer remained, the embedded flash memory structure does not include other barrier layers；The blocking
Layer is silicon nitride layer；
Wherein, a barrier layer is being deposited, in the step of barrier layer covers side wall and the bottom of the groove, including deposition one
Second dielectric layer, the second dielectric layer cover side wall and the bottom of the groove；In the second dielectric layer described in deposition
Barrier layer；
It further include removing the second dielectric layer before depositing the erasing grid structure after removing the barrier layer；?
It further include removing the first medium layer when removing the second dielectric layer；
It include: deposition monoxide, the oxidation in the step of forming a first medium layer on the barrier layer of the bottom portion of groove
Object covers the barrier layer and fills the full groove；The oxide is etched, on the barrier layer for retaining the bottom portion of groove
The oxide, to form the first medium layer.
2. the production method of embedded flash memory structure as described in claim 1, which is characterized in that the formation of the FGS floating gate structure
Step includes: to be sequentially depositing dielectric layer and control gate polysilicon layer between floating gate polysilicon layer, grid from bottom to top on the substrate.
3. the production method of embedded flash memory structure as claimed in claim 2, which is characterized in that etching the floating gate knot
Structure, in the step of forming a groove in the FGS floating gate structure, comprising:
Dielectric layer is sequentially etched between control gate polysilicon layer, the grid to the upper surface of the floating gate polysilicon layer to be formed
First opening；
Continue to etch the bottom of first opening until through the floating gate polysilicon layer to form the second opening, described second
The cross-sectional width of opening is less than the cross-sectional width of first opening, and the first opening and the second opening form the groove.
4. the production method of embedded flash memory structure as claimed in claim 2, which is characterized in that in the floating gate polysilicon layer
One first tunnel oxide skin(coating) is also deposited between the substrate.
5. the production method of embedded flash memory structure as claimed in claim 2, which is characterized in that the first medium layer it is upper
Surface is lower than the upper surface of the floating gate polysilicon layer.
6. the production method of embedded flash memory structure as described in claim 1, which is characterized in that remove institute by wet etching
State barrier layer and the second dielectric layer.
7. the production method of embedded flash memory structure as claimed in claim 6, which is characterized in that using described in hydrofluoric acid removal
Second dielectric layer.
8. the production method of embedded flash memory structure as described in claim 1, which is characterized in that the first medium layer and
Second medium layer is oxide skin(coating).
9. the production method of the embedded flash memory structure as described in claim 1 to 8 any one, which is characterized in that retaining
Deposition one was wiped in the step of grid structure on the barrier layer got off, including on the barrier layer remained and described
The one second tunnel oxide skin(coating) of deposited on sidewalls of groove forms an erasing gate polysilicon on the second tunnel oxide skin(coating)
Layer.
10. the production method of embedded flash memory structure as described in claim 1, which is characterized in that use phosphoric acid wet etching
Remove the silicon nitride layer.
11. embedded flash memory structure made from a kind of production method using embedded flash memory structure described in claim 1,
It is characterized in that, comprising:
One substrate；
One FGS floating gate structure, the FGS floating gate structure are located on the substrate；
One groove, the groove are located in the FGS floating gate structure, and the groove includes the first opening and is open positioned at described first
Second opening of lower section, the cross-sectional width of second opening are less than the cross-sectional width of first opening；
One erasing grid structure, the erasing grid structure are located on the substrate and are located in the groove；And
One barrier layer, be only located at it is described erasing grid bottom and between the erasing grid structure and the substrate, the resistance
Barrier prevents the substrate and the erasing grid structure to be oxidized；Wherein, the erasing grid structure includes one positioned at the blocking
The second tunnel oxide skin(coating) and one on layer and the recess sidewall are located at the erasing on the second tunnel oxide skin(coating)
Gate polysilicon layer, in addition to the barrier layer, the embedded flash memory structure does not include other barrier layers；The material on the barrier layer
For silicon nitride.
12. embedded flash memory structure as claimed in claim 11, which is characterized in that the FGS floating gate structure is included in the substrate
On the floating gate polysilicon layer, dielectric layer and the control gate polysilicon layer between grid that stack gradually from bottom to top.
13. embedded flash memory structure as claimed in claim 12, which is characterized in that in the substrate and the floating gate polysilicon
It further include one first tunnel oxide skin(coating) between layer.
14. embedded flash memory structure as claimed in claim 12, which is characterized in that the upper surface on the barrier layer is lower than described
The upper surface of floating gate polysilicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610922247.8A CN106449389B (en) | 2016-10-21 | 2016-10-21 | Embedded flash memory structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610922247.8A CN106449389B (en) | 2016-10-21 | 2016-10-21 | Embedded flash memory structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106449389A CN106449389A (en) | 2017-02-22 |
| CN106449389B true CN106449389B (en) | 2019-09-17 |
Family
ID=58176984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610922247.8A Active CN106449389B (en) | 2016-10-21 | 2016-10-21 | Embedded flash memory structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106449389B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200802816A (en) * | 2006-06-27 | 2008-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6605840B1 (en) * | 2002-02-07 | 2003-08-12 | Ching-Yuan Wu | Scalable multi-bit flash memory cell and its memory array |
| US7046552B2 (en) * | 2004-03-17 | 2006-05-16 | Actrans System Incorporation, Usa | Flash memory with enhanced program and erase coupling and process of fabricating the same |
| CN105140187A (en) * | 2015-08-04 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Embedded flash memory structure and preparation method thereof |
-
2016
- 2016-10-21 CN CN201610922247.8A patent/CN106449389B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200802816A (en) * | 2006-06-27 | 2008-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106449389A (en) | 2017-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10504917B2 (en) | Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays | |
| US10665599B2 (en) | Integrated structures and methods of forming vertically-stacked memory cells | |
| CN104795331B (en) | The forming method of transistor | |
| CN104217962B (en) | Transistor and the method for manufacturing transistor | |
| CN109300973A (en) | Form the method and dependency structure of nanometer sheet transistor | |
| CN110249428A (en) | NAND memory array and the method for forming NAND memory array | |
| TWI615982B (en) | Memory device comprising sonos stack with split nitride memory layer and related manufacturing process | |
| US10672785B2 (en) | Integrated structures of vertically-stacked memory cells | |
| CN108649034B (en) | Semiconductor structure and forming method thereof | |
| CN103854989A (en) | Structures having uniform finFET gate height and forming method thereof | |
| CN108470737A (en) | Three-dimensional storage and its manufacturing method | |
| CN103681846A (en) | Semiconductor device and manufacturing method thereof | |
| CN107437549A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| TW201622063A (en) | Semiconductor device and method of manufacturing the same | |
| CN106449389B (en) | Embedded flash memory structure and preparation method thereof | |
| CN109872994A (en) | Split-gate flash memory and preparation method thereof | |
| CN105405809A (en) | Method of manufacturing flash memory | |
| CN107527858B (en) | Method for fabricating shallow trench in flash memory | |
| CN106025799B (en) | Use laser structure on the silicon of aspect ratio capture growth | |
| CN105448921B (en) | A kind of semiconductor devices and preparation method thereof and electronic device | |
| CN106972020A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| CN106960819A (en) | A kind of semiconductor devices and its manufacture method, electronic installation | |
| CN108550578A (en) | Three-dimensional storage manufacturing method | |
| CN106356293B (en) | Metal gates and preparation method thereof | |
| CN106298489B (en) | The preparation method of grid |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |