CN105512069A - Serializer and deserializer device and asynchronous conversion method thereof - Google Patents
Serializer and deserializer device and asynchronous conversion method thereof Download PDFInfo
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- CN105512069A CN105512069A CN201510887965.1A CN201510887965A CN105512069A CN 105512069 A CN105512069 A CN 105512069A CN 201510887965 A CN201510887965 A CN 201510887965A CN 105512069 A CN105512069 A CN 105512069A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The invention discloses a serializer and deserializer device. The serializer and deserializer device comprises a first phase locked loop device, a second phase locked loop device and a flip-flop. The first phase locked loop device receives a first frequency signal of a first cycle and generates a second frequency signal of a second cycle and a third frequency signal of a third cycle. The first phase locked loop device generates a flag signal according to the first frequency signal, the second frequency signal and the third frequency signal and transmits the flag signal to the second phase locked loop device. The second phase locked loop device synchronously receives the first frequency signal and generates a fourth frequency signal of the third cycle. The second phase locked loop device samples flag signals which are different in phase position according to the first frequency signal and the fourth frequency signal to obtain a reset signal, and the reset signal has nothing to do with phase diversity. The flip-flop receives the reset signal and the fourth frequency signal and correspondingly generates a fifth frequency signal which is synchronous with the second frequency signal and the same as the second frequency signal.
Description
Technical field
The invention relates to deserializer (serializer (Serializer)/deserializer (Deserializer)) device, relate to the asynchronous conversion method between the middle different PLL device being applied in deserializer device especially.
Background technology
The present invention discloses a kind of deserializer device, comprises the first PLL device, the second PLL device and flip-flop.First PLL device receives the first frequency signal of period 1, and produces the second frequency signal of second round and the 3rd frequency signal of period 3.First PLL device produces flag signals according to first, second, and third frequency signal, and flag signals is sent to the second PLL device.Second PLL device synchronously receives first frequency signal, and produces the 4th frequency signal of period 3.Second PLL device foundation first and the 4th frequency signal obtain reset signal to the flag signals sampling with phase difference, and reset signal and phase difference are had nothing to do.Flip-flop receives reset signal and the 4th frequency signal, and the 5th frequency signal that corresponding generation is synchronous and identical with second frequency signal.
Summary of the invention
An one exemplary embodiment of the present invention provides a kind of deserializer device.This deserializer device comprises one first PLL device, one second PLL device and a flip-flop.This first PLL device is in order to receive a first frequency signal of a period 1, and corresponding generation is less than a second frequency signal of a second round of this period 1 and one the 3rd frequency signal of a period 3, wherein this second round is the twice of this period 3.This second PLL device is in order to synchronously to receive this first frequency signal, and corresponding one the 4th frequency signal producing this period 3.This flip-flop is connected to this second PLL device, in order to receive a reset signal and one the 4th frequency signal of the output of this second PLL device, and one the 5th frequency signal that corresponding generation is synchronous and identical with this second frequency signal, wherein this first PLL device exports a flag signals according to this first frequency signal, this second frequency signal and the 3rd frequency signal; When wherein this flag signals is passed to this second PLL device, there is a phase difference; And wherein this second PLL device produces a sampled signal according to this first frequency signal and the 4th frequency signal, and use this sampled signal to obtain this reset signal to this flag signals sampling with this phase difference, this reset signal and this phase difference are had nothing to do.
An one exemplary embodiment of the present invention provides a kind of asynchronous conversion method for a deserializer device.The first frequency signal that this asynchronous conversion method comprises synchronized transmission one period 1 is to one first PLL device of this deserializer device and one second PLL device; Produce through this first PLL device and be less than a second frequency signal of a second round of this period 1 and one the 3rd frequency signal of a period 3, wherein this second round is the twice of this period 3; A flag signals is exported through this first PLL device, wherein this flag signals produces from this first frequency signal of this first PLL device, this second frequency signal and the 3rd frequency signal, and had a phase difference when this flag signals is passed to this second PLL device; One the 4th frequency signal of this period 3 is produced through this second PLL device; Produce a sampled signal through this second PLL device, wherein this sampled signal produces from this first frequency signal of this second PLL device and the 4th frequency signal; Use this sampled signal to obtain a reset signal to this flag signals sampling with this phase difference, this reset signal and this phase difference are had nothing to do; And receive this reset signal and the 4th frequency signal through a flip-flop of this deserializer device, produce one five frequency signal synchronous and identical with this second frequency signal with correspondence.
Accompanying drawing explanation
Fig. 1 is the block diagram realizing deserializer device 10 according to one first embodiment of the present invention;
Fig. 2 is the frequency plot that each frequency signal in deserializer device 10 is described according to first embodiment of the invention;
Fig. 3 is the circuit diagram realizing flag circuit 30 according to the second embodiment of the present invention;
Fig. 4 A to Fig. 4 D is the frequency plot that each frequency signal in flag circuit 30 is described according to second embodiment of the invention;
Fig. 5 A to Fig. 5 D is the frequency plot that each frequency signal in flag circuit 30 is described according to the third embodiment of the present invention;
Fig. 6 is the process flow diagram realizing being applicable to the asynchronous conversion method of deserializer device 10 according to of the present invention 1 the 4th embodiment.
Embodiment
The appended illustrated embodiment of this exposure or example will as described below.The category of this exposure is not as limit.Prior art person should be able to know under the prerequisite of the spirit and framework that do not depart from this exposure, when doing a little change, replacement and displacement.In the embodiment of this exposure, element numbers may be used repeatedly, and the connection with several embodiments of this exposure may share identical element numbers, but the features component used for an embodiment must not used by another embodiment.
Fig. 1 is the block diagram realizing a deserializer device 10 according to one first embodiment of the present invention.In the first embodiment of the invention, deserializer device 10 comprises one first PLL device 11,1 second PLL device 12 and a logical circuit 13.First PLL device 11 is in order to supply different frequency signals to the various low-frequency channels in deserializer device 10, and such as, clock data restores (ClockDataRecovery, CDR) circuit.Second PLL device 12 is in order to supply different clocks signal as high-frequency signal needed for the RX path in deserializer device 10.
In the first embodiment of the invention, first PLL device 11 and the second PLL device 12 synchronously receive a reference frequency signal REF100IN of an identical period 1, and wherein the time span of aforementioned period 1 was 10 how seconds (that is the frequency of first frequency signal REF100IN is 100MHz).
In the first embodiment of the invention, first PLL device 11 produces/exports a frequency signal CK250 of an a second round and frequency signal CK500 of a period 3 according to reference frequency signal REF100IN, wherein aforementioned second and the time span of period 3 be respectively for 4 how how seconds (that is the frequency of frequency signal CK250 and frequency signal CK500 is respectively 250MHz and 500MHz) second and 2.Logical circuit 13 is receiving frequency signals CK250 and frequency signal CK500 respectively, and correspondence exports the frequency signal LP_CTSCK250 of second round and the frequency signal LP_CTSCK500 to ethernet PHY transceiver 14 (ethernetphysicallayertransceiver14, EPHYTX14) of period 3 respectively.In the first embodiment of the invention, frequency signal LP_CTSCK250 and LP_CTSCK500 that ethernet PHY transceiver 14 receives is synchronized with reference frequency signal REF100IN.
In the first embodiment of the invention, the second PLL device 12 produces/exports a frequency signal TPLCK250 of a second round and frequency signal TPLCK500 of period 3 to each drawing lines (lane) in deserializer device 10 according to reference frequency signal REF100IN.In the first embodiment of the invention, frequency signal TPLCK500 be output in deserializer device 10 each drawing lines (lane) time Frequency Synchronization in reference frequency signal REF100IN.
In the first embodiment of the invention, the time span of aforementioned first, second or period 3 is not limited thereto, and this area has knows that the knowledgeable can understand the time span of aforementioned first, second or period 3 and can change according to the actual frequency demand of the first PLL device 11 of deserializer device 10 and the second PLL device 12 usually.
Fig. 2 is the frequency plot that each frequency signal in deserializer device 10 is described according to first embodiment of the invention.As shown in Figure 2, in the first embodiment of the invention, the frequency signal LP_CTSCK500 of period 3 and frequency signal TPLCK500 has been synchronized with reference frequency signal REF100IN all.Now, deserializer device 10 ensures that the frequency signal TPLCK250 of the frequency signal LP_CTSCK250 of the second round of the first PLL device 11 correspondence and the second round of the second PLL device 12 correspondence can both be synchronized with reference frequency signal REF100IN each other again through a flag circuit.Finally, when the frequency signal LP_CTSCK250 of the second round of the first PLL device 11 correspondence can be synchronized with reference frequency signal REF100IN time, the first PLL device 11 just the rising edge of frequency of utilization signal LP_CTSCK250 can correctly transmit data transfer signal to ethernet PHY transceiver 14; And when the frequency signal TPLCK250 of the second PLL device 12 correspondence can be synchronized with reference frequency signal REF100IN time, the second PLL device 12 just the negative edge of frequency of utilization signal TPLCK250 can correctly receive data transfer signal from ethernet PHY transceiver 14.Therefore, in the first embodiment of the invention, aforementioned flag circuit how is designed to ensure that frequency signal LP_CTSCK250 and frequency signal TPLCK250 can both be synchronized with reference frequency signal REF100IN each other and become the subject under discussion being badly in need of overcoming.
Fig. 3 is the circuit diagram realizing a flag circuit 30 according to one second embodiment of the present invention.In second embodiment of the invention, flag circuit 30 realizes first embodiment of the invention and states flag circuit in advance, to ensure that frequency signal LP_CTSCK250 and frequency signal TPLCK250 can both be synchronized with reference frequency signal REF100IN each other.
Conveniently describe, in flag circuit 30 shown in second embodiment of the invention, reference frequency signal REF100IN described in first embodiment represents with a first frequency signal M100 (or T100) of period 1, frequency signal LP_CTSCK250 described in first embodiment represents with a second frequency signal M250 of second round, frequency signal LP_CTSCK500 described in first embodiment represents with 1 of the period 3 the 3rd frequency signal M500, frequency signal TPLCTSCK500 described in first embodiment represents with 1 of the period 3 the 4th frequency signal T500, frequency signal TPLCTSCK250 described in first embodiment represents with 1 of second round the 5th frequency signal T250.
In second embodiment of the invention, flag circuit 30 comprises the first sub-flag circuit 31, second sub-flag circuit 32 and flip-flop 33, wherein the first sub-flag circuit 31 is arranged in the first PLL device 11, and the second sub-flag circuit 32 and flip-flop 33 are then arranged in the second PLL device 12.Flip-flop 33 is D type flip-flops, but the present invention is not limited thereto, and also can use other kenel flip-flops, such as, and RS flip-flop etc.
In second embodiment of the invention, first sub-flag circuit 31 of the first PLL device 11 receives first frequency signal M100, second frequency signal M250 and the 3rd frequency signal M500 of the first PLL device 11, and corresponding generation one flag signals flagM.Then, because the first sub-flag circuit 31 and the second sub-flag circuit 32 lay respectively in the first PLL device 11 and the second PLL device 12, the flag signals flagM that first sub-flag circuit 31 of flag circuit 30 produces needs first through several drawing lines (lane), such as, the flag signals flagM ' of the second sub-flag circuit 32 inputing to flag circuit 30 can just be become after 4 drawing lines (lane).Therefore, in second embodiment of the invention, increase newly/there is a phase difference and become above-mentioned flag signals flagM ' when flag signals flagM is passed to the second PLL device 12.
In second embodiment of the invention, second sub-flag circuit 32 of flag circuit 30 receives above-mentioned flag signals flagM ', first frequency signal T100 and the 4th frequency signal T500, and the corresponding reset signal reset that produces is to flip-flop 33, wherein second of the second PLL device 12 the sub-flag circuit 32 produces a sampled signal sampleT according to first frequency signal T100 and the 4th frequency signal T500, and use sampled signal sampleT to obtain reset signal reset to the above-mentioned flag signals flagM ' sampling with this phase difference, reset signal reset and this phase difference are had nothing to do.
In second embodiment of the invention, flip-flop 33 is connected to the second sub-flag circuit 32 of the second PLL device 12.The 4th frequency signal T500 that flip-flop 33 exports in order to the reset signal reset and the second PLL device 12 receiving the second sub-flag circuit 32 output.Flip-flop 33 produces the one five frequency signal T250 synchronous and identical with second frequency signal M250 according to reset signal reset with the 4th frequency signal T500.Finally, the negative edge that deserializer device 10 re-uses the 5th frequency signal T250 correctly receives the data transfer signal from ethernet PHY transceiver 14, to reach the first PLL device 11 and the asynchronous conversion of the second PLL device 12.
Fig. 4 A to Fig. 4 D is the frequency plot that each frequency signal in flag circuit 30 is described according to second embodiment of the invention.Fig. 4 A is the frequency plot that each frequency signal in the first sub-flag circuit 31 is described according to second embodiment of the invention.In Figure 4 A, first sub-flag circuit 31 produces a sampled signal sampleM through first frequency signal M100 and the 3rd frequency signal M500, wherein sampled signal sampleM performs a logical operation by by the 3rd frequency signal M500 to an active signal activeM " & " try to achieve, wherein the logical operation of active signal activeM is closed is be expressed as follows:
activeM＝！M100rstM500/3。
Then, the negative edge triggering second frequency signal M250 that the first sub-flag circuit 31 re-uses sampled signal sampleM obtains flag signals flagM, and wherein the logical operation of flag signals flagM is closed is be expressed as follows:
FlagM＝M250(negedgesampleM)。
Fig. 4 B is the frequency plot that each frequency signal in the second sub-flag circuit 32 is described according to second embodiment of the invention.In figure 4b, second sub-flag circuit 32 is according to reception above-mentioned flag signals flagM ', first frequency signal T100 and the 4th frequency signal T500, and the corresponding reset signal reset that produces is to flip-flop 33, wherein sampled signal sampleT performs a logical operation by by the 4th frequency signal T500 to an active signal activeT " & " try to achieve, wherein the logical operation relation of active signal activeM is expressed as follows:
activeT＝！T100rstT500/3。
Then, the second sub-flag circuit 32 uses sampled signal sampleT to obtain reset signal reset to the above-mentioned flag signals flagM ' sampling with this phase difference, and reset signal reset and this phase difference are had nothing to do.The logical operation relation of flag signals flagM is expressed as follows:
reset＝！(sampleT&flagM’)。
Fig. 4 C is the frequency plot of the input/output signal that flip-flop 33 is described according to second embodiment of the invention.In figure 4 c, flip-flop 33 produces the five frequency signal T250 synchronous and identical with second frequency signal M250 according to reset signal reset with the 4th frequency signal T500.
Fig. 4 D illustrates a time sequence allowance (timingmargin) of this phase difference in flag signals flagM ' shown in second embodiment of the invention with frequency plot.The flag signals flagM produced due to the first sub-flag circuit 31 needs first through several drawing lines (lane) (such as, 4 drawing lines (lane)) just can become the flag signals flagM ' inputing to the second sub-flag circuit 32 afterwards, the phase delay caused through drawing lines (lane) becomes this phase difference in flag signals flagM '.In addition, the shake (jitter) produced in deserializer device 10 or deflection (skew) also may produce this phase difference in flag signals flagM '.In fig. 4d, two flag signals flagM ' indicate a time sequence allowance (timingmargin) corresponding to this phase difference in flag signals flagM ', and wherein two flag signals flagM ' represent a maximum-delay phase place of this phase difference and a maximum leading phase place of this phase difference respectively.In second embodiment of the invention, the time span of this maximum-delay phase place is the half that the half of period 1 T1 (10 how second) deducts period 3 T3 (2 how second), and the time span of this maximum leading phase place is then the half of period 1 T1 (10 how second).Therefore, in second embodiment of the invention, the time span of time sequence allowance is the half that period 1 T1 (10 how second) deducts period 3 T3 (2 how second), that is 10-0.5*2=9 how second.
In other words, in second embodiment of the invention, as long as this phase difference is in the scope of above-mentioned time sequence allowance (9 how second) in flag signals flagM ', flip-flop 33 can correctly produce the five frequency signal T250 synchronous and identical with second frequency signal M250 according to reset signal reset and the 4th frequency signal T500.That is flag circuit 30 can tolerate that flag signals flagM ' has this phase difference in the above-mentioned time sequence allowance half of period 3 corresponding to the 3rd frequency signal M500 (period 1 that first frequency signal M100 is corresponding deduct) scope, flip-flop 33 is made can correctly to produce the five frequency signal T250 synchronous and identical with second frequency signal M250 according to reset signal reset with the 4th frequency signal T500.
Fig. 5 A to Fig. 5 D is the frequency plot that each frequency signal in flag circuit 30 is described according to of the present invention 1 the 3rd embodiment.Third embodiment of the invention and second embodiment of the invention use same deserializer device 10 and flag circuit 30 thereof, and its uniquely different time span be in the second round described in third embodiment of the invention and period 3 is different from second embodiment of the invention.
Therefore, in third embodiment of the invention, first PLL device 11 produces/exports a frequency signal CK150 of an a second round and frequency signal CK300 of a period 3 according to reference frequency signal REF100IN, and the second PLL device 12 produces/exports a frequency signal TPLCK150 of a second round and frequency signal TPLCK300 of period 3 to each drawing lines (lane) in deserializer device 10 according to reference frequency signal REF100IN, wherein aforementioned second and the time span of period 3 be respectively for 3.33 how how seconds (that is the frequency of frequency signal CK150 and frequency signal CK300 is respectively 150MHz and 300MHz) second and 6.66.
Fig. 5 A is the frequency plot that each frequency signal in the first sub-flag circuit 31 is described according to third embodiment of the invention.In fig. 5, first sub-flag circuit 31 produces a sampled signal sampleM through first frequency signal M100 and the 3rd frequency signal M300, wherein sampled signal sampleM performs a logical operation by by sampled signal sampleM to an active signal activeM " & " try to achieve, wherein the logical operation of active signal activeM is closed is be expressed as follows:
activeM＝！M100rstM300/3。
Then, the negative edge triggering second frequency signal M150 that the first sub-flag circuit 31 re-uses sampled signal sampleM obtains flag signals flagM, and wherein the logical operation relation of flag signals flagM is expressed as follows:
FlagM＝M150(negedgesampleM)。
Fig. 5 B is the frequency plot that each frequency signal in the second sub-flag circuit 32 is described according to third embodiment of the invention.In figure 5b, second sub-flag circuit 32 is according to reception above-mentioned flag signals flagM ', first frequency signal T100 and the 4th frequency signal T300, and the corresponding reset signal reset that produces is to flip-flop 33, wherein sampled signal sampleT performs a logical operation by by the 4th frequency signal T300 to an active signal activeT " & " try to achieve, wherein the logical operation relation of active signal activeM is expressed as follows:
activeT＝！T100rstT300/2。
Then, the second sub-flag circuit 32 uses sampled signal sampleT to obtain reset signal reset to the above-mentioned flag signals flagM ' sampling with this phase difference, and reset signal reset and this phase difference are had nothing to do.The logical operation relation of flag signals flagM is expressed as follows:
reset＝！(sampleT&flagM’)。
Fig. 5 C is the frequency plot of the input/output signal that flip-flop 33 is described according to third embodiment of the invention.In figure 5 c, flip-flop 33 produces the five frequency signal T150 synchronous and identical with second frequency signal M150 according to reset signal reset with the 4th frequency signal T300.
Fig. 5 D illustrates a time sequence allowance (timingmargin) of this phase difference in flag signals flagM ' shown in third embodiment of the invention with frequency plot.In figure 5d, two flag signals flagM ' indicate a time sequence allowance (timingmargin) corresponding to this phase difference in flag signals flagM ', and wherein two flag signals flagM ' represent a maximum-delay phase place of this phase difference and a maximum leading phase place of this phase difference respectively.In third embodiment of the invention, the time span of time sequence allowance is the half that period 1 T1 (10 how second) deducts period 3 T3 (3.33 how second), that is 10-0.5*3.33=8.33 how second.In other words, in second embodiment of the invention, as long as this phase difference is in the scope of above-mentioned time sequence allowance (9 how second) in flag signals flagM ', flip-flop 33 can correctly produce the five frequency signal T150 synchronous and identical with second frequency signal M150 according to reset signal reset and the 4th frequency signal T300.
In third embodiment of the invention, as long as this phase difference is in the scope of above-mentioned time sequence allowance (8.33 how second) in flag signals flagM ', flip-flop 33 can correctly produce the five frequency signal T150 synchronous and identical with second frequency signal M150 according to reset signal reset and the 4th frequency signal T500.That is flag circuit 30 can tolerate that flag signals flagM ' has this phase difference in the above-mentioned time sequence allowance half of period 3 corresponding to the 3rd frequency signal M300 (period 1 that first frequency signal M100 is corresponding deduct) scope, flip-flop 33 is made can correctly to produce the five frequency signal T150 synchronous and identical with second frequency signal M150 according to reset signal reset with the 4th frequency signal T300.
Fig. 6 is the process flow diagram realizing being applicable to an asynchronous conversion method of deserializer device 10 according to of the present invention 1 the 4th embodiment.In step s 601, a reference frequency signal REF100IN (that is first frequency signal M100, T100) of synchronized transmission one period 1 is to the first PLL device 11 and the second PLL device 12 of deserializer device 10.In step S602, produce through the first PLL device 11 and be less than a second frequency signal M250 of a second round of this period 1 and one the 3rd frequency signal M500 of a period 3, wherein this second round is the twice of this period 3.In step S603, a flag signals is exported through the first PLL device 11, wherein this flag signals produces from reference frequency signal REF100IN, the second frequency signal M250 of this first PLL device and the 3rd frequency signal M500, and had a phase difference when this flag signals is passed to the second PLL device 12.In step s 604, one the 4th frequency signal T500 of this period 3 is produced through the second PLL device 12.In step s 605, produce a sampled signal through the second PLL device 12, wherein this sampled signal produces from the reference frequency signal REF100IN of the second PLL device 12 and the 4th frequency signal T500.In step S606, use this sampled signal to obtain a reset signal to this flag signals sampling with this phase difference, this reset signal and this phase difference are had nothing to do.In step S607, the flip-flop through deserializer device 10 receives this reset signal and the 4th frequency signal T500, produces the one five frequency signal T250 synchronous and identical with second frequency signal M250 with correspondence.
Though the present invention discloses as above with preferred embodiment, this area is had and usually knows that the knowledgeable can more clearly understand content of the present invention.But, this area have usually know the knowledgeable it will be appreciated that they can easily with the present invention as basis, design or modification process and use deserializer device and asynchronous conversion method thereof to carry out identical object and/or reach the same advantage of embodiment presented here.Therefore protection scope of the present invention is when being as the criterion depending on the accompanying claim person of defining.
Claims (10)
1. can realize a deserializer device for asynchronous conversion, comprise:
First PLL device, in order to receive the first frequency signal of period 1, and corresponding generation is less than the second frequency signal of the second round of this period 1 and the 3rd frequency signal of period 3, wherein this second round is the twice of this period 3, and wherein this first PLL device exports flag signals according to this first frequency signal, this second frequency signal and the 3rd frequency signal;
Second PLL device, in order to synchronously to receive this first frequency signal, and corresponding the 4th frequency signal producing this period 3, there is phase difference when wherein this flag signals is passed to this second PLL device,
Wherein this second PLL device produces sampled signal according to this first frequency signal and the 4th frequency signal, and use this sampled signal to obtain reset signal to this flag signals sampling with this phase difference, this reset signal and this phase difference are had nothing to do; And
Flip-flop, is connected to this second PLL device, in order to receive this reset signal and the 4th frequency signal of the output of this second PLL device, and one the 5th frequency signal that corresponding generation is synchronous and identical with this second frequency signal.
2. the deserializer device as described in claim the 1st, wherein the time span of the time sequence allowance of this phase difference is the half this period 1 deducting this period 3.
3. the deserializer device as described in claim the 2nd, wherein when this flip-flop can produce five frequency signal synchronous and identical with this second frequency signal, the time span of the maximum-delay phase place of this phase difference is the half that the half of this period 1 deducts this period 3, and the time span of the maximum leading phase place of this phase difference is then the half of this period 1.
4. the deserializer device as described in claim the 1st, more comprises:
Flag circuit, can both be synchronized with this first frequency signal each other in order to make this second frequency signal and the 5th frequency signal.
5. the deserializer device as described in claim the 1st, more comprise when the 5th frequency signal that this flip-flop exports can be synchronized with this first frequency signal time, this second PLL device uses the negative edge of the 5th frequency signal to receive from the data transfer signal of ethernet PHY transceiver.
6., for an asynchronous conversion method for deserializer device, this asynchronous conversion method comprises:
The first frequency signal of synchronized transmission period 1 is to the first PLL device of this deserializer device and the second PLL device;
Produce through this first PLL device and be less than the second frequency signal of the second round of this period 1 and the 3rd frequency signal of period 3, wherein this second round is the twice of this period 3;
Flag signals is exported through this first PLL device, wherein this flag signals produces from this first frequency signal of this first PLL device, this second frequency signal and the 3rd frequency signal, and have phase difference when this flag signals is passed to this second PLL device;
The 4th frequency signal of this period 3 is produced through this second PLL device;
Produce sampled signal through this second PLL device, wherein this sampled signal produces from this first frequency signal of this second PLL device and the 4th frequency signal;
Use this sampled signal to obtain reset signal to this flag signals sampling with this phase difference, this reset signal and this phase difference are had nothing to do; And
A flip-flop through this deserializer device receives this reset signal and the 4th frequency signal, produces five frequency signal synchronous and identical with this second frequency signal with correspondence.
7. the asynchronous conversion method as described in claim the 6th, wherein the time span of the time sequence allowance of this phase difference is the half this period 1 deducting this period 3.
8. the asynchronous conversion method as described in claim the 7th, wherein when this flip-flop can produce five frequency signal synchronous and identical with this second frequency signal, the time span of the maximum-delay phase place of this phase difference is the half that the half of this period 1 deducts this period 3, and the time span of the maximum leading phase place of this phase difference is then the half of this period 1.
9. the asynchronous conversion method as described in claim the 6th, the flag circuit more comprised by this deserializer device makes this second frequency signal and the 5th frequency signal can both be synchronized with this first frequency signal each other.
10. the asynchronous conversion method as described in claim the 6th, the 5th frequency signal wherein exported when this flip-flop can be synchronized with this first frequency signal time, this second PLL device uses the negative edge of the 5th frequency signal to receive from the data transfer signal of ethernet PHY transceiver.
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