CN102065208A - Digital audio and video signal SerDes and realization method thereof - Google Patents
Digital audio and video signal SerDes and realization method thereof Download PDFInfo
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Abstract
The invention provides a digital audio and video signal SerDes and a realization method thereof, which belong to the technical field of panel display and can be applied to serial interface circuits of microdisplays of an LCD (Liquid Crystal Display), an LCoS (Liquid Crystal on Silicon), an AMOLED (Active Matrix/Organic Light Emitting Diode), and the like. A serial encoding circuit of the SerDes provided by the invention comprises eight unit circuits of an image preprocessing circuit, an adjacent pixel comparer, a similarity encoding circuit, a diversity encoding circuit, a scrambling and encoding circuit, a multiplexer 1, a control clock circuit, a syncgenerator, and the like. Based on the similarity of adjacent pixels of a video image, the invention provides an improved scrambling mechanism and in particular relates to a serial transmission technology with respect to a digital video signal, which has the characteristics of simple structure and lower extra system overhead; and meanwhile, the digital audio and video signal SerDes has the function of simultaneously transmitting audio signals.
Description
[technical field]:
The invention belongs to technical field of flat panel display, relate to a kind of digital video signal serial deserializer.
[background technology]:
Development along with flat panel display, various high-resolution digital image display devices and mobile media display device become the main flow in market, as display screen of one of display system key element and the interfacing between the audio video processor, has very big development in recent years, traditional analog video interface such as CVBS, VGA interface etc., can not adapt to the requirement of various high definition display systems and movable display system, just progressively replaced by various Digital Video Interface Technology.The contemporary information display industry of new digital video interface technology such as the HD-SDI that develops rapidly, DVI, HDMI, DiiVA, DisplayPort play an important role, has vast market prospect, in order to satisfy the displaying contents of large information capacity, improve the transmission rate of display interface device circuit, these new Digital interfacings all adopted high speed data interface (Serial Data Interface, SDI).Because audio video processor and display device all are parallel data interfaces, therefore the serial deserializer of two-forty, high efficiency digital audio-video signal is the key technology that realizes the high-speed serial data transmission, switch in order to realize dc balance and to satisfy the needed state of clock recovery, in the middle of prior art, the technology that the high speed serialization deserializer is adopted has two kinds, i.e. 8B/10B coding techniques and scrambler coding techniques.Wherein the 8B/10B coding techniques is the American I BM company patent of nineteen eighty-three, it also is most widely used coding techniques, the major defect of this technology is exactly the extra overhead that increases up to 25%, people have proposed the method for concentrated reduction 8B/10B overhead such as 64B66B etc. in recent years, but be cost all, exchange lower overhead for to improve hardware design complexity; Scrambler is that a kind of method that pseudo random sequence is mixed with source code flow realizes purposes such as conversion, dc balance, and scrambler does not need extra bandwidth.DVI, HDMI adopted the 8b/10b coding techniques, and HD-SDI have adopted the scrambler technology based on transition minimized differential signaling (TMDS) channel.
[summary of the invention]: the purpose of this invention is to provide a kind of serial deserializer and its implementation that is used for digital audio/video high speed serial transmission interface,, realize the serial transmission of the wired and wireless audio and video signal of high efficiency, two-forty in order to simplify circuit structure.
Digital audio-video signal serial deserializer provided by the invention comprises serial code reconciliation circuit string decoding circuit; The serial code circuit application is in data sending terminal, and the decoding circuit that unstrings is applied to data receiver; Link to each other by optical fiber, radio wave external transmission medium between the serial code reconciliation circuit string decoding circuit;
Described serial code circuit comprises as shown in Figure 8:
Image is anticipated circuit: the input that image is anticipated circuit 1 has the digital video signal bus of each N position of RGB, links to each other with the external video treatment circuit; Signal input end CON, CK and OE link to each other with control clock circuit 7; Its output links to each other with neighbor comparator 2;
The neighbor comparator: the input of neighbor comparator 2 has two, and the one, the output that the digital video signal bus and the image of 2N position anticipated circuit 1 links to each other, and the 2nd, signal input end S0 links to each other with control clock circuit 7; Its output signal has three groups, links to each other with similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6 respectively;
The similitude coding circuit; The input of similitude coding circuit 3 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1;
The scrambler coding circuit: the input of scrambler coding circuit 5 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1;
The diversity coding circuit; The input of diversity coding circuit 6 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1;
MUX: the input of MUX 1 links to each other with similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6, synchronizing generator 8 and neighbor comparator 2, and output links to each other with the serial data receiving terminal of outside;
Clock control circuit: the input of clock control circuit 7 links to each other with external video clock signal, frame synchronizing signal and line synchronizing signal; Output is anticipated circuit 1, neighbor comparator 2, similitude coding circuit 3, diversity coding circuit 5, scrambler coding circuit 6 and synchronizing generator 8 with image and is linked to each other;
Synchronizing generator: the input of synchronizing generator 8 and outside parallel audio data/address bus, row are synchronously, frame synchronization links to each other with the effective control signal of audio signal; Its output links to each other with MUX 1 with control clock circuit 7;
The described decoding circuit that unstrings comprises: clock data recovery circuit 37, serial data and conversion and clock down conversion circuit 38, identity code identification and data multiplex control circuit 39, similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, synchronous and audio signal restore circuit 43 and local clock 44, and the interconnected relationship of foregoing circuit is as shown in Figure 9; The input of clock data recovery circuit 37 links to each other with the outside; The reference clock input links to each other with local clock 44; The synchronised clock that recovers to come out links to each other with clock down conversion circuit 38 with serial data and conversion with the serial data output; Identity code identification and data multiplex control circuit 39 are made up of 2N+2 bit data latch 7 46, synchronous mark sign indicating number identification circuit 47 and Data Labels sign indicating number identification circuit 48; Its parallel data input links to each other with clock down conversion circuit 38 with serial data and conversion with work clock Clock input; Work clock Clock output with similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, with audio signal restore circuit 43 respectively link to each other synchronously, and link to each other with the outside as the parallel video clock output signal.
The image of described serial code circuit is anticipated circuit 1 inside and is made up of tristimulus image data timesharing output control circuit 9, data latches 1 and data latches 2 11; Tristimulus image data timesharing output control circuit 9 odd number pixel data in proper order with the RGB image of timesharing under the control of CON signal and clock signal C K is delivered to data latches 1, and the pixel data of even number order is delivered to data latches 2 11, when output enable signal OE is effective, simultaneously two pixel datas are outputed to neighbor comparator 2 then.
Described serial code circuit neighbor comparator 2, inner by with or circuit 12, similitude flag register 13, coding circuit 14 and MUX 2 15 form; 2 pairs of images of neighbor comparator are anticipated the not overlapping neighbor of circuit 1 output, carry out the same exclusive disjunction of step-by-step, and operation result is placed in the N position similitude flag register 13; Numerical value in 14 pairs of similitude flag registers 13 of coding circuit is encoded, when N-1 1 being arranged or when above in this N bit data, 14 output of coding circuit S1S2S3=100, when N-1 0 being arranged or when above in this N bit data, 14 output of coding circuit S1S2S3=010, under other situations, coding circuit 14 output S1S2S3=001; MUX 2 15 is delivered to similitude coding circuit 3, diversity coding circuit 6 and scrambler coding circuit 5 respectively with two not overlapping neighbors under the control of signal S1S2S3, simultaneously the S1S2S3 signal is respectively as the enable signal of similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6.
Described serial code circuit similitude coding circuit 3 by data latches 3 16, data latches 4 20, step-by-step negate circuit 19, insert circuit 17 and sign every the position and insert circuit 18 and form; When the S1=1 of neighbor comparator 2 output, data on data latches 3 16 and the data latches 4 20 image data lines, wherein the data in the data latches 4 20 are after step-by-step negate circuit 19 is handled, inserting the 1st pixel mixing of circuit 17 neutralizations every the position, form new 2N bit data, regulation is the data of the 1st pixel from high position 2n+1 position, and the 2n position is the data of the 2nd pixel, and n is less than 8; Sign is inserted circuit 18 and is inserted 10 in 2N bit data front, and data are become the output of 2N+2 Bits Serial sign indicating number.
Described serial code circuit diversity coding circuit 6 by data latches 5 21, data latches 6 24, insert circuit 22 and sign every the position and insert circuit 23 and form; When the S2=1 of neighbor comparator 2 output, data on data latches 5 21 and the data latches 6 24 image data lines, inserting every the position in the circuit 22 the 1st pixel and the 2nd pixel mixing, form new 2N bit data, regulation is the data of the 1st pixel from high position 2n+1 position, and the 2n position is the data (n is less than 8) of the 2nd pixel; Sign is inserted circuit 23 and is inserted 01 in 2N bit data front, and data are become the output of 2N+2 Bits Serial sign indicating number.
Described serial code circuit synchronizing generator 8 can between frame synchronization and row sync period, handle and the transmission of digital audio signal, when the H signal of synchronizing generator 8 output and V signal are effective, control clock circuit 7 will be exported the S0 signal, make S1S2S3=000, stop 2 work of neighbor comparator, while similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6 quit work, MUX 1 is under the control of S4 signal, with synchronous mark sign indicating number and the audio output signal and the serial data output connection of synchronizing generator 8 generations, thus output frame synchronous mark sign indicating number, row synchronous mark sign indicating number and serial audio signal.
The identity code identification and the data multiplex control circuit 39 of the described decoding circuit that unstrings are made up of 2N+2 bit data latch 7 46, synchronous mark sign indicating number identification circuit 47 and Data Labels sign indicating number identification circuit 48; Input clock Clock drives 2N+2 bit data latch 7 46 and latchs current data.
The described decoding circuit that unstrings similar solution decoding circuit 40, when control signal E1 is effective, adopted the data handling procedure of similitude coding circuit 3 contraries; Diversity decoding circuit 42 has adopted the data handling procedure of diversity coding circuit 6 contraries when control signal E3 is effective; Synchronously and audio signal restore circuit 44, when control signal E4 is effective, adopted the data handling procedure of synchronizing generator 8 contraries.
The implementation method of above-mentioned digital audio-video signal serial deserializer, pass through following step successively:
The first, when effective frame synchronization, row synchronously and after vision signal occurs, synchronizing generator 8 will be by the synchronous mark sign indicating number of MUX one 4 transmit frames and row, after having only effective capable synchronous mark sign indicating number to finish, control clock circuit 7 just can be exported S0, CON, CK and OE signal effectively, starts image and anticipates circuit 1 and 2 work of neighbor comparator circuit;
The second, the grouping of neighbor: under the control of input clock, image is anticipated circuit 1 each N bit data timesharing output of RGB with the outside input, and the N bit data of first pixel is temporarily stored in data latches 1, the N bit data of the 2nd pixel is temporarily stored in data latches 2 11, and the data parallel with these two neighbors outputs to neighbor comparator 2 again.Image is anticipated circuit 1 video data of temporary the 3rd pixel more then, forms second group of neighbor with the 4th pixel data, by that analogy;
Three, judge the similitude of every group of neighbor: the data for each group neighbor are carried out same exclusive disjunction, divide three kinds of situations to classify: when the value of the neighbor data of two N positions equates, then the result behind the two data inclusive ORs is complete 1, this situation appears at the zone of video image background or solid color, and our preset threshold is to have two neighbors of N-1 and N 1 expression similar; When the value of the neighbor data of two N positions was opposite, then the result behind the two data inclusive ORs was complete 0, and this situation appears at the borderline region of video image, and our preset threshold is that N-1 and two adjacent datas of N 0 expression are different;
Four, for two neighbors, carry out the similitude encoding process,, and insert every the position, form serial data stream output with the one other pixel step-by-step with one of them pixel step-by-step negate with similitude;
Five, for two neighbors, carry out the diversity encoding process, one of them pixel and one other pixel step-by-step are inserted every the position, form serial data stream output with diversity;
Six, in other cases, two neighbors are formed the 2N bit data, by the scrambler algorithm, form serial data stream output;
Seven, for the serial data stream of similitude encoding process in front titled with " 10 ", form the 2N+2 bit data stream; In front titled with " 01 ", form the 2N+2 bit data stream for the serial data stream of diversity encoding process; Titled with " 11 ", form the 2N+2 bit data stream for the data of scrambler encoding process;
Eight, between frame synchronization and row sync period, synchronizing generator 8 produces the synchronous mark code of frame and row, through MUX one 4 outputs; Row synchronous mark code is divided into two sections, and between two sections codes, voice data is handled and sent to synchronizing generator 8;
Nine, pass through optical fiber or radio wave transmit frame synchronous mark sign indicating number, capable synchronous mark sign indicating number, serial voice data and serial video data through MUX one 4 timesharing at last.
Ten, unstring decoding circuit from the serial data that receives by optical fiber or radio wave clock data recovery circuit 37, recover the data and the identity code of synchronised clock and 2N+2 position;
The 11, by serial data and conversion and clock down conversion circuit 38, conversion produces the parallel data of work clock Clock and 2N+2 position;
The 12, analyze by identity code identification and 39 pairs of parallel 2N+2 bit data of data multiplex control circuit, extract digital coding identity code and synchronous mark sign indicating number, produce E1, E2, E3, E4 control signal;
The 13, under the control of E1, E2, E3, E4 signal, data are carried out similitude decoding, scrambler decoding, diversity decoding, synchronizing signal decoding and audio signal decoding respectively;
The 14, the video data that obtains of decoding outputs to the external display circuit system under the control of clock signal, frame synchronizing signal and line synchronizing signal; Audio signal, clock signal, frame synchronizing signal and line synchronizing signal directly output to the external display circuit system.
The present invention adopts integral design method, serial code reconciliation circuit string decoding circuit is designed to an integrated circuit respectively, as the transmitter and the receiver of transfer of data.Circuit adopts the hardware description language design, and based semiconductor technology realizes.
Advantage of the present invention and good effect:
Serial deserializer provided by the invention has adopted follow-on scrambler algorithm, can adopt the coding method of simplifying when neighbor has similitude or diversity according to the similarity principle of video image neighbor, and other situations adopt the scrambler coding.For background parts, the still image monochromatic areas of view data, adopt similitude or diversity coding, the expense that can save serial deserializer hardware and software, the efficient of raising circuit, the power consumption of reduction circuit, the dc balance characteristic is good.The present invention simultaneously can realize the transmission of Voice ﹠ Video data simultaneously, is specially adapted to Helmet Mounted Display etc.
[description of drawings]:
Fig. 1 is that image is anticipated circuit 1 structured flowchart;
Fig. 2 is neighbor comparator 2 structured flowcharts;
Fig. 3 is similitude coding circuit 3 structured flowcharts;
Fig. 4 is diversity coding circuit 6 structured flowcharts;
Fig. 5 is synchronizing generator circuit 8 structured flowcharts;
Fig. 6 is clock control circuit 7 structured flowcharts;
Fig. 7 is identity code identification and data multiplex control circuit 39 structured flowcharts;
Fig. 8 is a serial code circuit structure block diagram;
Fig. 9 is the decoding circuit structured flowchart that unstrings.
[embodiment]:
Embodiment 1:
As shown in Figure 8, the serial code circuit of this digital audio-video signal serial deserializer is anticipated circuit 1, neighbor comparator 2, similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6, MUX 1, clock control circuit 7 and synchronizing generator 8 by image and is formed, and all element circuits integrate.Wherein:
The input that image is anticipated circuit 1 has the digital video signal bus of each N position of RGB, links to each other with the external video treatment circuit, and control signal CON, CK and OE input link to each other with control clock circuit 7; Its output links to each other with neighbor comparator 2, and the output of data presses 0,1,2,3,4,5 ... one group of nonoverlapping neighbor data of the each output of order to neighbor comparator 2; The input data-interface is each N position of RGB, and the dateout interface is the 2N position, and according to the standard difference of input signal, N can be 6 or 8, respectively corresponding RGB565 and RGB888 standard.Image is anticipated circuit 1 inside and is made up of tristimulus image data timesharing output control circuit 9 and data latches 1, data latches 2 11; Tristimulus image data timesharing output control circuit 9 is under the control of CON and CK signal, the odd number pixel data in proper order with the RGB data of timesharing is delivered to data latches 1, and the pixel data of even number order is delivered to data latches 2 11, under enable signal OE control, simultaneously two pixels are outputed to neighbor comparator 2 then.
The input of neighbor comparator 2 has two, and the one, the digital video signal of 2N position links to each other with the output that image is anticipated circuit 1, and the 2nd, control signal S0 input links to each other with control clock circuit 7; Its output has three groups, links to each other with similitude coding circuit 3, scrambler coding circuit 5 and diversity coding circuit 6 respectively.Whether neighbor comparator 2 is the same by two N bit data of bit comparison, provide each whether identical sign of two data, be all 1 mutually, be not all 0, and classify according to the data that this sign is anticipated circuit 1 output to image, when flag data has N-1 1 above, then two neighbor data of this group are delivered to similitude coding circuit 3 and handle; When flag data has N-1 0 above, then two neighbor data of this group are delivered to diversity coding circuit 6 and handle; Otherwise these group neighbor data are delivered to scrambler coding circuit 5 to be handled.Simultaneously neighbor comparator 2 output control signal S1S2S3 are used to start the respective coding circuit working, and as the gating control signal of back MUX 1.Neighbor comparator 2 inside are made up of same or circuit 12, similitude flag register 13, coding circuit 14 and MUX 2 15; Numerical value in 14 pairs of similitude flag registers 13 of coding circuit is encoded, when this N bit data has N-1 1 or when above, 14 output of coding circuit S1S2S3=100, when this N bit data has N-1 0 or when above, 14 output of coding circuit S1S2S3=001, under other situations, coding circuit output S1S2S3=010;
The input of similitude coding circuit 3 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1.The sign that provides when neighbor comparator 2 is when N-1 1 is above, S1S2S3=100, the data of two neighbors of this group are delivered to similitude coding circuit 3, after the similitude encoding process, data conversion is become the serial data of a kind of 2N+2 position, through MUX one 4 outputs.Similitude coding circuit 3 by data latches 3 16, data latches 4 20, step-by-step negate circuit 19, insert circuit 17 and sign every the position and insert circuit 18 and form; When the S1=1 of neighbor comparator 2 output, data on data latches 3 16 and the data latches 4 20 image data lines, the data of the 2nd pixel are after step-by-step negate circuit 19 is handled, inserting the 1st pixel mixing of circuit 17 neutralizations every the position, form new 2N bit data, regulation is the data of the 1st pixel from high position 2n+1 position, and the 2n position is the data (n is less than 8) of the 2nd pixel; Sign is inserted circuit and is inserted 10 in 2N bit data front, and data are become the output of 2N+2 Bits Serial sign indicating number.
The input of scrambler coding circuit 5 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1.The flag data that provides when neighbor comparator 2 is 1～(N-2) individual 1 or 1～(N-2) individual 0 the time, S1S2S3=010, the data of two neighbors of this group are handled by scrambler coding circuit 5, when the S3=1 of neighbor comparator 2 output, scrambler coding circuit 5 becomes the serial data of a kind of 2N+2 position with data conversion, through MUX one 4 outputs.
The input of diversity coding circuit 6 links to each other with the output of neighbor comparator 2, and its output links to each other with MUX 1.The sign that provides when neighbor comparator 2 is when N-1 0 is above, S1S2S3=001, the data of two neighbors of this group are delivered to diversity coding circuit 6, after the diversity encoding process, data conversion is become the serial data of a kind of 2N+2 position, through MUX one 4 outputs.Diversity coding circuit 6 by data latches 5 21, data latches 6 24, insert circuit 22 and sign every the position and insert circuit 23 and form; When the S2=1 of neighbor comparator 2 output, data on data latches 5 21 and the data latches 6 24 image data lines, inserting every the position in the circuit 22 the 1st pixel and the 2nd pixel mixing, form new 2N bit data, regulation is the data of the 1st pixel from high position 2n+1 position, and the 2n position is the data (n is less than 8) of the 2nd pixel; Sign is inserted circuit 23 and is inserted 01 in 2N bit data front, and data are become the output of 2N+2 Bits Serial sign indicating number.
The data input pin of MUX 1 links to each other with similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6, synchronizing generator 8, and output links to each other with the serial interface receiving end of outside.MUX 1 is according to the numerical value of control signal S1S2S3S4, and the code stream similitude coding circuit 3, scrambler coding circuit 5, diversity coding circuit 6 and synchronizing generator 8 outputs of timesharing is sent to external circuit.MUX 1 can be under the control of the control signal S1S2S3 that neighbor comparator 2 is exported, the serial data bit stream of the selection similitude coding circuit 3 of timesharing, scrambler coding circuit 5 and 6 outputs of diversity coding circuit; When S1S2S3=100, the 2N+2 Bits Serial sign indicating number of similitude coding circuit 3 outputs is with sign " 10 " beginning, when S1S2S3=001. the 2N+2 Bits Serial sign indicating number of scrambler coding circuit 5 outputs is with sign " 11 " beginning, and when S1S2S3=010, the 2N+2 Bits Serial sign indicating number of diversity coding circuit 6 outputs is with sign " 01 " beginning.
Synchronizing generator 8 has 5 inputs, effectively links to each other with the high-frequency clock CLK of clock control circuit 7 outputs with frame synchronizing signal, line synchronizing signal, parallel audio input signal, the audio signal of external circuit respectively.Its output signal has 4, frame synchronization V signal, the synchronous H signal of row link to each other with clock control circuit 7, be used for controlling the synchronous of clock circuit and vision signal, another control signal S4 links to each other with MUX 1 with the identity code output, and the timesharing of control Port Multiplier receives synchronous mark sign indicating number and audio signal.
Embodiment 2:
The realization of the serial code circuit of this serial digital audio frequency and video serial deserializer is successively through step what follows:
The first, when effective frame synchronization, row synchronously and after vision signal occurs, synchronizing generator 8 will be by the synchronous mark sign indicating number of MUX one 4 transmit frames and row, after having only effective capable synchronous mark sign indicating number to finish, control clock circuit 7 just can be exported S0, CON, CK and OE signal effectively, starts image and anticipates circuit 1 and 2 work of neighbor comparator circuit;
The second, the grouping of neighbor: under the control of input clock, image is anticipated circuit 1 each N bit data timesharing output of RGB with the outside input, and the N bit data of first pixel is temporarily stored in data latches 1, the N bit data of the 2nd pixel is temporarily stored in data latches 2 11, and the data parallel with these two neighbors outputs to neighbor comparator 2 again.Image is anticipated circuit 1 video data of temporary the 3rd pixel more then, forms second group of neighbor with the 4th pixel data, by that analogy;
Three, judge the similitude of every group of neighbor: the data for each group neighbor are carried out same exclusive disjunction, divide three kinds of situations to classify: when the value of the neighbor data of two N positions equates, result behind the two data inclusive ORs is complete 1, this situation appears at the zone of video image background or solid color, and our preset threshold is to have two neighbors of N-1 and N 1 expression similar; When the value of the neighbor data of two N positions was opposite, the result behind the two data inclusive ORs was complete 0, and this situation appears at the borderline region of video image, and our preset threshold is that N-1 and two adjacent datas of N 0 expression are different;
Four, for two neighbors, carry out the similitude encoding process,, and insert every the position, form serial data stream output with the one other pixel step-by-step with one of them pixel step-by-step negate with similitude;
Five, for two neighbors, carry out the diversity encoding process, one of them pixel and one other pixel step-by-step are inserted every the position, form serial data stream output with diversity;
Six, in other cases, two neighbors are formed the 2N bit data, by the scrambler algorithm, form serial data stream output;
Seven, for the serial data stream of similitude encoding process in front titled with " 10 ", form the 2N+2 bit data stream; In front titled with " 01 ", form the 2N+2 bit data stream for the serial data stream of diversity encoding process; Titled with " 11 ", form the 2N+2 bit data stream for the data of scrambler encoding process;
Eight, between frame synchronization and row sync period, synchronizing generator 8 produces the synchronous mark code of frame and row, through MUX one 4 outputs; Row synchronous mark code is divided into two sections, and between two sections codes, voice data is handled and sent to synchronizing generator 8;
Nine, pass through optical fiber or radio wave transmit frame synchronous mark sign indicating number, capable synchronous mark sign indicating number, serial voice data and serial video data through MUX one 4 timesharing at last.
Ten, unstring decoding circuit from the serial data that receives by optical fiber or radio wave clock data recovery circuit 37, recover the data and the identity code of synchronised clock and 2N+2 position;
The 11, by serial data and conversion and clock down conversion circuit 38, conversion produces the parallel data of work clock Clock and 2N+2 position;
The 12, analyze by identity code identification and 39 pairs of parallel 2N+2 bit data of data multiplex control circuit, extract digital coding identity code and synchronous mark sign indicating number, produce E1, E2, E3, E4 control signal;
The 13, under the control of E1, E2, E3, E4 signal, data are carried out similitude decoding, scrambler decoding, diversity decoding, synchronizing signal decoding and audio signal decoding respectively;
The 14, the video data that obtains of decoding outputs to the external display circuit system under the control of clock signal, frame synchronizing signal and line synchronizing signal; Audio signal, clock signal, frame synchronizing signal and line synchronizing signal directly output to the external display circuit system.
Embodiment 3:
The realization of the serial code of this digital audio frequency and video serial deserializer, get N=8, corresponding RGB888 video standard is as embodiment 1, when signal CON is effective, image is anticipated circuit 1 under the control of CK clock signal, time-division processing RGB view data, to each primary color image, the video data of 2 neighbors of continuous acquisition, and when the OE signal is effective, the neighbor comparator 2 of the back that parallel 16 bit data with 2 neighbors are exported.
After neighbor comparator 2 receives two neighbor video datas, to two 8 data by carrying out same exclusive disjunction with exclusive disjunction circuit 12, and the result of computing is latched in the similitude flag register 13, the numerical value of 14 pairs of similitude flag registers of coding circuit is encoded, and output control signal S1S2S3, when S0=1, S1S2S3=000; When S0=0, if similitude flag register 13 in have 7 or 81 then S1S2S3=100, if content of registers has 7 or 80, S1S2S3=001 then, S1S2S3=010 under other situations.If S1S2S3=000, MUX 2 15 is closed the data output channel; If S1S2S3=100, data output to the similitude coding circuit through MUX 2 15; If S1S2S3=001, data output to the diversity coding circuit through MUX 2 15; If S1S2S3=010, data output to the scrambler coding circuit through MUX 2 15.
In addition when S2=1, start scrambler coding circuit 5, the data of two neighbors to input do not carry out inserting every the position, but by the data of the 1st pixel the data of preceding (most-significant byte) the 2nd pixel after order, carry out 16 scrambler computings, fixing insertion 11 backs form one group 18 serial data output in 16 scrambler data fronts that generate at last.
Embodiment 4:
The synchronizing generator 8 of this digital audio frequency and video serial deserializer and the workflow of clock control circuit 7 are as follows:
The structure of synchronizing generator 8 is as described in the embodiment 1, the implementation process of synchronizing generator 8 is as follows: the first step, externally frame synchronizing signal is effectively when (high level), Port Multiplier 30 is delivered to synchronous mark sign indicating number and audio output with 18 fractional frequency signals of CLK, output frame synchronous mark sign indicating number, this identity code will continue between the high period of frame-synchronizing impulse; Second step; Externally effectively when (high level), parallel-to-serial converter 27 latchs the voice data of input to line synchronizing signal, and delivers to scrambler coding circuit 29 and handle; The 3rd step, externally line synchronizing signal is effectively when (high level) and external frame synchronizing signal invalid (low level), timer 28 regularly begins, in 512 clk cycles, timer 28 output signal T are low level, this moment, Port Multiplier 30 was delivered to synchronous mark sign indicating number and audio output with 9 fractional frequency signals of CLK, the leading portion of output row synchronous mark sign indicating number; The 4th step, externally line synchronizing signal is effectively when (high level) and external frame synchronizing signal invalid (low level), timer 28 through 512 clk cycles after output signal T be high level, this moment is at signal T=1, H=1, when V=0 satisfied, Port Multiplier 30 was exported 2 times 18 Bits Serial voice datas continuously with output and the synchronous mark sign indicating number and the audio output connection of scrambler coding circuit 29; The 5th step, externally line synchronizing signal is effectively when (high level) and frame synchronizing signal invalid (low level), timer 28 is a low level through 476 clk cycles timing back output signal T, Port Multiplier 30 send synchronous mark sign indicating number and audio output with 9 fractional frequency signals of CLK, the back segment of output row synchronous mark sign indicating number, and last till that always horizontal synchronizing pulse H occurs till the low level; In the 6th step, during synchronous and capable synchronized void (low level), synchronizing generator 8 is in wait state, and exports S0=0 when external frame.
The circuit structure of clock control circuit 7 is as described in the embodiment 1, the implementation process of clock control circuit 7 is as follows: at frame synchronizing signal V or line synchronizing signal H is between high period, by or the signals of door 32 outputs make control circuit 34 output S0=1, suspend neighbor comparator 2, show that be between sync period this moment; At frame synchronizing signal V and line synchronizing signal H all is between low period, or the signals of door 32 outputs make control circuit 34 output S0=0, starts neighbor comparator 2, and control circuit 34 output CON signals, CK signal and OE signal are effective simultaneously; The video clock input signal makes phase-locked loop 35 work together as reference clock and local clock 33, and output master clock CLK; At frame synchronizing signal V and line synchronizing signal H all is between low period, and control circuit 34 detects less than the video clock input signal, and then showing does not have the signal input, and 34 closing high-speed clock driver circuits 36 of control circuit are to reduce power consumption.
Embodiment 5:
As shown in Figure 9, this digital audio-video signal serial deserializer unstring decoding circuit by clock data recovery circuit 37, serial data and conversion and clock down conversion circuit 38, identity code identification and data multiplex control circuit 39, similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, synchronously and audio signal restore circuit 43 and local clock 44 form.
Externally Shu Ru vision signal is under the RGB888 form situation, clock data recovery circuit 37 from continuous serial data bit stream, recover the to come out serial code stream of 18 words, output to serial data and conversion and clock down conversion circuit 38, switching state according to serial code stream recovers out the high-speed synchronous clock simultaneously, outputs to serial data and conversion and the clock of clock down conversion circuit 38 as serial data and conversion.
Serial data and conversion and clock down conversion circuit 38 under the synchronised clock control that clock data recovery circuit 37 recovers, become 18 Bits Serial code conversions 18 parallel sign indicating number to output to identity code identification and data multiplex control circuit 39; And synchronised clock is carried out 18 frequency divisions handle, form the needed work clock of parallel data, the reference clock that fetches data as subsequent decoding circuit and external read.
Identity code identification is made up of 18 bit data latchs 7 46, synchronous mark sign indicating number identification circuit 47 and Data Labels sign indicating number identification circuit 48 with data multiplex control circuit 39; Synchronous mark sign indicating number identification circuit 47 reads 18 data, judge whether 18 bit data are complete 0 or complete 1, when not having complete 0 or complete 1 to occur, then there is not the synchronous mark sign indicating number, thereby output signal E4=0, when per 18 0 18 1 data flow occurs then, then be judged as frame synchronizing signal and output signal E4=1 occurs; When per 9091 data flow occurs then, then being judged as line synchronizing signal occurs, synchronous mark sign indicating number identification circuit 47 timer internal startup work this moment, catch the back segment of leading portion, voice data and the row synchronous mark sign indicating number of row synchronous mark sign indicating number, and output signal E4=1, and, select the output of audio signal by output signal T; Data Labels sign indicating number identification circuit 48 reads the highest 2 of 18 bit data, when high 2 bit data are 10, output signal E1=1 then, send similar solution decoding circuit 40 to decode 18 bit data, when high 2 bit data are 11, output signal E2=1 then, send scrambler decoding circuit 41 to decode 18 bit data, when high 2 bit data were 01, then output signal E3=1 sent diversity decoding circuit 42 to decode 18 bit data.
Synchronously and the parallel video data exported of the signal (frame synchronizing signal Vs, line synchronizing signal Hs and voice data) of audio signal restore circuit 43 outputs and similar solution decoding circuit 40, scrambler decoding circuit 41, diversity decoding circuit 42, and the reference clock Clock that works outputs to external circuit together.
Claims (9)
1. a digital audio-video signal serial deserializer is characterized in that this serial deserializer comprises serial code reconciliation circuit string decoding circuit; Link to each other by optical fiber, radio wave external transmission medium between the serial code reconciliation circuit string decoding circuit;
Described serial code circuit comprises:
Image is anticipated circuit: the input that image is anticipated circuit (1) has the digital video signal bus of each N position of RGB, links to each other with the external video treatment circuit; Signal input end CON, CK and OE link to each other with control clock circuit (7); Its output links to each other with neighbor comparator (2);
The neighbor comparator: the input of neighbor comparator (2) has two, and the one, the output that the digital video signal bus and the image of 2N position anticipated circuit (1) links to each other, and the 2nd, signal input end S0 links to each other with control clock circuit (7); Its output signal has three groups, links to each other with similitude coding circuit (3), scrambler coding circuit (5) and diversity coding circuit (6) respectively;
The similitude coding circuit; The input of similitude coding circuit (3) links to each other with the output of neighbor comparator (2), and its output links to each other with MUX one (4);
The scrambler coding circuit: the input of scrambler coding circuit (5) links to each other with the output of neighbor comparator (2), and its output links to each other with MUX one (4);
The diversity coding circuit; The input of diversity coding circuit (6) links to each other with the output of neighbor comparator (2), and its output links to each other with MUX one (4);
MUX: the input of MUX one (4) links to each other with similitude coding circuit (3), scrambler coding circuit (5), diversity coding circuit (6), synchronizing generator (8) and neighbor comparator (2), and output links to each other with the serial data receiving terminal of outside;
Clock control circuit: the input of clock control circuit (7) links to each other with external video clock signal, frame synchronizing signal and line synchronizing signal; Output is anticipated circuit (1), neighbor comparator (2), similitude coding circuit (3), diversity coding circuit (5), scrambler coding circuit (6) and synchronizing generator (8) with image and is linked to each other;
Synchronizing generator: the input of synchronizing generator (8) and outside parallel audio data/address bus, row are synchronously, frame synchronization links to each other with the effective control signal of audio signal; Its output links to each other with MUX one (4) with control clock circuit (7);
The described decoding circuit that unstrings comprises: clock data recovery circuit (37), serial data and conversion and clock down conversion circuit (38), identity code identification and data multiplex control circuit (39), similar solution decoding circuit (40), scrambler decoding circuit (41), diversity decoding circuit (42), synchronous and audio signal restore circuit (43) and local clock (44); The input of clock data recovery circuit (37) links to each other with the outside; The reference clock input links to each other with local clock (44); The synchronised clock that recovers to come out links to each other with clock down conversion circuit (38) with serial data and conversion with the serial data output; Identity code identification and data multiplex control circuit (39) are made up of 2N+2 bit data latch seven (46), synchronous mark sign indicating number identification circuit (47) and Data Labels sign indicating number identification circuit (48); Its parallel data input links to each other with clock down conversion circuit (38) with serial data and conversion with work clock Clock input; Work clock Clock output with similar solution decoding circuit (40), scrambler decoding circuit (41), diversity decoding circuit (42), with audio signal restore circuit (43) respectively link to each other synchronously, and link to each other with the outside as the parallel video clock output signal.
2. digital audio-video signal serial deserializer according to claim 1, it is characterized in that the image of described serial code circuit is anticipated circuit (1) inside and is made up of tristimulus image data timesharing output control circuit (9), data latches one (10) and data latches two (11); Tristimulus image data timesharing output control circuit (9) odd number pixel data in proper order with the RGB image of timesharing under the control of CON signal and clock signal C K is delivered to data latches one (10), and the pixel data of even number order is delivered to data latches two (11), when output enable signal OE is effective, simultaneously two pixel datas are outputed to neighbor comparator (2) then.
3. digital audio-video signal serial deserializer according to claim 1, it is characterized in that, described serial code circuit neighbor comparator (2), inner by with or circuit (12), similitude flag register (13), coding circuit (14) and MUX two (15) form; Neighbor comparator (2) is anticipated the not overlapping neighbor that circuit (1) is exported to image, carries out the same exclusive disjunction of step-by-step, and operation result is placed in the N position similitude flag register (13); Coding circuit (14) is encoded to the numerical value in the similitude flag register (13), when N-1 1 being arranged or when above in this N bit data, coding circuit (14) is then exported S1S2S3=100, when N-1 0 being arranged or when above in this N bit data, coding circuit (14) is then exported S1S2S3=010, under other situations, coding circuit (14) output S1S2S3=001; MUX two (15) is delivered to similitude coding circuit (3), diversity coding circuit (6) and scrambler coding circuit (5) respectively with two not overlapping neighbors under the control of signal S1S2S3, simultaneously the S1S2S3 signal is respectively as the enable signal of similitude coding circuit (3), scrambler coding circuit (5) and diversity coding circuit (6).
4. digital audio-video signal serial deserializer according to claim 1, it is characterized in that, described serial code circuit similitude coding circuit (3) by data latches three (16), data latches four (20), step-by-step negate circuit (19), insert circuit (17) and sign insertion circuit (18) is formed every the position; When the S1=1 of neighbor comparator (2) output, data on data latches three (16) and data latches four (20) the image data lines, wherein the data in the data latches four (20) are after step-by-step negate circuit (19) is handled, inserting the 1st pixel mixing of circuit (17) neutralization every the position, form new 2N bit data, regulation is the data of the 1st pixel from high position 2n+1 position, and the 2n position is the data of the 2nd pixel, and n is less than 8; Sign is inserted circuit (18) and is inserted 10 in 2N bit data front, and data are become the output of 2N+2 Bits Serial sign indicating number.
5. digital audio-video signal serial deserializer according to claim 1, it is characterized in that, described serial code circuit diversity coding circuit (6) by data latches five (21), data latches six (24), insert circuit (22) and sign insertion circuit (23) is formed every the position; When the S2=1 of neighbor comparator (2) output, data on data latches five (21) and data latches six (24) the image data lines, inserting every the position in the circuit (22) the 1st pixel and the 2nd pixel mixing, form new 2N bit data, regulation is the data of the 1st pixel from high position 2n+1 position, the 2n position is the data of the 2nd pixel, and n is less than 8; Sign is inserted circuit (23) and is inserted 01 in 2N bit data front, and data are become the output of 2N+2 Bits Serial sign indicating number.
6. digital audio-video signal serial deserializer according to claim 1, it is characterized in that, described serial code circuit synchronizing generator (8) can between frame synchronization and row sync period, handle and the transmission of digital audio signal, when the H signal of synchronizing generator (8) output and V signal are effective, control clock circuit (7) will be exported the S0 signal, make S1S2S3=000, stop neighbor comparator (2) work, while similitude coding circuit (3), scrambler coding circuit (5) and diversity coding circuit (6) quit work, MUX one (4) is under the control of S4 signal, with synchronous mark sign indicating number and the audio output signal and the serial data output connection of synchronizing generator (8) generation, thus output frame synchronous mark sign indicating number, row synchronous mark sign indicating number and serial audio signal.
7. digital audio-video signal serial deserializer according to claim 1, it is characterized in that the identity code identification and the data multiplex control circuit (39) of the described decoding circuit that unstrings are made up of 2N+2 bit data latch seven (46), synchronous mark sign indicating number identification circuit (47) and Data Labels sign indicating number identification circuit (48); Input clock Clock drives 2N+2 bit data latch seven (46) and latchs current data.
8. digital audio-video signal serial deserializer according to claim 1, it is characterized in that, the described decoding circuit that unstrings similar solution decoding circuit (40), when control signal E1 is effective, adopted the data handling procedure of similitude coding circuit (3) contrary; Diversity decoding circuit (42) has adopted the data handling procedure of diversity coding circuit (6) contrary when control signal E3 is effective; Synchronously and audio signal restore circuit (44), when control signal E4 is effective, adopted the data handling procedure of synchronizing generator (8) contrary.
9. the implementation method of the described digital audio-video signal serial of claim 1 deserializer is characterized in that this method passes through following step successively:
The first, when effective frame synchronization, row synchronously and after vision signal occurs, synchronizing generator (8) will be by the synchronous mark sign indicating number of MUX one (4) transmit frame and row, after having only effective capable synchronous mark sign indicating number to finish, control clock circuit (7) just can be exported S0, CON, CK and OE signal effectively, starts image and anticipates circuit (1) and neighbor comparator circuit (2) work;
The second, the grouping of neighbor: under the control of input clock, image is anticipated circuit (1) each N bit data timesharing output of RGB with the outside input, and the N bit data of first pixel is temporarily stored in data latches one (10), the N bit data of the 2nd pixel is temporarily stored in data latches two (11), and the data parallel with these two neighbors outputs to neighbor comparator (2) again; Image is anticipated circuit (1) video data of temporary the 3rd pixel more then, forms second group of neighbor with the 4th pixel data, by that analogy;
Three, judge the similitude of every group of neighbor: the data for each group neighbor are carried out same exclusive disjunction, divide three kinds of situations to classify: when the value of the neighbor data of two N positions equates, then the result behind the two data inclusive ORs is complete 1, this situation appears at the zone of video image background or solid color, and our preset threshold is to have two neighbors of N-1 and N 1 expression similar; When the value of the neighbor data of two N positions was opposite, then the result behind the two data inclusive ORs was complete 0, and this situation appears at the borderline region of video image, and our preset threshold is that N-1 and two adjacent datas of N 0 expression are different;
Four, for two neighbors, carry out the similitude encoding process,, and insert every the position, form serial data stream output with the one other pixel step-by-step with one of them pixel step-by-step negate with similitude;
Five, for two neighbors, carry out the diversity encoding process, one of them pixel and one other pixel step-by-step are inserted every the position, form serial data stream output with diversity;
Six, in other cases, two neighbors are formed the 2N bit data, by the scrambler algorithm, form serial data stream output;
Seven, for the serial data stream of similitude encoding process in front titled with " 10 ", form the 2N+2 bit data stream; In front titled with " 01 ", form the 2N+2 bit data stream for the serial data stream of diversity encoding process; Titled with " 11 ", form the 2N+2 bit data stream for the data of scrambler encoding process;
Eight, between frame synchronization and row sync period, synchronizing generator (8) produces the synchronous mark code of frame and row, through MUX one (4) output; Row synchronous mark code is divided into two sections, and between two sections codes, voice data is handled and sent to synchronizing generator (8);
That nine, passes through MUX one (4) timesharing at last passes through optical fiber or radio wave transmit frame synchronous mark sign indicating number, row synchronous mark sign indicating number, serial voice data and serial video data.
Ten, unstring decoding circuit from the serial data that receives by optical fiber or radio wave clock data recovery circuit (37), recover the data and the identity code of synchronised clock and 2N+2 position;
The 11, by serial data and conversion and clock down conversion circuit (38), conversion produces the parallel data of work clock Clock and 2N+2 position;
The 12, by identity code identification and data multiplex control circuit (39) parallel 2N+2 bit data is analyzed, extracted digital coding identity code and synchronous mark sign indicating number, produce E1, E2, E3, E4 control signal;
The 13, under the control of E1, E2, E3, E4 signal, data are carried out similitude decoding, scrambler decoding, diversity decoding, synchronizing signal decoding and audio signal decoding respectively;
The 14, the video data that obtains of decoding outputs to the external display circuit system under the control of clock signal, frame synchronizing signal and line synchronizing signal; Audio signal, clock signal, frame synchronizing signal and line synchronizing signal directly output to the external display circuit system.
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