CN105490283A - Reactive power compensation controller for power - Google Patents
Reactive power compensation controller for power Download PDFInfo
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- CN105490283A CN105490283A CN201510610473.8A CN201510610473A CN105490283A CN 105490283 A CN105490283 A CN 105490283A CN 201510610473 A CN201510610473 A CN 201510610473A CN 105490283 A CN105490283 A CN 105490283A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/30—Reactive power compensation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/70—Smart grids as climate change mitigation technology in the energy generation sector
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/20—Systems supporting electrical power generation, transmission or distribution using protection elements, arrangements or systems
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/22—Flexible AC transmission systems [FACTS] or power factor or reactive power compensating or correcting units
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Abstract
The invention belongs to the technical field of power equipment, and particularly relates to a reactive power compensation controller for power, in particular to a device of the reactive power compensation controller applied to an electric power line. The reactive power compensation controller for power is a design of the reactive power compensation controller on the basis of an FPGA and DSP unit, and comprises a power supply unit, the FPGA and DSP unit, a key input unit, a liquid crystal display unit, a communication unit and a control unit. Automatic tracking compensation is carried out according to the change condition of a reactive power and a voltage of the line, so that the power factor is improved; the voltage quality is improved; the reactive power transmission flow of a power distribution line is reduced; the reactive power transmission distance of the power distribution line is shortened; and the reactive power compensation controller also has significant characteristics of high reliability, small size, easiness in installation, powerful function and low cost.
Description
Technical field
The invention belongs to electrical equipment technical field, particularly relate to a kind of electric reactive compensating controller, specifically a kind of device being applied to power circuit idle compensating control.
Background technology
Rural power grids circuit is longer, and power load distributing is uneven, and the compensation point that need install is more, if indiscriminately imitate the reactive power compensation pattern of transformer station, investment certainly will be caused large, and compensation effect is not obvious, and installation and maintenance are inconvenient.If adopt fixed location to install the compensation method of fixed capacity, although invest less, owing to not adding any protection, in the rural power grids that service conditions is severe, normal generation capacitor burnout failure, causes potential safety hazard to operation of power networks.
Therefore existing reactive power compensator, substantially also also exists function singleness, poor stability, the weak points such as precision is low.
Summary of the invention
The present invention is directed to above-mentioned the deficiencies in the prior art part, a kind of electric reactive compensating controller is provided.Object is to provide a kind of high-tension line reactive power compensation automatic switching, protection act is reliable, switch on-off capacity is large, easy for installation, and adapts to very much the idle compensating control of the needs that rural power grids circuit is long, compensation point is many, service conditions is severe.
For achieving the above object, the technical solution adopted in the present invention is:
Electric reactive compensating controller, be the design of the idle compensating control based on FPGA+DSP unit, it comprises: power subsystem, FPGA+DSP unit, key-press input unit and liquid crystal display, communication unit, control unit; Described FPGA+DSP cellular construction can realize logic control and complicated algorithm coordinated control function easily; Annexation is: data acquisition unit, input and output unit, communication unit and two-port RAM unit are connected to FPGA unit; And FPGA unit and DSP unit realize data interaction by two-port RAM, and multimode communication unit is connected with DSP unit with man-machine interaction unit, push-button unit and liquid crystal display are then revised and the function such as control signal display by completing controling parameters with control unit communication; Such hardware configuration can realize the real-time operation of complicated algorithm and logic control.
Described FPGA+DSP unit, first, FPGA supports parallel and flowing structure; Like this can by the concurrent working of multiple processing unit (PE), the algorithm that energy implementation structure is good, data volume is large and high performance Digital Signal Processing; Secondly, FPGA is inner embedded DSP multiplier module, these unit are hardware modules, and the speed of service is very high, are applicable to the algorithm of a large amount of multiplication calculating of needs; Described dsp chip is based on software programmable, and development language is C language mainly, and indivedual occasion needs to write assembler language; Described FPGA+DSP unit, wherein fpga chip and dsp chip can configure mutually between the two; Under normal circumstances, DSP can as the master controller of system, after FPGA powers on by DSP to complete configuration; At the duration of work of system, DSP as required, can reconfigure FPGA, realizes the function remodeling of system.
Described FPGA+DSP unit, switching capacitance measures realization that is how many and FUZZY ALGORITHMS FOR CONTROL to need the data collected according to FPGA to judge, the flexibility that FPGA+DSP builds can be given full play to, DSP can select different configuration files to be loaded in FPGA according to fuzzy control method, realizes self adaptation Dynamic controlling; In addition, in system work process, if dsp chip discovery feature in process of self-test is abnormal, fpga chip also can be asked to reconfigure oneself.
Described key-press input unit, button input hinders rows, GAL20V8B programming in logic chip, button etc. by 9 pins and forms, and can realize activating, confirm, exit, restart, the push button function such as up and down; Utilize GAL20V8B to realize 83 decoding functions, reduce the pin that button is connected to dsp chip, save mcu resource, pull-up function is realized by resistance row and VCC power supply, realize high level when a button is depressed to low level saltus step, single-chip microcomputer scans each button state, realizes button corresponding function; Realize simple man-machine communication, when button is not pressed, input port is high level, representing does not have button to press, when button is pressed, single-chip microcomputer input port is low level, now button is pressed, and by the low and high level of read port, single-chip microcomputer can judge whether button is pressed, thus perform the function of each button.
Described liquid crystal display; there are serial communication and parallel communication two kinds of communication modes; adopt parallel mode; shared I/O mouth resource is many, but fast response time, can the display of real-time tracking signal; serial mode speed is slower than parallel mode; the controller general I/O resource of this system is a lot, adopts parallel mode to carry out the display of measurement data, protection information, fault waveform, fault message is prompted to operations staff simultaneously.
Described communication unit is that ethernet communication has 10Mbit or 100Mbit adaptive communications ability; There is RS232 interface, RS485 interface, USB interface and jtag interface simultaneously; Described ethernet communication adopts Realtek company third generation Fast Ethernet control chip RTL8019, it supports EthernetII and IEEE802.3 standard, embedded 16KbitSRAM, 10Mbps can be realized on the twisted-pair by Ethernet switch to transmit and receive data simultaneously, there are 16 position datawire interfaces and 20 bit address line interfaces, support the data pattern of 8 or 16, support wire jumper and wire jumper free two kinds of patterns, support the interrupt requests of 8 circuits, support 3 kinds of reference power supply " shut " mode"s.
Described control unit, realizes the control of opening-closing capacitor bank, and by dividing, closing relay, latching relay, signal relay forms, and relay connects vacuum permanent magnet circuit breaker, with the fling-cut switch of vacuum permanent magnet circuit breaker as capacitor
Described FPGA+DSP unit mainly divides according to function, the collection of FPGA unit primary responsibility data and calculating, voltage, current effective value that the data collected are current in fast fourier transform computational scheme, active power, reactive power, the parameters such as power factor, DSP is given the parameter calculated, DSP realizes the function such as switching and protecting control of capacitor according to FUZZY ALGORITHMS FOR CONTROL, and have DSP unit to export control signal, complete the switching of Capacitor banks and the protection of electric capacity; Judge that switching capacitance measures realization that is how many and FUZZY ALGORITHMS FOR CONTROL according to the data that FPGA unit collects, the flexibility that FPGA+CPLD builds just can be given full play in this application, DSP unit can select different configuration files to be loaded in FPGA unit according to fuzzy control method, realizes fuzzy dynamic and controls; In addition, in system work process, if dsp chip discovery feature in process of self-test is abnormal, fpga chip also can be asked to reconfigure oneself; Complete amendment and the function setting of parameter finally by key-press input unit and liquid crystal display, and by optimum configurations, the information displaying such as operation result out.
Described FPGA unit is the FPGA unit of idle compensating control, it can carry out analytical calculation to input signal, draw the voltage of circuit, electric current, active power, reactive power, the parameters such as power factor, according to reactive power and power factor core controling parameters, obtain the reactive power needed for load, calculate the reactive compensation capacity needed for circuit, input in DSP, then according to fuzzy control theory, select multiple switching control mode, mainly contain the type of controlling by time variable, by voltage-controlled type, temporally/voltage-controlled type, by power factor controlling type, by reactive power and voltage integrated control type, remote control type, Manual local controlling, the lagging reactive power of adjustment circuit and power factor, complete the improvement of the quality of power supply,
The model of described DSP unit is TMS320F2812, as the core cell of FUZZY ALGORITHMS FOR CONTROL and communication, the model of described FPGA unit is EP1C12Q240C8, as the auxiliary unit that signals collecting calculates, FPGA unit is responsible for gathering voltage and current in circuit, the voltage that the data collected are current in fast fourier transform computational scheme, current effective value, active power, reactive power, the parameters such as power factor, DSP unit is given the parameter calculated, DSP unit realizes the function such as switching and protecting control of capacitor according to FUZZY ALGORITHMS FOR CONTROL.
Advantage of the present invention and effect are:
Compared with prior art, current controller control algolithm is simple, can not reach accurate control, and realtime control is poor, does not have remote control function.The present invention has following features: controller is idle according to circuit, the situation of change of voltage carries out automatic tracking and compensating, improves power factor, improves quality of voltage, reduces the idle feed flow of distribution line, shortens the idle fed distance of distribution line.The application of FPGA+DSP, strengthens the reliability of control system, can reach real-time measurement and control; Ethernet has high-speed data communication ability and antijamming capability, and can realize remote measurement, remote signalling, remote control, remote regulating, the inquiry of the setting of protection definite value and device operating state; Button and display circuit, use LCD liquid crystal display, realize parameters input arrange and measurement data, protection information, fault waveform display, display module, employing parallel mode, fast response time, man-machine interaction is very strong; Defencive function is complete: have overvoltage protection, under-voltage protection, current quick, overcurrent protection, overload protection, zero-sequence current protection, unbalanced fault protection, tripping protection, open-phase protection, the protection of capacitor openings triangular voltages, harmonic voltage protection, harmonic current protection, and can ask according to demand and customize; Measurement function: high-acruracy survey electric current, voltage, active power, reactive power, power factor, frequency; Highly integrated: to integrate the several functions such as protection, measurement, control, monitoring, communication, logout; Friendly man-machine interface: graphic lcd shows, Dynamic Announce primary system figure, real-time waveform figure, fault oscillograph, various electric parameter and protection information; In addition the present invention also has high reliability, and volume is little, easily installs, powerful, the distinguishing feature that cost is low.
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of idle compensating control of the present invention;
Fig. 2 is power circuit principle figure of the present invention;
Fig. 3 is key circuit in button display circuit schematic diagram of the present invention;
Fig. 4 is liquid crystal display circuit in button display circuit schematic diagram of the present invention;
Fig. 5 is Ethernet communication circuit schematic diagram of the present invention.
Embodiment
The present invention is a kind of electric reactive compensating controller, specifically a kind of design of the idle compensating control based on FPGA+DSP unit.It comprises: power subsystem, FPGA+DSP unit, key-press input unit and liquid crystal display, communication unit, control unit.FPGA+DSP cellular construction can realize logic control and complicated algorithm coordinated control function easily.Annexation is: data acquisition unit, input and output unit, communication unit and two-port RAM unit are connected to FPGA unit; And FPGA unit and DSP unit realize data interaction by two-port RAM, and multimode communication unit is connected with DSP unit with man-machine interaction unit; Push-button unit and liquid crystal display are then revised and the function such as control signal display by completing controling parameters with control unit communication; Such hardware configuration can realize the real-time operation of complicated algorithm and logic control.
Power subsystem, power supply is the basic guarantee that whole system can normally work, if power circuit design is bad, system likely can not work, but or namely enable work radiating condition is bad, cause the abnormal conditions such as system instability.So how to select suitable power supply chip, and how reasonably placement-and-routing to be carried out to power supply, be all worth research of making great efforts.
FPGA+DSP unit, first, FPGA supports parallel and flowing structure.Like this can by the concurrent working of multiple processing unit (PE), the algorithm that energy implementation structure is good, data volume is large and high performance Digital Signal Processing, be specially adapted in the present invention.Secondly, FPGA inside is embedded more and more DSP multiplier module.These unit are hardware modules, and the speed of service is very high, are particularly suitable for the algorithm that those need a large amount of multiplication to calculate.The highest level having exceeded 100GMAC of performance of multiplication operation of FPGA, far exceedes general dsp chip, close to the ability of dedicated processes chip (ASIC).In addition, FPGA is the same with other all programmable devices, has extraordinary flexibility.Particularly the FPGA of certain model has started to support dynamic-configuration or Partial Reconstruction, provides possibility for designing high intelligent signal handling equipment.
Dsp chip is based on software programmable, and development language is C language mainly, and indivedual occasion needs to write assembler language.Relative to HDL language, C language more easily allows beginner accept, and therefore dsp chip is widely used in signal transacting field.Meanwhile, C language belongs to high-level language, and the difficulty therefore describing complicated algorithm on DSP will lower than FPGA.In addition, the structure of dsp chip is also applicable to data volume greatly, the algorithm that repeatability is high.Particularly take advantage of and add the intensive and for of accumulation calculating (MAC) and to circulate intensive algorithm.Dsp chip generally adopts time upper compression and two kinds of spatially parallel Main Means to realize high performance data processing.On time, compress technique comprises one-cycle instruction, special hardware multiplication accumulator and multiple addressing system etc.: spatially concurrent technique comprises Harvard's formula bus structures, multioperation unit and pipelining etc. flexibly.
Signal processing system based on FPGA+DSP can possess the advantage of FPGA and DSP simultaneously.
(1) higher computing ability is supported.
The computing capability of FPGA+DSP dual chip cell processing system is more powerful relative to system-on-a-chip, and can give full play to the performance potential of two kinds of chips.
(2) reconfiguration scheme flexibly.
Fpga chip and dsp chip can configure mutually between the two.Under normal circumstances, DSP can as the master controller of system, after FPGA powers on by DSP to complete configuration.At the duration of work of system, DSP as required, can reconfigure FPGA, realizes the function remodeling of system.
In the present invention, switching capacitance measures realization that is how many and FUZZY ALGORITHMS FOR CONTROL to need the data collected according to FPGA to judge, the flexibility that FPGA+DSP builds just can be given full play in this application, DSP can select different configuration files to be loaded in FPGA according to fuzzy control method, realizes self adaptation Dynamic controlling.In addition, in system work process, if dsp chip discovery feature in process of self-test is abnormal, fpga chip also can be asked to reconfigure oneself.Such system possesses certain self-repairing capability, more intelligent.
(1) development difficulty and system cost compromise.
From control system cost angle, single-chip should be best scheme.But no matter be adopt FPGA or DSP, the solution development difficulty of single-chip all can improve.The scheme of single FPGA realizes complicated control can be more difficult, and the double counting that the scheme of single DSP realizes big data quantity has great difficulty.
Described key-press input unit, button input hinders rows, GAL20V8B programming in logic chip, button etc. by 9 pins and forms, and can realize activating, confirm, exit, restart, the push button function such as up and down.Utilize GAL20V8B to realize 83 decoding functions, reduce the pin that button is connected to dsp chip, save mcu resource, pull-up function is realized by resistance row and VCC power supply, realize high level when a button is depressed to low level saltus step, single-chip microcomputer scans each button state, realizes button corresponding function.Realize simple man-machine communication, when button is not pressed, input port is high level, representing does not have button to press, when button is pressed, single-chip microcomputer input port is low level, now button is pressed, and by the low and high level of read port, single-chip microcomputer can judge whether button is pressed, thus perform the function of each button.
Described liquid crystal display; adopt liquid crystal display; have serial communication and parallel communication two kinds of communication modes, adopt parallel mode, shared I/O mouth resource is many; but fast response time; can the display of real-time tracking signal, serial mode speed is slower than parallel mode, and the controller general I/O resource of this system is a lot; adopt parallel mode to carry out the display of measurement data, protection information, fault waveform, fault message is prompted to operations staff simultaneously.
Described communication unit, this device has high-speed data communication ability and antijamming capability, and current ethernet communication has 10Mbit or 100Mbit adaptive communications ability, and Optical Fiber Transmission has good antijamming capability.Therefore, adopt fiber optic Ethernet communication mode to strengthen antijamming capability and the high-speed communication ability of this device, expansion simultaneously has conventional RS232 interface, RS485 interface, USB interface and jtag interface.Multiple communication modes in electric power system the today of depositing, in the urgent need to a kind of current standard that there is high speed transmission abilities, there is uniform transmission form, under Utilities Electric Co. of various countries and institute promote international standard IEC61850, ethernet communication is made to become the standard (IEEE802.3) of communication network in electric power system.Therefore, using IEEE802.3 standard as the external Primary communication form of this device.The ethernet communication of this device adopts Realtek company third generation Fast Ethernet control chip RTL8019, it supports EthernetII and IEEE802.3 standard, embedded 16KbitSRAM, 10Mbps can be realized on the twisted-pair by Ethernet switch to transmit and receive data simultaneously, there are 16 position datawire interfaces and 20 bit address line interfaces, support the data pattern of 8 or 16, support wire jumper and wire jumper free two kinds of patterns, support the interrupt requests of 8 circuits, support 3 kinds of reference power supply " shut " mode"s.
Described control unit, realizes the control of opening-closing capacitor bank.By dividing, close relay, latching relay, signal relay forms, relay connects vacuum permanent magnet circuit breaker, with the fling-cut switch of vacuum permanent magnet circuit breaker as capacitor, there is divide-shut brake speed fast, contact pressure is large, clearance between open contacts is large, excellent arc extinction performance, jumbo capacitive means can be cut-off and do not restrike, the micro power consumption of vacuum circuit-breaker self simultaneously, without the need to considering heat dissipation problem especially, and the permanent-magnet operating mechanism adopted is the most reliable a kind of operating mechanism of current structure, its part used is few, during work, main motion parts only has one, permanent magnet realizes the maintenance function of mechanism's terminal location, instead of traditional mechanical trip and locker.Switch coil only passes to a little pulse current when combined floodgate or sub-switching operation, coil does not generate heat substantially, fundamentally ensure that the life-span of coil.Therefore adopt permanent magnetic actuator vacuum circuit breaker to be very suitable for the frequent switching capacitor status of native system, there is the advantage that other switchgear is incomparable.
When the present invention works; FPGA unit and DSP unit mainly divide according to function, the collection of FPGA primary responsibility data and calculating, and DSP unit is responsible for the realization of fuzzy control strategy; and have DSP to export control signal, complete the switching of Capacitor banks and the protection of electric capacity.Switching capacitance measures realization that is how many and FUZZY ALGORITHMS FOR CONTROL to need the data collected according to FPGA to judge, the flexibility of FPGA+CPLD cell formation just can be given full play in this application, DSP unit can select different configuration files to be loaded in FPGA unit according to fuzzy control method, realizes fuzzy dynamic and controls.In addition, in system work process, if dsp chip discovery feature in process of self-test is abnormal, fpga chip also can be asked to reconfigure oneself.The FPGA of idle compensating control carries out analytical calculation to input signal, draw the voltage of circuit, electric current, active power, idle cell power, the parameters such as power factor, according to reactive power and power factor core controling parameters, obtain the reactive power needed for load, calculate the reactive compensation capacity needed for circuit, input in DSP unit, then according to fuzzy control theory, select multiple switching control mode, mainly contain the type of controlling by time variable, by voltage-controlled type, temporally/voltage-controlled type, by power factor controlling type, by reactive power and voltage integrated control type, remote control type, Manual local controlling, the lagging reactive power of adjustment circuit and power factor, complete the improvement of the quality of power supply, this device is also provided with perfect defencive function, realizes the defencive functions such as overvoltage protection, under-voltage protection, current quick, overcurrent protection, overload protection, the application of Ethernet, can be sent to backstage in real time the action at all scenes and guard signal and coordinate monitor system software to carry out display analysis, the active power of circuit, reactive power, voltage total harmonic distortion factor, current total harmonic distortion
The parameters such as rate and capacitor three-phase current, really can realize remote control switching and defencive function; The application of key-press input and liquid crystal display circuit, can complete amendment and the function setting of parameter, and by optimum configurations, the information displaying such as operation result out.
The present invention is the design of the Multifunctional Reactive integrated protection controller based on the realization of DSP+FPGA unit, the model of DSP is TMS320F2812, as the core cell of FUZZY ALGORITHMS FOR CONTROL and communication, the model of FPGA is EP1C12Q240C8, as the auxiliary unit that signals collecting calculates, FPGA is responsible for gathering voltage and current in circuit, the voltage that the data collected are current in fast fourier transform computational scheme, current effective value, active power, reactive power, the parameters such as power factor, DSP is given the parameter calculated, DSP realizes the function such as switching and protecting control of capacitor according to FUZZY ALGORITHMS FOR CONTROL.
As shown in Figure 1, Fig. 1 is the structured flowchart of idle compensating control of the present invention, and the object of the present invention's protection comprises the overall structure function described in this block diagram, and DSP+FPGA is the controller core unit of name of the present invention.FPGA+DSP unit application, FPGA supports parallel and flowing structure.Like this can by the concurrent working of multiple processing unit (PE), the algorithm that energy implementation structure is good, data volume is large and high performance Digital Signal Processing, be specially adapted in the present invention.Secondly, FPGA inside is embedded more and more DSP multiplier module.These modules are hardware modules, and the speed of service is very high, are particularly suitable for the algorithm that those need a large amount of multiplication to calculate.The highest level having exceeded 100GMAC of performance of multiplication operation of FPGA, far exceedes general dsp chip, close to the ability of dedicated processes chip (ASIC).In addition, FPGA is the same with other all programmable devices, has extraordinary flexibility.Particularly the FPGA of certain model has started to support dynamic-configuration or Partial Reconstruction, provides possibility for designing high intelligent signal handling equipment.Collecting unit major function gathers line voltage and electric current, and through signal processing circuit, be connected to FPGA unit and realize the control of many AD data sampling time sequence, and by the real-time data transmission of collection in two-port RAM, DSP constantly reads data and calculates from RAM, and exports control signal and carry out Logic judgment through RAM to FPGA.The logic control of FPGA primary responsibility and communication function, the interpersonal interactive functions such as the calculating of DSP primary responsibility algorithm, button display, and notice has multimode communication unit.
FPGA power circuit described in Fig. 2, AS2380 can provide 3A electric current, linear power supply, is suitable for below 240 pins, the FPGA below 300,000 gates.For linear power supply, the pass of output and input voltage is: Vout=(1+RP3/RP2) * Vref, and Vref is generally 1.25V, input Vin is 5V, exports as 1.5V, RP2/RP3=1/5, and RP3 General Requirements 100 ~ 150 ohm, RP3=100, RP2=500.If have employed the chip that fixed level exports, only need RP3 ground connection, RP2 does not weld.
As shown in Figure 3, Fig. 3 is key circuit in button display circuit schematic diagram of the present invention; Button input hinders rows, GAL20V8B programming in logic chip, button etc. by 9 pins and forms, and can realize activating, confirm, exit, restart, the push button function such as up and down.GAL20V8B is utilized to realize 83 decoding functions, reduce the pin that button is connected to TMS320F2812 chip, save mcu resource, pull-up function is realized by resistance row and VCC power supply, realize high level when a button is depressed to low level saltus step, single-chip microcomputer scans each button state, realizes button corresponding function.
As shown in Figure 4, Fig. 4 is liquid crystal display circuit in button display circuit schematic diagram of the present invention; Display translation is made up of large-screen lc display module SMG240128A, 74HC138, LCD MODULE SMG240128A and TMS320F2812 interface adopt 8 position datawires to walk abreast input and output and 8 control lines, will generate read-write enable signal by logical combination.A0, A1 are connected respectively to CS1, CS2 pin, four control signals are mapped on the address space of TMS320F2812, facilitate writing of program.Generate chip selection signal with 74HC138, after convenient, expand other peripheral chips.Chip of LCD adopts the ST7920 chip of LCD of Xi Chuan company, this chip of LCD contains Chinese character base, accelerate writing of liquid crystal program, can realize showing letter, numerical chracter, middle character type and custom images, can be realized the adjustment of liquid crystal brightness and contrast by adjustable resistance, output type can realize dot matrix output, text output, images outputting.
Fig. 5 is Ethernet communication circuit schematic diagram of the present invention.Be the ethernet communication circuit theory diagrams be made up of RTL8019 chip, adopt wire jumper working method, namely the I/O of network interface card is determined by wire jumper with interrupting; JP pin connects high level, selects 16 bit data bus; Dsp processor selects register address and the storage address of RTL8019 by 4 address wire A0-A3, controls and realizes the reading of data; The pin of instruction network card status is connected to Green/RedLED, is convenient to intuitive judgment ethernet communication state; Controlled by programmable logic device (PSD4235G2) chip selection signal to RTL8019.RTL8019 Ethernet chip can not work independently, and a network transformer also must be had in the middle of RJ-45 interface and RTL8019 to carry out level conversion.
Operationally, the basic principle that DSP+FPGA divides is exactly data-intensive in the present invention, and algorithm is simple, the high function of repeatability is placed on FPGA and performs, i.e. voltage, electric current, active power, reactive factor, the calculation of parameter such as power factor are placed on FPGA and realize.Algorithm is complicated, and the low function of repeatability is distributed to DSP and is realized.FPGA is responsible for gathering voltage and current in circuit; voltage, current effective value that the data collected are current in fast fourier transform computational scheme; active power; reactive power; the parameters such as power factor; give DSP the parameter calculated, DSP realizes the function such as switching and protecting control of capacitor according to FUZZY ALGORITHMS FOR CONTROL.
In this example, the design cycle of FPGA+DSP unit is compared with independent FPGA or DSP design cycle, and maximum difference adds function exactly and divides link inside design cycle.Even if systemic-function is decomposed by the main purpose of this link, then distribute to FPGA and DSP and go to perform.In the present invention, the basic principle that function divides is exactly data-intensive, but the high function of the simple repeatability of algorithm is placed on execution on FPGA, and the function of control strategy and algorithm is distributed to DSP realization, can give full play to the speciality of two kinds of chips like this.Specifically, be exactly that FPGA is responsible for image data, and give dsp chip data, and DSP is used for processing the data collected.Due to the application of FGPA process chip, make the measurement of all parameters have extraordinary real-time, the application of Ethernet, achieves distributed AC servo system, and convenient operation personnel carry out the operating state that WEB browses and controls current controller; Key-press input and liquid crystal display circuit module make on-the-spot viewing operational factor and parameter modification provide conveniently.This device man-machine interaction is very strong, realizes hommization, and summary operates.
Test under premised on the technical program, give detailed execution mode and specific operation process, but protection scope of the present invention is not limited to following embodiment.
Claims (10)
1. electric reactive compensating controller, is characterized in that: the design being the idle compensating control based on FPGA+DSP unit, and it comprises: power subsystem, FPGA+DSP unit, key-press input unit and liquid crystal display, communication unit, control unit; Described FPGA+DSP cellular construction can realize logic control and complicated algorithm coordinated control function easily; Annexation is: data acquisition unit, input and output unit, communication unit and two-port RAM unit are connected to FPGA unit; And FPGA unit and DSP unit realize data interaction by two-port RAM, and multimode communication unit is connected with DSP unit with man-machine interaction unit, push-button unit and liquid crystal display are then revised and the function such as control signal display by completing controling parameters with control unit communication; Such hardware configuration can realize the real-time operation of complicated algorithm and logic control.
2. an electric reactive compensating controller according to claim 1, is characterized in that: described FPGA+DSP unit, and first, FPGA supports parallel and flowing structure; Like this can by the concurrent working of multiple processing unit (PE), the algorithm that energy implementation structure is good, data volume is large and high performance Digital Signal Processing; Secondly, FPGA is inner embedded DSP multiplier module, these unit are hardware modules, and the speed of service is very high, are applicable to the algorithm of a large amount of multiplication calculating of needs;
Described dsp chip is based on software programmable, and development language is C language mainly, and indivedual occasion needs to write assembler language;
Described FPGA+DSP unit, wherein fpga chip and dsp chip can configure mutually between the two; Under normal circumstances, DSP can as the master controller of system, after FPGA powers on by DSP to complete configuration; At the duration of work of system, DSP as required, can reconfigure FPGA, realizes the function remodeling of system.
3. an electric reactive compensating controller according to claim 1, it is characterized in that: described FPGA+DSP unit, switching capacitance measures realization that is how many and FUZZY ALGORITHMS FOR CONTROL to need the data collected according to FPGA to judge, the flexibility that FPGA+DSP builds can be given full play to, DSP can select different configuration files to be loaded in FPGA according to fuzzy control method, realizes self adaptation Dynamic controlling; In addition, in system work process, if dsp chip discovery feature in process of self-test is abnormal, fpga chip also can be asked to reconfigure oneself.
4. an electric reactive compensating controller according to claim 1, it is characterized in that: described key-press input unit, button input hinders rows, GAL20V8B programming in logic chip, button etc. by 9 pins and forms, and can realize activating, confirm, exit, restart, the push button function such as up and down; Utilize GAL20V8B to realize 83 decoding functions, reduce the pin that button is connected to dsp chip, save mcu resource, pull-up function is realized by resistance row and VCC power supply, realize high level when a button is depressed to low level saltus step, single-chip microcomputer scans each button state, realizes button corresponding function; Realize simple man-machine communication, when button is not pressed, input port is high level, representing does not have button to press, when button is pressed, single-chip microcomputer input port is low level, now button is pressed, and by the low and high level of read port, single-chip microcomputer can judge whether button is pressed, thus perform the function of each button.
5. an electric reactive compensating controller according to claim 1; it is characterized in that: described liquid crystal display; there are serial communication and parallel communication two kinds of communication modes; adopt parallel mode; shared I/O mouth resource is many; but fast response time; can the display of real-time tracking signal; serial mode speed is slower than parallel mode; the controller general I/O resource of this system is a lot; adopt parallel mode to carry out the display of measurement data, protection information, fault waveform, fault message is prompted to operations staff simultaneously.
6. an electric reactive compensating controller according to claim 1, is characterized in that: described communication unit, is that ethernet communication has 10Mbit or 100Mbit adaptive communications ability; There is RS232 interface, RS485 interface, USB interface and jtag interface simultaneously; Described ethernet communication adopts Realtek company third generation Fast Ethernet control chip RTL8019, it supports EthernetII and IEEE802.3 standard, embedded 16KbitSRAM, 10Mbps can be realized on the twisted-pair by Ethernet switch to transmit and receive data simultaneously, there are 16 position datawire interfaces and 20 bit address line interfaces, support the data pattern of 8 or 16, support wire jumper and wire jumper free two kinds of patterns, support the interrupt requests of 8 circuits, support 3 kinds of reference power supply " shut " mode"s.
7. an electric reactive compensating controller according to claim 1, it is characterized in that: described control unit, realize the control of opening-closing capacitor bank, by dividing, closing relay, latching relay, signal relay forms, and relay connects vacuum permanent magnet circuit breaker, with the fling-cut switch of vacuum permanent magnet circuit breaker as capacitor.
8. the control method of an electric reactive compensating controller according to claim 1, it is characterized in that: described FPGA+DSP unit mainly divides according to function, the collection of FPGA unit primary responsibility data and calculating, the voltage that the data collected are current in fast fourier transform computational scheme, current effective value, active power, reactive power, the parameters such as power factor, DSP is given the parameter calculated, DSP realizes the function such as switching and protecting control of capacitor according to FUZZY ALGORITHMS FOR CONTROL, and have DSP unit to export control signal, complete the switching of Capacitor banks and the protection of electric capacity, judge that switching capacitance measures realization that is how many and FUZZY ALGORITHMS FOR CONTROL according to the data that FPGA unit collects, the flexibility that FPGA+CPLD builds just can be given full play in this application, DSP unit can select different configuration files to be loaded in FPGA unit according to fuzzy control method, realizes fuzzy dynamic and controls, in addition, in system work process, if dsp chip discovery feature in process of self-test is abnormal, fpga chip also can be asked to reconfigure oneself,
Complete amendment and the function setting of parameter finally by key-press input unit and liquid crystal display, and by optimum configurations, the information displaying such as operation result out.
9. the control method of an electric reactive compensating controller according to claim 8, it is characterized in that: described FPGA unit is the FPGA unit of idle compensating control, it can carry out analytical calculation to input signal, draw the voltage of circuit, electric current, active power, reactive power, the parameters such as power factor, according to reactive power and power factor core controling parameters, obtain the reactive power needed for load, calculate the reactive compensation capacity needed for circuit, input in DSP, then according to fuzzy control theory, select multiple switching control mode, mainly contain the type of controlling by time variable, by voltage-controlled type, temporally/voltage-controlled type, by power factor controlling type, by reactive power and voltage integrated control type, remote control type, Manual local controlling, the lagging reactive power of adjustment circuit and power factor, complete the improvement of the quality of power supply.
10. the control method of an electric reactive compensating controller according to claim 8, it is characterized in that: the model of described DSP unit is TMS320F2812, as the core cell of FUZZY ALGORITHMS FOR CONTROL and communication, the model of described FPGA unit is EP1C12Q240C8, as the auxiliary unit that signals collecting calculates, FPGA unit is responsible for gathering voltage and current in circuit, the voltage that the data collected are current in fast fourier transform computational scheme, current effective value, active power, reactive power, the parameters such as power factor, DSP unit is given the parameter calculated, DSP unit realizes the function such as switching and protecting control of capacitor according to FUZZY ALGORITHMS FOR CONTROL.
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| CN111146810A (en) * | 2020-01-20 | 2020-05-12 | 上海发电设备成套设计研究院有限责任公司 | Three-phase grid-connected cascade photovoltaic inverter and optical fiber communication control method thereof |
| CN111146810B (en) * | 2020-01-20 | 2021-05-11 | 上海发电设备成套设计研究院有限责任公司 | Three-phase grid-connected cascade photovoltaic inverter and optical fiber communication control method thereof |
| CN112688340A (en) * | 2020-12-21 | 2021-04-20 | 苏州沪港科技股份有限公司 | Reactive compensation controller for distributed photovoltaic power station |
| CN116799965A (en) * | 2023-08-24 | 2023-09-22 | 西安前进电器实业有限公司 | Intelligent control method and system for power consumption of vacuum circuit breaker |
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