CN105489594A - Semiconductor structure - Google Patents
Semiconductor structure Download PDFInfo
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- CN105489594A CN105489594A CN201410470150.9A CN201410470150A CN105489594A CN 105489594 A CN105489594 A CN 105489594A CN 201410470150 A CN201410470150 A CN 201410470150A CN 105489594 A CN105489594 A CN 105489594A
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- heavily doped
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Abstract
The invention discloses a semiconductor structure which comprises an improved electrostatic discharge protection element. The structure comprises a substrate, a well region formed in the substrate, a first heavily-doped region formed in the well region, a second heavily-doped region which is formed in the well region and is separated from the first heavily-doped region, a grid structure which is formed on the substrate and is located between the first and second heavily-doped regions, a field region which is formed in the well region below the first heavily-doped region and the grid structure, and a field oxide/shallow channel isolation structure which is formed to be adjacent to the first heavily-doped region. The field region is not formed below the second heavily-doped region. The well region and the field region are of a first doping type. The first and second heavily-doped regions are of a second doping region.
Description
Technical field
This specification is about a kind of semiconductor structure.This specification particularly comprises the semiconductor structure of static discharge (electrostaticdischarge, ESD) protection component about one.
Background technology
Static discharge may cause the breaking-up of sensitive electronic components.Therefore, electric static discharge protector often provides in the semiconductor structure.Metal oxide semiconductcor field effect transistor (Metal-Oxide-SemiconductorField-EffectTransistor; MOSFET), XDMOS extended drain metal-oxide-semiconductor field-effect transistor (ExtendedDrainMOSFET; EDMOSFET), lateral double diffusion metal oxide semiconductor field-effect transistor (LateralDouble-diffusedMOSFET; LDMOSFET) and application surface electric field reduce (ReducedSurfaceField; RESURF) element etc. of technology, can be used as electric static discharge protector.Research for electric static discharge protector is still constantly carried out so far with improvement.
Summary of the invention
In this manual, a kind of semiconductor structure comprising the electric static discharge protector of improvement is proposed.
According to some embodiments, this kind of semiconductor structure comprises a substrate, a well region (well), one first heavily doped region, one second heavily doped region, a grid structure, a place (fieldregion) and a field oxide.Well region is formed in substrate.Well region has one first doping type.First heavily doped region is formed in well region.First heavily doped region has one second doping type.Second heavily doped region to be formed in well region and to be separated with the first heavily doped region.Second heavily doped region has the second doping type.Grid structure to be formed on substrate between the first heavily doped region and the second heavily doped region.Place to be formed in well region under the first heavily doped region and grid structure.Under place is not formed at the second heavily doped region.Place has the first doping type.Field oxide is formed at adjacent first heavily doped region place.
According to some embodiments, this kind of semiconductor structure comprises a substrate, a well region, one first heavily doped region, one second heavily doped region, a grid structure, a place and shallow trench isolation (ShallowTrenchIsolation, a STI) structure.Well region is formed in substrate.Well region has one first doping type.First heavily doped region is formed in well region.First heavily doped region has one second doping type.Second heavily doped region to be formed in well region and to be separated with the first heavily doped region.Second heavily doped region has the second doping type.Grid structure to be formed on substrate between the first heavily doped region and the second heavily doped region.Place to be formed in well region under the first heavily doped region and grid structure.Under place is not formed at the second heavily doped region.Place has the first doping type.Isolation structure of shallow trench is formed at adjacent first heavily doped region place.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating institute's accompanying drawings, being described in detail below:
Accompanying drawing explanation
Figure 1A-Figure 1B is the schematic diagram of the semiconductor structure according to an embodiment.
Fig. 2 A-Fig. 2 B is the schematic diagram of the semiconductor structure according to an embodiment.
Fig. 3 is the schematic diagram of the semiconductor structure according to an embodiment.
Fig. 4 is the curve chart of the feature of the semiconductor structure that this specification one example is shown.
Fig. 5 is the curve chart of the feature of the semiconductor structure that a comparative example is shown.
Fig. 6 is the schematic diagram of the semiconductor structure according to an embodiment.
[symbol description]
102: substrate
104: electric static discharge protector
106: well region
108: the first heavily doped regions
110: the second heavily doped regions
112: grid structure
114: place
116: field oxide
118: grid dielectric medium
120: gate electrode
122,124: sept
126,128: light doping section
130: the three heavily doped regions
204: electric static discharge protector
232: the four heavily doped regions
304: electric static discharge protector
334: deep-well region
404: electric static discharge protector
414: place
416: trench isolation structures
Embodiment
Will now describe the semiconductor structure comprising electric static discharge protector.For the sake of clarity, may omit graphic in some elements.In the conceived case, identical element is indicated with identical component symbol.
Please refer to Figure 1A-Figure 1B, it illustrates the semiconductor structure according to an embodiment.Figure 1A is the vertical view of semiconductor structure, and Figure 1B is the profile of the semiconductor structure taking from Figure 1A section line B-B.
Semiconductor structure comprises substrate 102 and an electric static discharge protector 104.Substrate 102 can be silicon substrate or silicon-on-insulator (SiliconOnInsulator, SOI) substrate etc.In the present embodiment, electric static discharge protector 104 is depicted as MOSFET kenel illustratively.But electric static discharge protector 104 can be other kenels.Electric static discharge protector 104 comprises heavily doped region 110, well region 106,1 first heavily doped region 108,1 second grid structure 112 and a place 114.Well region 106 is formed in substrate 102.Well region 106 has one first doping type.First heavily doped region 108 is formed in well region 106.First heavily doped region 108 has one second doping type.Second heavily doped region 110 to be formed in well region 106 and to be separated with the first heavily doped region 108.Second heavily doped region 110 has the second doping type.First heavily doped region 108 can be source area, and the second heavily doped region 110 can be drain region.Grid structure 112 to be formed on substrate 102 between the first heavily doped region 108 and the second heavily doped region 110.More particularly, grid structure 112 comprises grid dielectric medium 118, gate electrode 120 and two septs 122,124, wherein grid dielectric medium 118 is formed on substrate 102, and gate electrode 120 is formed on grid dielectric medium 118, and two septs 122 and 124 are formed at two sides of gate electrode 120 respectively.Place 114 to be formed in well region 106 first heavily doped region 108 and grid structure 112 times.Place 114 is not formed at the second heavily doped region 110 times, to improve resistance to pressure.Place 114 has the first doping type.Semiconductor structure also comprises a field oxide 116.Field oxide 116 is formed at adjacent first heavily doped region 108 place.In the present embodiment, place 114 also may extend to field oxide 116 times.In the present embodiment, the first doping type can be p-type, and the second doping type can be N-shaped.In another embodiment, the first doping type can be N-shaped, and the second doping type can be p-type.
Electric static discharge protector 104 also can comprise two light doping sections 126 and 128.One of them is formed at adjacent first heavily doped region 108 in well region 106, and another is formed at adjacent second heavily doped region 110 in well region 106.Light doping section 126 and 128 has the second doping type.Light doping section 128 close to drain region (being the second heavily doped region 110 in the present embodiment) has the effect of falling low hot carrier effect, so protects drain region.
Electric static discharge protector 104 also can comprise one the 3rd heavily doped region 130.3rd heavily doped region 130 is formed in the first heavily doped region 108.3rd heavily doped region 130 has the first doping type.Such configuration constitutes the parasitic bipolar junction transistor (BipolarJunctionTransistor, BJT) improving electrostatic discharge (ESD) protection effect.
Being formed in the technique according to the semiconductor structure of the present embodiment, first in substrate 102, inject well region 106.Then, in well region 106, source area and drain region is formed, that is the first heavily doped region 108 and the second heavily doped region 110.Place 114 is injected in well region 106.Afterwards, field oxide 116 is formed.Sequentially form grid dielectric medium 118 and gate electrode 120.Then, in well region 106, light doping section 126 and 128 is injected.Afterwards, sept 122 and 124 is formed in two sides of gate electrode 120.The 3rd heavily doped region 130 is formed in the first heavily doped region 108.Contact (contact) and other structures can be formed afterwards.
Please refer to Fig. 2 A-Fig. 2 B, it illustrates the semiconductor structure according to another embodiment.Fig. 2 A is the vertical view of semiconductor structure, and Fig. 2 B is for taking from the profile of the semiconductor structure of Fig. 2 A section line B '-B '.In the present embodiment, electric static discharge protector 204 comprises one the 4th heavily doped region 232.4th heavily doped region 232 is formed in the second heavily doped region 110.3rd heavily doped region 130 and the 4th heavily doped region 232 can be formed alternately, as shown in Figure 2 A.4th heavily doped region 232 has the first doping type.The setting being similar to the 3rd heavily doped region 232, heavily doped region the 130, four can improve electrostatic discharge (ESD) protection effect.
Please refer to Fig. 3, it illustrates the semiconductor structure according to another embodiment.In the present embodiment, semiconductor structure also comprises for an isolated deep-well region 334.Deep-well region 334 is formed in substrate 102, and well region 106 is formed in deep-well region 334.The place 114 of electric static discharge protector 304 does not extend to deep-well region 334.Deep-well region 334 has the second doping type.
Fig. 4 marks the feature of the semiconductor structure of this specification one example, and Fig. 5 marks the feature of the semiconductor structure of a comparative example.The semiconductor structure of example and the semiconductor structure of comparative example have identical overall width and identical gate electrode to drain side standard (rule).Compared with the semiconductor structure of comparative example, ME for maintenance (holdingvoltage) increase about 20% of the semiconductor structure of example, driving voltage (triggervoltage) increase about 17%.The increase of ME for maintenance is conducive to the impact reducing latch-up (latch-up).The increase of driving voltage means that the semiconductor structure of example is more sturdy and durable.
Please refer to Fig. 6 now, it illustrates the semiconductor structure according to another embodiment.Semiconductor structure comprises substrate 102 and an electric static discharge protector 404.In the present embodiment, electric static discharge protector 404 is depicted as MOSFET kenel illustratively.But electric static discharge protector 404 can be other kenels.Electric static discharge protector 404 comprises heavily doped region 110, well region 106,1 first heavily doped region 108,1 second grid structure 112 and a place 414.Heavily doped region, well region 106, first heavily doped region 108, second 110 and the grid structure 112 of electric static discharge protector 404 are the heavily doped region, well region 106, first heavily doped region 108, second 110 and the grid structure 112 that are same as electric static discharge protector 104, and relevant describing is omitted at this point.Place 414 to be formed in well region 106 first heavily doped region 108 and grid structure 112 times.Place 414 is not formed at the second heavily doped region 110 times, to improve resistance to pressure.Place 414 has the first doping type.Semiconductor structure also comprises an isolation structure of shallow trench 416.Isolation structure of shallow trench 416 is formed at adjacent first heavily doped region 108 place.In the present embodiment, place 414 does not extend to isolation structure of shallow trench 416 times.In the present embodiment, the first doping type can be p-type, and the second doping type can be N-shaped.In another embodiment, the first doping type can be N-shaped, and the second doping type can be p-type.
Be similar to electric static discharge protector 104, electric static discharge protector 404 also can comprise two light doping sections 126 and 128 and/or one the 3rd heavily doped region 130.One the 4th heavily doped region as shown in Figure 2 also can be comprised according to the semiconductor structure of the present embodiment.A deep-well region as shown in Figure 3 also can be comprised according to the semiconductor structure of the present embodiment.
Being formed in the technique according to the semiconductor structure of the present embodiment, first in substrate 102, form isolation structure of shallow trench 416.Then, in substrate 102, well region 106 is injected.Afterwards, in well region 106, form source area and drain region, that is the first heavily doped region 108 and the second heavily doped region 110.Place 414 is injected in well region 106.Then, sequentially grid dielectric medium 118 and gate electrode 120 is formed.Light doping section 126 and 128 is injected in well region 106.Afterwards, sept 122 and 124 is formed in two sides of gate electrode 120.The 3rd heavily doped region 130 is formed in the first heavily doped region 108.Contact and other structures can be formed afterwards.
Under place is not formed at the second heavily doped region, according in the semiconductor structure of embodiment, rushing between source area and drain region can be avoided to wear (punch-through).Therefore, the resistance to pressure of the semiconductor structure according to embodiment can be improved.
In sum, although the present invention with preferred embodiment disclose as above, so itself and be not used to limit the present invention.Persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion of defining depending on the right of enclosing.
Claims (10)
1. a semiconductor structure, comprising:
One substrate;
One well region, is formed in this substrate, and this well region has one first doping type;
One first heavily doped region, is formed in this well region, and this first heavily doped region has one second doping type;
One second heavily doped region, being formed in this well region and being separated with this first heavily doped region, this second heavily doped region has this second doping type;
One grid structure, to be formed on this substrate between this first heavily doped region and this second heavily doped region;
One place, be formed in this well region under this first heavily doped region and this grid structure, this place has this first doping type, under wherein this place is not formed at this second heavily doped region; And
One field oxide, is formed at this first heavily doped region place adjacent.
2. semiconductor structure according to claim 1, under wherein this place more extends to this field oxide.
3. semiconductor structure according to claim 1, more comprises:
One light doping section, be formed at this second heavily doped region place adjacent in this well region, this light doping section has this second doping type.
4. semiconductor structure according to claim 1, more comprises:
One the 3rd heavily doped region, be formed in this first heavily doped region, the 3rd heavily doped region has this first doping type.
5. semiconductor structure according to claim 1, more comprises:
One the 4th heavily doped region, be formed in this second heavily doped region, the 4th heavily doped region has this first doping type.
6. semiconductor structure according to claim 1, more comprises:
One deep-well region, is formed in this substrate, and this deep-well region has this second doping type, and wherein this well region is formed in this deep-well region.
7. semiconductor structure according to claim 1, more comprises:
One electric static discharge protector, comprises this well region, this first heavily doped region, this second heavily doped region, this grid structure and this place.
8. a semiconductor structure, comprising:
One substrate;
One well region, is formed in this substrate, and this well region has one first doping type;
One first heavily doped region, is formed in this well region, and this first heavily doped region has one second doping type;
One second heavily doped region, being formed in this well region and being separated with this first heavily doped region, this second heavily doped region has this second doping type;
One grid structure, to be formed on this substrate between this first heavily doped region and this second heavily doped region;
One place, be formed in this well region under this first heavily doped region and this grid structure, this place has this first doping type, under wherein this place is not formed at this second heavily doped region; And
One isolation structure of shallow trench, is formed at this first heavily doped region place adjacent.
9. semiconductor structure according to claim 8, more comprises:
One light doping section, be formed at this second heavily doped region place adjacent in this well region, this light doping section has this second doping type.
10. semiconductor structure according to claim 8, more comprises:
One the 3rd heavily doped region, be formed in this first heavily doped region, the 3rd heavily doped region has this first doping type.
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| CN201410470150.9A CN105489594A (en) | 2014-09-16 | 2014-09-16 | Semiconductor structure |
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| CN201410470150.9A CN105489594A (en) | 2014-09-16 | 2014-09-16 | Semiconductor structure |
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Citations (6)
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| CN1941416A (en) * | 2005-09-28 | 2007-04-04 | 东部电子株式会社 | Ldmos device and method for manufacturing the same |
| CN101645447A (en) * | 2008-08-06 | 2010-02-10 | 联华电子股份有限公司 | Static discharge protection circuit element |
| CN102637744A (en) * | 2012-05-08 | 2012-08-15 | 中北大学 | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device |
| US20120273879A1 (en) * | 2011-04-27 | 2012-11-01 | Shekar Mallikarjunaswamy | Top drain ldmos |
| CN103855210A (en) * | 2012-12-03 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof |
| CN104037171A (en) * | 2013-03-04 | 2014-09-10 | 旺宏电子股份有限公司 | Semiconductor element, and manufacturing method and operation method thereof |
-
2014
- 2014-09-16 CN CN201410470150.9A patent/CN105489594A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1941416A (en) * | 2005-09-28 | 2007-04-04 | 东部电子株式会社 | Ldmos device and method for manufacturing the same |
| CN101645447A (en) * | 2008-08-06 | 2010-02-10 | 联华电子股份有限公司 | Static discharge protection circuit element |
| US20120273879A1 (en) * | 2011-04-27 | 2012-11-01 | Shekar Mallikarjunaswamy | Top drain ldmos |
| CN102637744A (en) * | 2012-05-08 | 2012-08-15 | 中北大学 | Signal operation instruction (SOI) transverse super junction power metal oxide semiconductor field effect transistor (MOSFET) device |
| CN103855210A (en) * | 2012-12-03 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof |
| CN104037171A (en) * | 2013-03-04 | 2014-09-10 | 旺宏电子股份有限公司 | Semiconductor element, and manufacturing method and operation method thereof |
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