CN105489542B - 芯片封装方法及芯片封装结构 - Google Patents

芯片封装方法及芯片封装结构 Download PDF

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CN105489542B
CN105489542B CN201510849034.2A CN201510849034A CN105489542B CN 105489542 B CN105489542 B CN 105489542B CN 201510849034 A CN201510849034 A CN 201510849034A CN 105489542 B CN105489542 B CN 105489542B
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bonding wire
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CN105489542A (zh
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谭小春
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Hangzhou Silergy Semiconductor Technology Ltd
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Abstract

本申请提供了一种芯片封装方法及芯片封装结构，所述封装方法包括：在载体表面的第一区域上形成焊线管脚，并在芯片的非有源面形成绝缘层，然后将芯片通过所述绝缘层粘贴到载体表面的第二区域，在进行引线键合和塑封工艺后，将载体与塑封体相剥离，使得绝缘层和焊线管脚裸露在塑封体的表面。这种封装方法形成的封装结构在贴装到PCB板上时，可保证芯片的非有源面与PCB之间的绝缘性，保证了封装结构的电气特性。此外，所述封装方法，无需使用预先制作好的引线框架，而是在封装的过程中形成焊线管脚，有利于提高封装设计的灵活性。

Description

芯片封装方法及芯片封装结构
技术领域
本发明涉及芯片封装技术领域，尤其涉及一种芯片封装方法及芯片封装结构。
背景技术
早期的芯片封装为双列直插式DI封装，这种封装布线和操作较为方便。但是，DIP封装的封装效率很低，且封装产品的面积较大，不利于提高内存条的容量，同时还会影响内存频率、传输速率和电器性能的提升。
为了减少芯片的封装面积，表面贴装技术(SMT封装)成为目前电子组装行业里比较受欢迎的封装技术，而在SMT封装中，QFN封装(方形扁平无引脚封装)成为主流。现有的QFN封装的方法通常是将半导体裸芯片的非有源面通过导电银胶安装在引线框架的中间焊盘上，然后再进行引线键合和塑封，使引线框架的引脚和中间焊盘均裸露在塑封体的表面。中间焊盘裸露在外，可增加芯片的散热性能。
然而，有些小功率器件对散热性能的要求并不高，但是对于其非有源面与PCB板直接的绝缘性要求非常，以防止漏电，影响了芯片的性能。对于这一类芯片的封装，常规的这种QFN封装方式已经不在适应。此外这种常规的QFN封装中，需要使用预先制作好的引线框架，而引线框架一旦制作好了，引脚的排布、间距和尺寸均已经确定，因而不利于封装的灵活性设计。
发明内容
有鉴于此，本发明提供了一种芯片封装方法及芯片封装结构，以保证芯片的非有源面与PCB板之间的绝缘性，同时提高封装的灵活性设计。
一种芯片封装方法，包括：
在载体的第一表面的第一区域上形成焊线管脚，并在芯片的非有源面形成绝缘层，所述芯片的非有源面与所述芯片的有源面相对；
将所述芯片通过所述绝缘层贴装在所述载体的第一表面的第二区域上；
将所述芯片的有源面上的电极通过导电引线与所述焊线管脚电连接，然后进行塑封工艺，以形成覆盖所述芯片和焊线管脚的包封体；
将所述载体与所述包封体进行剥离，以将所述焊线管脚和绝缘层裸露在所述包封体的表面。
优选的，所述的芯片封装方法还包括：在形成所述焊线管脚前，先至少将所述第二区域进行表面平坦化处理，以使所述载体与所述包封体进行剥离时，所述绝缘层可与所述第二区域相剥离开。
优选的，所述的芯片封装方法还包括：完成所述表面平坦化处理后，将所述第一区域进行表面粗糙化处理，以使得在所述第一区域上形成所述焊线管脚时，防止所述焊线管脚移位，且可使得在所述载体与所述包封体进行剥离时，所述焊线管脚可与所述第二区域相剥离开。
优选的，蚀刻所述第一区域，形成具有预定深度的凹槽，以实现所述第一区域表面的粗糙化处理。
优选的，在所述凹槽处电镀形成所述焊线管脚。
优选的，所述凹槽的深度介于0微米到5微米之间。
优选的，所述焊线管脚的底部与所述载体接触，所述焊线管脚的底部截面积小于顶部截面积。
优选的，在所述芯片的非有源面涂覆绝缘胶，以形成所述绝缘层，所述芯片的非有源面通过所述绝缘胶粘贴在所述第二区域的表面上。
优选的，采用机械剥离方法将所述载体与所述包封体进行剥离。
一种根据如任意一项芯片封装方法所形成芯片封装结构。
由上可见，本发明提供的芯片封装方法中，在载体表面的第一区域上形成焊线管脚，并在芯片的非有源面形成绝缘层，然后将芯片通过所述绝缘层粘贴到载体表面的第二区域，在进行引线键合和塑封工艺后，将载体与塑封体相剥离，使得绝缘层和焊线管脚裸露在塑封体的表面。这种封装方法形成的封装结构在贴装到PCB板上时，可保证芯片的非有源面与PCB之间的绝缘性，保证了封装结构的电气特性。此外，所述封装方法，无需使用预先制作好的引线框架，而是在封装的过程中形成焊线管脚，有利于提高封装设计的灵活性。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
图1为依据本发明实施例的芯片封装方法的工艺流程图；
图2a～2d为依据本发明实施例的芯片封装方法的各个工艺步骤中所形成的剖面结构图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中，相同的组成部分采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本发明的许多特定的细节，例如每个组成部分的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本发明。
图1为依据本发明实施例的芯片封装方法的工艺流程图。
参考图1所示，本发明提供的芯片方法主要包括以下几大步骤：
步骤S1:在载体的第一表面的第一区域形成焊线管脚，且在芯片的非有源面上形成绝缘层。
步骤S2:将芯片通过所述绝缘层贴装在所述载体的第一表面的第一区域。
步骤S3:将所述芯片有源面上的电极通过导电引线与所述焊线管脚电连接，然后进行塑封工艺，以形成覆盖所述芯片和所述焊线管脚的包封体。
步骤S4：将所述载体与包封体进行剥离，以将所述焊线管脚和所述绝缘层裸露在所述包封体的表面。
图2a～2d为依据本发明实施例的芯片封装方法的各个工艺步骤中所形成的剖面结构图。下面将结合图2a～2d来具体阐述本发明提供的芯片封装方法。
如图2a所示，步骤S1包括两个部分，一个是在载体1的上表面的第一区域形成焊线管脚2，另一个是在芯片3的非有源面形成绝缘层4，且这两个部分不限定先后顺序，可以同时形成，也可以先后形成。
载体1在本实施例中为金属基板，其形成的化学元素与焊线管脚2底部的化学元素不同族，从而可使其与焊线管脚2之间的粘附力小于预定值，以确保所述焊线管脚2在步骤S4中能够顺利的与载体1相剥离。
此外，为了确保步骤S4中绝缘层4能顺利的与载体1相剥离，在形成焊线管脚1之前，先至少将载体1的上表面的第二区域进行表面平坦化处理，使得所述第二区域成为光滑的表面。所述第二区域为载体1上表面的第一区域外的区域，在本实施例中，载体1上表面的第一区域位于第二区域的周围。由于需要在载体1上表面的第一区域形成焊线管脚，为了防止焊线管脚2移位，在形成焊线管脚2之前，需要将第一区域进行表面粗糙化处理，通过控制第一区域表面粗糙化的程度既能防止焊线管脚2的移位，又能保证在进行步骤S4时，焊线管脚2可与载体1相剥离。
将第一区域进行表面粗糙化处理的具体方法为：微蚀刻第一区域，以形成具有预定值深度的凹槽(图2a中未画出)，所述预定值为0微米至5微米之间的一个值，例如3微米。所述凹槽的深度决定第一区域表面粗糙化的程度，因此可以通过控制所述凹槽的深度来防止焊线管脚的移位，同时还能确保焊线管脚可与载体相剥离。
在形成所述凹槽后，在所述凹槽处电镀形成焊线管脚2。具体电镀步骤可以包括：先利用电镀掩模层，在凹槽处电镀一金属层作为电镀籽层，如金属镍层，然后再在电镀籽层上电镀厚的金属层，如金属铜层。为了保证在步骤S3中，焊线管脚可以更好的被塑封体锁定住，而不易脱落，在电镀形成焊线管脚2时，可使电镀层在掩模层表面适当的延伸。使得形成的焊线管脚2的底部(与载体1的上表面相接触的部分)截面积小于顶部截面积，可增加焊线管脚2与塑封体的接触面积，可在进行步骤S4时，焊线管脚不与塑封体相脱离，可确保封装的可靠性。
在本实施例中，在芯片3的非有源面形成绝缘层4的方法具体为：在芯片3的非有源面上涂覆绝缘胶，以形成绝缘层4。然后，将所述芯片3的非有源面通过所述绝缘胶粘贴在载体1上表面的第二区域上，如图2b所示。在本申请中，芯片3是指半导体裸芯片，而非有源面为与有源面相对的一面。
参考与2c所示，在完成步骤S2后，将芯片3的有源面上的电极通过导电引线5与焊线管脚2电连接，然后再进行塑封工艺，使塑封料覆盖在芯片3和焊线管脚2上，以形成包封体5。最后可采用机械剥离的方法，将载体1与包封体5进行分离，使得焊线管脚2与绝缘层4裸露在塑封体5的表面，如图2d所示。
将图2d所示的芯片封装结构贴装在PCB板上时，由于芯片3的非有源面上形成有绝缘层4，因而可保证芯片3的非有源面与PCB板之间的绝缘性，防止漏电，保证了封装结构的电气特性和可靠性。
由上可见，本发明提供的芯片封装方法中，在载体表面的第一区域上形成焊线管脚，并在芯片的非有源面形成绝缘层，然后将芯片通过所述绝缘层粘贴到载体表面的第二区域，在进行引线键合和塑封工艺后，将载体与塑封体相剥离，使得绝缘层和焊线管脚裸露在塑封体的表面。这种封装方法形成的封装结构在贴装到PCB板上时，可保证芯片的非有源面与PCB之间的绝缘性，保证了封装结构的电气特性。此外，所述封装方法，无需使用预先制作好的引线框架，而是在封装的过程中形成焊线管脚，有利于提高封装设计的灵活性。
依照本发明的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本发明的原理和实际应用，从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。

Claims (8)

1.一种芯片封装方法，包括：
在载体的第一表面的第一区域上形成焊线管脚，并在芯片的非有源面形成绝缘层，所述芯片的非有源面与所述芯片的有源面相对；
将所述芯片通过所述绝缘层贴装在所述载体的第一表面的第二区域上；
将所述芯片的有源面上的电极通过导电引线与所述焊线管脚电连接，然后进行塑封工艺，以形成覆盖所述芯片和焊线管脚的包封体；
将所述载体与所述包封体进行剥离，以将所述焊线管脚和绝缘层裸露在所述包封体的表面，
其中，在形成所述焊线管脚前，先至少将所述第二区域进行表面平坦化处理，以使得采用机械剥离方法将所述载体与所述包封体进行剥离时，所述绝缘层可与所述第二区域相剥离开，
且将采用所述芯片封装方法形成的芯片封装结构贴装在PCB上时，所述绝缘层用于保证所述芯片的非有源面与所述PCB板之间的绝缘性。
2.根据权利要求1所述的芯片封装方法，其特征在于，还包括：完成所述表面平坦化处理后，将所述第一区域进行表面粗糙化处理，以使得在所述第一区域上形成所述焊线管脚时，防止所述焊线管脚移位，且可使得在所述载体与所述包封体进行剥离时，所述焊线管脚可与所述第二区域相剥离开。
3.根据权利要求2所述芯片封装方法，其特征在于，蚀刻所述第一区域，形成具有预定深度的凹槽，以实现所述第一区域表面的粗糙化处理。
4.根据权利要求3所述芯片封装方法，其特征在于，在所述凹槽处电镀形成所述焊线管脚。
5.根据权利要求4所述的芯片封装方法，其特征在于，所述凹槽的深度介于0微米到5微米之间。
6.根据权利要求1所述的芯片封装方法，其特征在于，所述焊线管脚的底部与所述载体接触，所述焊线管脚的底部截面积小于顶部截面积。
7.根据权利要求1所述的芯片封装方法，其特征在于，在所述芯片的非有源面涂覆绝缘胶，以形成所述绝缘层，所述芯片的非有源面通过所述绝缘胶粘贴在所述第二区域的表面上。
8.一种根据如权利要求1至7中任意一项芯片封装方法所形成芯片封装结构。
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Families Citing this family (2)

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Publication number Priority date Publication date Assignee Title
CN109935577A (zh) * 2017-12-18 2019-06-25 无锡华润安盛科技有限公司 一种封装体
CN111106018B (zh) * 2018-10-26 2021-08-31 深圳市鼎华芯泰科技有限公司 一种封装过程中形成金属电极的方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1144016A (zh) * 1994-03-18 1997-02-26 日立化成工业株式会社 半导体组件的制造方法及半导体组件
CN101740407A (zh) * 2008-11-25 2010-06-16 三星电子株式会社 四方扁平无外引脚封装结构的封装工艺
CN103325753A (zh) * 2013-05-16 2013-09-25 华天科技（西安）有限公司 一种基于无框架csp封装背面植球塑封封装件及其制作工艺
CN103474406A (zh) * 2013-09-27 2013-12-25 华天科技（西安）有限公司 一种aaqfn框架产品无铜扁平封装件及其制作工艺

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028354A (en) * 1997-10-14 2000-02-22 Amkor Technology, Inc. Microelectronic device package having a heat sink structure for increasing the thermal conductivity of the package
JP3939429B2 (ja) * 1998-04-02 2007-07-04 沖電気工業株式会社 半導体装置
KR100335481B1 (ko) 1999-09-13 2002-05-04 김덕중 멀티 칩 패키지 구조의 전력소자
KR20050001159A (ko) 2003-06-27 2005-01-06 삼성전자주식회사 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법
JP2005353911A (ja) 2004-06-11 2005-12-22 Toshiba Corp 半導体装置
US8163604B2 (en) * 2005-10-13 2012-04-24 Stats Chippac Ltd. Integrated circuit package system using etched leadframe
US7662672B2 (en) * 2006-10-13 2010-02-16 Chipmos Technologies (Bermuda) Ltd. Manufacturing process of leadframe-based BGA packages
US7960997B2 (en) 2007-08-08 2011-06-14 Advanced Analogic Technologies, Inc. Cascode current sensor for discrete power semiconductor devices
JP2009302212A (ja) 2008-06-11 2009-12-24 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
TWI581384B (zh) 2009-12-07 2017-05-01 英特希爾美國公司 堆疊式電子電感封裝組件及其製造技術
TW201138047A (en) * 2010-04-26 2011-11-01 Advance Materials Corp Circuit board structure, packaging structure and method for making the same
JP2011258623A (ja) 2010-06-07 2011-12-22 Toshiba Corp パワー半導体システム
CN103283019A (zh) 2011-02-10 2013-09-04 松下电器产业株式会社 半导体装置
JP5919087B2 (ja) * 2012-05-10 2016-05-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
CN103021889A (zh) * 2012-12-17 2013-04-03 北京工业大学 一种再布线aaqfn封装器件的制造方法
CN103928353A (zh) * 2014-04-14 2014-07-16 矽力杰半导体技术(杭州)有限公司 无外引脚封装构造及其制造方法与导线框架
CN105097571B (zh) * 2015-06-11 2018-05-01 合肥矽迈微电子科技有限公司 芯片封装方法及封装组件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1144016A (zh) * 1994-03-18 1997-02-26 日立化成工业株式会社 半导体组件的制造方法及半导体组件
CN101740407A (zh) * 2008-11-25 2010-06-16 三星电子株式会社 四方扁平无外引脚封装结构的封装工艺
CN103325753A (zh) * 2013-05-16 2013-09-25 华天科技（西安）有限公司 一种基于无框架csp封装背面植球塑封封装件及其制作工艺
CN103474406A (zh) * 2013-09-27 2013-12-25 华天科技（西安）有限公司 一种aaqfn框架产品无铜扁平封装件及其制作工艺

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