CN105471411B - A kind of circuit system applied to pwm pulse shaping - Google Patents
A kind of circuit system applied to pwm pulse shaping Download PDFInfo
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Abstract
The present invention provides a kind of circuit system applied to pwm pulse shaping; it further include a power supply, an incoming level selecting module, two pwm pulse Shaping Modules, a pwm pulse dead time generator and cascade system selecting module, a logic fault protective module including two pwm pulse input terminals.Pwm pulse dead time generator and cascade system selecting module can choose two kinds of pwm pulse operating modes, comprising: and first, two-way input pwm pulse independently drives different loads；Second, the same load of two-way input pulse complementary drive.
Description
Technical field
The present invention relates to a kind of electronic information technology, especially a kind of circuit system applied to pwm pulse shaping.
Background technique
PWM (PulseWidth Modulation) control, i.e. pulse modulation technology, its thought are derived from the communication technology, base
Present principles are to carry out waveform required for equivalent acquisition by being modulated to a series of width of pulses and (contain shape and width
Value).PWM control technology is in field of power electronics extensive application, and to one that power electronic technique exerts far reaching influence
Item technology.IGBT, power MOSFET etc. provide for the constantly improve for all-controlling power electronics device of representative to PWM control technology
Powerful material base.Currently, in power conversion field, the application of PWM control technology is seen everywhere, as PWM rectifier,
PWM inverter etc., main circuit topological structure are all by all-controlling power electronics device (IGBT, power MOSFET etc.) mostly
The single-phase H bridge or Three-phase full-bridge circuit structure constituted, these wholly-controled devices generally pass through PWM pulse modulation technology and control it
On-off generates specific frequency, amplitude and the waveform of phase, and these all-controlling power electronics devices (IGBT, power MOSFET
Deng) general power is larger, it needs using dedicated driving circuit.The major requirement of this kind of driving circuit in addition to it is good electrically every
Small etc. outer from ability, driving capability and delay, another main function is exactly to pwm pulse progress Shape correction.City at present
The product that the INFINEON company of the CONCEPT company of the driving product such as Switzerland of mainstream and Germany releases on field is with higher
Integrated level, digitized degree is high, and defencive function is more complete, is widely used in wind energy and solar inverter, but these products
It is expensive, it is not easy in actual use according to practical application adjusting parameter and meets certain customizables of user and want
It asks；And the moderate product price that domestic manufacturer releases, but have a single function, reliability is lower, therefore the model limited its application
It encloses.
Summary of the invention
The purpose of the present invention is to provide a kind of circuit module using pwm pulse shaping, which has input
The spies such as impedance high, function expansibility is strong, electric parameter is adjustable, defencive function is reliable, at low cost, outer dimension is small, strong applicability
Point is highly suitable to be applied in the dedicated driving circuit of wholly-controled device (such as IGBT, power MOSFET).
A kind of circuit system applied to pwm pulse shaping, including two pwm pulse input terminals, further include a power supply, one
Incoming level selecting module, two pwm pulse Shaping Modules, a pwm pulse dead time generator and cascade system select mould
Block, a logic fault protective module.
Power supply is for providing operating voltage；Incoming level selecting module is used to select the multilevel type of input pulse, such as TTL
Or CMOS type, and the reference voltage of inverting input terminal is provided for pwm pulse shaping；Pwm pulse Shaping Module is used for input
Pwm pulse carries out Shape correction, filters out the ghost pulse in signal；Pwm pulse dead time generator and cascade system are selected
Select both of which of the module for selecting two-way pwm pulse to work；If for operating circuit event occurs for logic fault protective module
When barrier, block pwm pulse output；Two switching logic control modules, for protecting the pulse of output with the pulse of input respectively
Hold same phase；Described two pwm pulse operating modes include: first, and two-way input pwm pulse independently drives different loads；Second,
The same load of two-way input pulse complementary drive.
Compared with prior art, the present invention its remarkable advantage: (1) parameter easily adjust, function expansibility it is strong, choosing can be passed through
The open and close of switch is selected to select input pulse level for TTL or CMOS type, while the closure of selection switch can be passed through
Input pulse PWM1 and PWM2 are set with disconnecting and work in the independent single power switch tube mode of driving or both complementary drive
Two power switch tube modes on the same bridge arm allow user to pass through the parallel resistance adjusting pwm pulse on terminal in parallel
Dead time requires to meet the switching characteristic of actual use power switch tube；(2) at low cost, structure is simple, the circuit module
Using discrete element realize, but it is at low cost, component number is few, occupy PCB printing board surface product it is small, be easily installed use；
(3) reliable and stable, versatility is high, circuit of the present invention, which uses, uses standard interface, while having reliable defencive function, very suitable
It closes in the dedicated driving circuit applied to full-control type power device (such as IGBT, power MOSFET).
The present invention is described further with reference to the accompanying drawings of the specification.
Detailed description of the invention
Fig. 1 is invention's principle block diagram.
Fig. 2 is the schematic diagram of implementing circuit of the present invention.
Fig. 3 is implementing circuit of the present invention each point typical waveform schematic diagram in the 4th selection switch S4 closure.
Fig. 4 is implementing circuit of the present invention each point typical waveform schematic diagram when the 4th selection switch S4 is disconnected.
Specific embodiment
In conjunction with Fig. 1, a kind of circuit system applied to pwm pulse shaping, including two pwm pulse input terminals, further include
One power supply 6, an incoming level selecting module 1, two pwm pulse Shaping Modules 2-1,2-2, a pwm pulse dead time occur
Device and cascade system selecting module 3, a logic fault protective module 4, two switching logic control modules 5-1,5-2.
Power supply 6 is for providing operating voltage；Incoming level selecting module 1 is used to select the multilevel type of input pulse, such as
TTL or CMOS type, and the reference voltage of inverting input terminal is provided for pwm pulse shaping；Pwm pulse Shaping Module 2-1,2-2 are used
In carrying out Shape correction to the pwm pulse of input, the ghost pulse in signal is filtered out；Pwm pulse dead time generator with
The both of which that cascade system selecting module 3 is used to that two-way pwm pulse to be selected to work；If logic fault protective module 4 is used for work
When making circuit malfunctions, block pwm pulse output；Two switching logic control modules 5-1,5-2 are used to make the pulse of output
Same phase is kept with the pulse of input respectively；Described two pwm pulse operating modes include: first, and it is independent that two-way inputs pwm pulse
Drive different loads；Second, the same load of two-way input pulse complementary drive.
The duty ratio of input pulse PWM1 and PWM2 are 50% in Fig. 3 and Fig. 4, and the amplitude of pulse is VREF, it is assumed that two arteries and veins
Rushing phase difference is 180 °, and supply voltage VCC is 15V.
The driving load of the output pulse is power switch tube.
One provides the power supply VCC of operating voltage, and VCC chooses 15V in this example.
One TTL or CMOS incoming level selecting module, by power supply VCC, first choice switch S1, the 19th resistance R19,
20th resistance R20, transistor Q3, the 18th resistance R18, the 16th resistance R16, the 17th resistance R17, first capacitor C1 group
At can be used for selecting input pulse for Transistor-Transistor Logic level or CMOS level, and provide inverting input terminal to pwm pulse shaping circuit
Reference voltage；Wherein power supply VCC is connected to GND through first choice switch S1, the 19th resistance R19, the 20th resistance R20, crystal
The base stage of pipe Q3 is connected to the common end that the 19th resistance R19 is connect with the 20th resistance R20, and the emitter of transistor Q3 is connected to
The collector of GND, transistor Q3 are connected to power supply VCC through the 18th resistance R18 and the 16th resistance R16, the 17th resistance R17 with
The public common end for being connected to the 18th resistance R18 and the 16th resistance R16 connection of one of first capacitor C1 connection, the 17th
Resistance R17 connect with first capacitor C1 another public be connected to GND；
The specific work process and principle of TTL or CMOS incoming level selecting module: the 19th resistance R19, the 20th are taken
Resistance R20, the 18th resistance R18, the 16th resistance R16, the value relatable between the 17th resistance R17 are as follows:
When first choice switch S1 is opened, third transistor Q3 is not turned on since base voltage is zero, then the first electricity
Press the anti-phase input reference voltage V of comparator U1 and second voltage comparator U2REFNumerical approximation are as follows:
At this point, being provided with input pulse PWM1 and PWM2 is CMOS level.
When first choice switch S1 closure, the base voltage of third transistor Q3 are as follows:
Therefore third transistor Q3 conducting, then the anti-phase input of first voltage comparator U1 and second voltage comparator U2 are joined
Examine voltage VREFNumerical approximation are as follows:
At this point, being provided with input pulse PWM1 and PWM2 is Transistor-Transistor Logic level.
One pwm pulse shaping circuit mainly includes second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance
R5, the 6th resistance R6, first voltage comparator U1, second voltage comparator U2, the tenth resistance R10, eleventh resistor R11,
12 resistance R12, thirteenth resistor R13, the 14th resistance R14, power supply VCC, first choice switch S1, the 23rd resistance
R23, the 24th resistance R24, transistor Q1, the 21st resistance R21, the 22nd resistance R22, transistor Q2, it is main
Effect is the issuable wave distortion in transmission process for pwm signal, carries out Shape correction to the pwm pulse of input,
Filter out the ghost pulse in signal；Wherein input pulse PWM1 is connected to the same of first voltage comparator U1 by second resistance R2
Phase input terminal, while the non-inverting input terminal of first voltage comparator U1 is connected to first voltage through 3rd resistor R3, the 5th resistance R5
The output end of comparator U1, power supply VCC are connected to the output end of first voltage comparator U1 through the 6th resistance R6, and first voltage compares
The anti-phase input of device U1 is connected to the common end of the 18th resistance R18 and the 16th resistance R16 connection, one end of the 4th resistance R4
It is connected to the common end of 3rd resistor R3 and the 5th resistance R5 connection, another current collection for being connected to transistor Q1 of the 4th resistance R4
Pole, the emitter of transistor Q1 are connected to GND, and the base stage of transistor Q1 is connected to GND, while transistor through the 24th resistance R24
The base stage of Q1 is connected to power supply VCC through the 23rd resistance R23, first choice switch S1；Input pulse PWM2 is by the 14th electricity
Resistance R14 is connected to the non-inverting input terminal of second voltage comparator U2, while the non-inverting input terminal of second voltage comparator U2 is through the tenth
Three resistance R13, eleventh resistor R11 are connected to the output end of second voltage comparator U2, and power supply VCC is connected to through the tenth resistance R10
The anti-phase input of the output end of second voltage comparator U2, second voltage comparator U2 is connected to the 18th resistance R18 and the tenth
The common end of six resistance R16 connections, an end of twelfth resistor R12 is connected to thirteenth resistor R13 and connects with eleventh resistor R11
Common end, another collector for being connected to transistor Q2 of twelfth resistor R12, the emitter of transistor Q2 is connected to GND, brilliant
The base stage of body pipe Q2 is connected to GND through the 22nd resistance R22, while the base stage of transistor Q2 is through the 21st resistance R21, first
Selection switch S1 is connected to power supply VCC.
The specific work process and principle of pwm pulse shaping circuit: the 23rd resistance R23, the 24th resistance R24,
There is following relationship between 21st resistance R21, the 22nd resistance R22:
Second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 23rd resistance
Compared with R23, the 24th resistance R24, transistor Q1 constitute the voltage with positive feedback feature with first voltage comparator U1
Device 1；Tenth resistance R10, eleventh resistor R11, twelfth resistor R12, thirteenth resistor R13, the 14th resistance R14, second
11 resistance R21, the 22nd resistance R22, transistor Q2 and second voltage comparator U2 are constituted with positive feedback feature
Voltage comparator 2.Voltage comparator 1 and voltage comparator 2 plus the purpose of positive feedback are to generate same Schmidt trigger class
As voltage back diffirence, i.e., when changing to high level from low level by comparison voltage, voltage comparator trigging signal with higher,
And when changing to low level from high level by comparison voltage, voltage comparator has lower trigging signal.
It joined positive feedback just because of voltage comparator, therefore when changing slow by comparison voltage, in comparison voltage
Near The Critical Point will not generate oscillation, be also achieved that the distortion generated in transmission process to input pulse PWM1 or PWM1
Shape correction is carried out, its waveform is made to tend to standard PWM wave.
The depth of positive feedback determines that the size of voltage back diffirence, the size of voltage back diffirence determine comparison voltage critical point area
The selection of the size in domain, the size in comparison voltage critical point region is related with the input property of pwm pulse, if input PWM arteries and veins
Punching is Transistor-Transistor Logic level, then since the variation range of Transistor-Transistor Logic level is 0-5V, positive feedback depth should be made to take lesser value, therefore more electric
Lesser value should be arranged in pressure critical point region；If input pwm pulse is CMOS level, due to the variation range of CMOS level
For 0-15V, positive feedback depth should be made to take biggish value, therefore biggish value should be arranged in comparison voltage critical point region.In Fig. 2
In, the size of 2 positive feedback depth of voltage comparator 1 and voltage comparator is decided by the resistance value over the ground of E point and F point respectively.
(1) assume that input pulse PWM1 and PWM2 are Transistor-Transistor Logic level, i.e. when first choice switch S1 is closed, the first transistor
The base voltage of Q1 are as follows:
The base voltage of second transistor Q2 are as follows:
Therefore the first transistor Q1 and second transistor Q2 is both turned on, and E point is approximately the 4th resistance R4 to ground resistance
Resistance value, F point be approximately to ground resistance twelfth resistor R12 resistance value.The resistance value over the ground of E point and the resistance value over the ground of F point
Lesser value is taken, therefore voltage comparator 1 and 2 positive feedback depth of voltage comparator are smaller, corresponding comparison voltage critical point area
Domain is smaller, and being suitble to input pulse PWM1 and PWM2 is the characteristic of Transistor-Transistor Logic level.
(2) assume that input pulse PWM1 and PWM2 are CMOS level, i.e. when first choice switch S1 is disconnected, due to the first crystalline substance
The base voltage V of body pipe Q1B1With the base voltage V of second transistor Q2B2It is zero, therefore be not turned on.The electricity over the ground of E point
Resistance is approximately the sum of resistance value and the first transistor Q1 collection emitter-base bandgap grading off-resistances of the 4th resistance R4, since the first transistor Q1 collection is penetrated
Pole off-resistances can consider infinity, and first resistor R1, second resistance R2, tri- resistance of 3rd resistor R3 and the branch are simultaneously
Connection, therefore E point is approximately the sum of first resistor R1, second resistance R2,3rd resistor R3 tri- resistance series connection to ground resistance, then
As long as the sum of tri- first resistor R1, second resistance R2,3rd resistor R3 resistance take biggish value, voltage comparator 1 can be obtained
Larger positive feedback depth is obtained, corresponding comparison voltage critical point region is larger.Similarly, F point to ground resistance twelfth resistor R12's
The sum of resistance value and second transistor Q2 collection emitter-base bandgap grading off-resistances, since second transistor Q2 collection emitter-base bandgap grading off-resistances can consider nothing
It is poor big, and thirteenth resistor R13, the 14th resistance R14, tri- resistance of the 15th resistance R15 and the branch circuit parallel connection, therefore F point
Be approximately the sum of thirteenth resistor R13, the 14th resistance R14, the 15th resistance R15 tri- resistance series connection to ground resistance, then
As long as the sum of setting thirteenth resistor R13, the 14th resistance R14, the 15th tri- resistance of resistance R15 take biggish value, voltage
Comparator 2 can obtain larger positive feedback depth, and corresponding comparison voltage critical point tends to be larger.Voltage comparator 1 and voltage ratio
It is suitble to input pulse PWM1 and PWM2 to be the characteristic of CMOS level compared with the biggish positive feedback depth of device 2.
One pwm pulse dead time generator and cascade system selection circuit are mainly applied including power supply VCC, third close
Special NAND gate U3, the 7th resistance R7, the second capacitor R2, the second parallel connection terminal S2, the A pipe of the first diode combination D1, the 7th apply
The C of close spy's NAND gate U7, the 8th resistance R8, the 4th selection switch S4, the 8th Schmidt's NAND gate U8, the second diode combination D2
Pipe, third capacitor C3, the 9th resistance R9, third parallel connection terminal S3, the 4th Schmidt NAND gate U4, effect can mainly be set
It sets input pulse PWM1 or PWM2 and works in the independent single power switch tube mode of driving or both the same bridge arm of complementary drive
On two power switch tube modes, two power switch tubes both worked on one bridge arm of complementary drive the case where
Under, the dead time of every road pwm pulse can be respectively set, guarantee only one conducting of two switching tubes of synchronization；Wherein,
The pin 1 of third Schmidt trigger U3 is connected to the output end of first voltage comparator U1, and third Schmidt trigger U3's draws
Foot 2 is connected to GND through the second capacitor C2, while the pin 2 of third Schmidt trigger U3 is connected to power supply VCC through the 7th resistance R7,
Second parallel connection terminal S2 is connected in parallel on the both ends of the 7th resistance R7, in addition, the pin 2 of third Schmidt trigger U3 is connected to second group
The anode of the C pipe of diode D2 is closed, the cathode of the C pipe of the second diode combination D2 is connected to the output of the 8th Schmidt's NAND gate U8
End, the pin 3 of the 7th Schmidt's NAND gate U7 are connected to the pin 1 of third Schmidt's NAND gate U3, the 7th Schmidt's NAND gate U7
Pin 4 be connected to power supply VCC through the 8th resistance R8, while the pin 4 of the 7th Schmidt's NAND gate U7 be connected to the 8th Schmidt with
The pin 5 of NOT gate U8, in addition the pin 4 of the 7th Schmidt's NAND gate U7 is connected to GND through the 4th selection switch S4；8th Schmidt
The pin 6 of NAND gate U8 is connected to the output end of second voltage comparator U2, and the pin 8 of the 4th Schmidt's NAND gate U4 is connected to the 8th
The pin 7 of the pin 6 of Schmidt's NAND gate U8, the 4th Schmidt's NAND gate U4 is connected to GND through third capacitor C3, while the 4th applies
The pin 7 of close spy's NAND gate U4 is connected to power supply VCC through the 9th resistance R9, and third parallel connection terminal S3 is connected in parallel on the two of the 9th resistance R9
End, in addition the pin 7 of the 4th Schmidt's NAND gate U4 is connected to the anode of the A pipe of the first diode combination D1, the first two poles of combination
The cathode of the A pipe of pipe D1 is connected to the output end of the 7th Schmidt's NAND gate U7.
The specific work process and principle of pwm pulse dead time generator and cascade system selection circuit:
(1) when the 4th selection switch S4 is closed, then the pin 4 of the 7th Schmidt's NAND gate U7 and the 8th Schmidt with it is non-
The equal input low level of pin 5 of door U8, so the 7th Schmidt's NAND gate U7 and the 8th Schmidt's NAND gate U8 export high electricity
Flat, under normal circumstances, ERROR signal is low level, so the 9th schmitt inverter U9 exports high level.Supply voltage VCC
It is charged by the 7th resistance R7 to the second capacitor C2, after charging process, the voltage V at the second both ends capacitor C2C2It is approximately equal to
Supply voltage VCC, since the C pipe of the second diode combination D2 and the cathode voltage of D pipe are approximately equal to supply voltage VCC, because
The positive cut-off of C pipe and D pipe of this second diode combination D2, the second capacitor C2 can not pass through the C of the second diode combination D2
Pipe or D tube discharge, so the voltage V at the second both ends capacitor C2C2The amplitude of supply voltage VCC is maintained always；Similarly, power supply electricity
VCC is pressed to charge by the 9th resistance R9 to third capacitor C3, after charging process, the voltage V at the both ends third capacitor C3C3It is approximate
Equal to supply voltage VCC, since the A pipe of the first diode combination D1 and the cathode voltage of B pipe are approximately equal to supply voltage
VCC, therefore the A pipe of the first diode combination D1 and the positive cut-off of B pipe, third capacitor C3 can not pass through the first diode combination
The A of D1 is managed or B tube discharge, so the voltage V at the both ends third capacitor C3C3The amplitude of supply voltage VCC is maintained always.
According to the pin 7 for the pin 2 and the 4th Schmidt's NAND gate U4 that third Schmidt's NAND gate U3 is analyzed above
Equal input high level, thus between third Schmidt's NAND gate U3 and the output and incoming level of the 4th Schmidt's NAND gate U4 at
Inverted relationship, then respectively after the 5th schmitt inverter U5 and the 6th schmitt inverter U6, the pulse of final output with
The pulse of initial input, which is positively correlated, is.So input pulse PWM1 and PWM2 do not have in the 4th selection switch S4 closure
Dead time, therefore work in the independent single power switch tube mode of driving.The typical waveform timing diagram of each point is as shown in Figure 3.
(2) when the 4th selection switch S4 disconnection, then the pin 4 of the 7th Schmidt's NAND gate U7 and the 8th Schmidt with it is non-
The equal input high level of pin 5 of door U8, therefore, the pulse phase difference of the output of the 7th Schmidt's NAND gate U7 and the input of pin 3
For 180 °, i.e. inverted relationship；The similar pulse phase difference for having the output of the 8th Schmidt's NAND gate U8 to input with pin 6 is
180 °, i.e. inverted relationship.Phase relation between pulse PWM1, PWM2, U7_PWM_OUT, U8_PWM_OUT as shown in Figure 4.
Below with reference to the generation process of Fig. 4 analysis dead time:
Firstly, when PWM1 becomes high level from low level, PWM2 becomes low from high level by taking input pulse PWM1 as an example
Level, therefore U7_PWM_OUT becomes low level from high level, U8_PWM_OUT becomes high level from low level, and third is applied at this time
The 2nd pin U3_PIN2 of close spy's NAND gate U3 is still low level, due to the output U8_PWM_OUT of the 8th Schmidt's NAND gate U8
For high level, ERROR signal under normal circumstances is low level, then the output of the 9th schmitt inverter U9 is high level, institute
With the C pipe of the second diode combination D2 and the positive cut-off of D pipe, therefore supply voltage VCC can give by circuit VCC- > R7- > C2
Second capacitor C2 charging, when charging voltage reaches third Schmidt NAND gate U3 forward direction level turnover voltage threshold value ViT+, the
The pin 2 of three Schmidt's NAND gate U3 becomes high level from low level, at this time the output U3_PWM_ of third Schmidt NAND gate U3
OUT can become low level from high level.When PWM1 becomes low level from high level, PWM2 becomes high level from low level, because
This U7_PWM_OUT becomes high level from low level, and U8_PWM_OUT becomes low level from high level, due to the second capacitor at this time
Voltage on C2 is still approximately supply voltage VCC, so the C pipe moment forward conduction of the second diode combination D2, the second capacitor
Charge on C2 sparks through the C pipe of the second diode combination D2 to U8_PWM_OUT, since impedance loop is small, it is believed that
Discharge process moment completes.So the output U3_PWM_OUT of third Schmidt's NAND gate U3 can become low from high level in PWM1
High level is become from low level when level.When PWM1 becomes high level from low level next time, variation above can be repeated
Journey.U3_PWM_OUT low and high level after the 5th schmitt inverter U5 is covert, exports pulse PWM1_OUT.It is above by
During input pulse PWM1 to output pulse PWM1_OUT, the rising edge dead time control to input pulse PWM1 is realized
System, produces with rising edge dead time tdead1Output pulse PWM1_OUT.
The analysis of input pulse PWM2 is similar with process above, when PWM2 becomes high level from low level, PWM1 by
High level becomes low level, therefore U8_PWM_OUT becomes low level from high level, and U7_PWM_OUT becomes high electricity from low level
Flat, the 7th pin U4_PIN7 of the 4th Schmidt's NAND gate U4 is still low level at this time, due to the 7th Schmidt's NAND gate U7's
Output U7_PWM_OUT is high level, and ERROR signal under normal circumstances is low level, then the 9th schmitt inverter U9's is defeated
It is out high level, so the positive cut-off of A pipe and B pipe of the first diode combination D1, therefore supply voltage VCC can be by circuit
VCC- > R9- > C3 charges to third capacitor C3, when charging voltage reaches positive 4th Schmidt's NAND gate U4 forward direction level overturning
When voltage threshold ViT+, the pin 7 of the 4th Schmidt's NAND gate U4 becomes high level from low level, at this time the 4th Schmidt with it is non-
The output U4_PWM_OUT of door U4 can become low level from high level.When PWM2 becomes low level from high level, PWM1 is by low
Level becomes high level, therefore U8_PWM_OUT becomes high level from low level, and U7_PWM_OUT becomes low level from high level,
Since the voltage on third capacitor C3 at this time is still approximately supply voltage VCC, so the A pipe moment of the first diode combination D1 is just
To conducting, the charge on third capacitor C3 sparks through the A pipe of the first diode combination D1 to U7_PWM_OUT, due to circuit
Impedance is small, it is believed that discharge process moment completes.So the output U4_PWM_OUT of the 4th Schmidt's NAND gate U4 can be
High level is become from low level when PWM2 becomes low level from high level.When PWM2 becomes high level from low level next time,
It can repeat change procedure above.U4_PWM_OUT low and high level after the 6th schmitt inverter U6 is covert, exports pulse
PWM2_OUT.It is above by input pulse PWM2 to output pulse PWM2_OUT during, realize to input pulse
The rising edge Power MOSFET of PWM2 is produced with rising edge dead time tdead2Output pulse PWM2_OUT.
Dead time tdead1With dead time tdead2Calculation formula, be calculated according to following formula:
Wherein in this case, it is positive level turnover voltage threshold value ViT+ by E.
Can respectively by the second parallel connection terminal S2 and third parallel connection terminal S3 parallel resistance come the controlling dead error time
tdead1And tdead2Numerical value.
In addition, both input pulse PWM1 or PWM2 are worked in complementary drive is same when the 4th selection switch S4 is opened
Two power switch tube modes on a bridge arm prevent two power on the same bridge arm from opening at this point, PWM shaping circuit also has
Close the straight-through function of pipe, that is, when preventing input pulse PWM1 and PWM2 from occurring while being high level, two function on the same bridge arm
Rate switching tube simultaneously turns on.Basic principle:
When input pulse PWM1 and PWM2 occur while being high level, the output U7_ of the 7th Schmidt's NAND gate U7
The output U8_PWM_OUT of PWM_OUT and the 8th Schmidt's NAND gate U8 are low level, therefore the A of the first diode combination D1
The C of pipe and second group of diode D2 manage equal forward conduction, at this time third Schmidt NAND gate U3 pin 2 and the 4th Schmidt with it is non-
The current potential of door U4 pin 7 is pulled down to low level current potential, thus the output U3_PWM_OUT of third Schmidt's NAND gate U3 and
The output U4_PWM_OUT of 4th Schmidt's NAND gate U4 is locked into high level, then respectively through the 5th schmitt inverter
PWM1_OUT and PWM2_OUT is locked into low level after U5 and the 6th schmitt inverter U6, at this time two on the same bridge arm
A power switch tube is turned off, and realizing prevents straight-through function.
One logic fault protective module, mainly by the B pipe of the first diode combination D1, the D of the second diode combination D2
Pipe and the 9th schmitt inverter U9 are constituted, and effect is to provide Real-time hardware defencive function to operating circuit, work as operating circuit
When breaking down, level reversion, the inspection of logic fault protective module occur for the input end signal ERROR of the 9th schmitt inverter U9
Pwm pulse output is blocked immediately after measuring level reversion, guarantees that driven power switch tube is in an off state；Wherein,
The ERROR signal of the input terminal connection system of nine schmitt inverter U9, the output end connection the of the 9th schmitt inverter U9
The cathode of the B pipe of one diode combination D1, while the output end of the 9th schmitt inverter U9 connects the second diode combination D2
D pipe cathode, the anode of the B pipe of the first diode combination D1 connects the anode of the A pipe of the first diode combination D1, second group
Close the anode of the C pipe of the second diode combination D2 of anode connection of the D pipe of diode D2.
The specific work process and basic principle of logic fault protective module: under normal circumstances, ERROR signal is low electricity
Flat, output is high level after the 9th schmitt inverter U9, therefore the first diode combination D1 and B is managed and the second combination two
The positive cut-off of the D pipe of pole pipe D2；When system jam, ERROR signal is high level by low level jump, therefore is passed through again
Output is low level after crossing the 9th schmitt inverter U9, at this time the first diode combination D1 and B pipe and the second diode combination
The D of D2 manages equal forward conduction, therefore the current potential of third Schmidt NAND gate U3 pin 2 and the 4th Schmidt NAND gate U4 pin 7
Be pulled down to low level current potential, then no matter how the level of input pulse PWM1 and PWM2 change, third Schmidt with it is non-
The output U4_PWM_OUT of the output U3_PWM_OUT and the 4th Schmidt's NAND gate U4 of door U3 are locked into high level, then divide
PWM1_OUT and PWM2_OUT is not locked into low electricity after the 5th schmitt inverter U5 and the 6th schmitt inverter U6
Flat, in the case of realization system jam to output pwm signal block.
One switching logic control circuit mainly includes the 5th schmitt inverter U5 and the 6th schmitt inverter U6,
Main function is to make the pulse PWM1_OUT and PWM2_OUT of output keep same with the pulse PWM1 and PWM2 of input respectively mutually to open
The conducting that pass control logic, i.e. high level part all correspond to institute's driving power switching tube, all corresponding the driven function of low level part
The shutdown of rate switching tube；The wherein output end of the input terminal connection third Schmidt NAND gate U3 of the 5th schmitt inverter U5,
The output end of 5th schmitt inverter U5 exports pulse PWM1_OUT；The input terminal connection the 4th of 6th schmitt inverter U6
The output end of the output end of Schmidt's NAND gate U4, the 6th schmitt inverter U6 exports pulse PWM2_OUT.
The reforming process of pwm pulse is as follows: the pulse PWM1 and PWM2 of input pass through the pull down resistor of respective route respectively:
Then first resistor R1 and the 15th resistance R15 enters pwm pulse by second resistance R2 and the 14th resistance R14 respectively
Shaping circuit, this partial circuit is the positive feedback system with schmidt trigger and voltage comparing function, effectively to pwm pulse
The distortion generated in transmission process carries out Shape correction, while this partial circuit passes through the anti-of first voltage comparator U1 respectively
Phase input terminal connects TTL or CMOS incoming level selecting module with the inverting input terminal of second voltage comparator U2；In TTL or
In CMOS incoming level selecting module, if closure first choice switch S1, the pulse that input is arranged is Transistor-Transistor Logic level；If
Open first choice switch S1, then be arranged input pulse be CMOS level, the module produce first voltage comparator U1 with
The anti-phase input reference voltage V of second voltage comparator U2REF；Subsequently respectively by the electricity of first voltage comparator U1 and second
The output end of pressure comparator U2 enters pwm pulse dead time generator and cascade system selection circuit, in the partial circuit,
If opening the 4th selection switch S4, input pulse PWM1 or PWM2 are set and worked on the two same bridge arm of complementary drive
Two power switch tube modes the rising edge dead time of pulse PWM1 and PWM2 can be respectively set, extremely in this mode
The size of area's time can be realized respectively by adjusting resistance value in parallel on the second parallel connection terminal S2 and third parallel connection terminal S3；
If the 4th selection switch S4 of closure, input pulse PWM1 or PWM2 are set and work in the independent single power switch pipe die of driving
Formula, in this mode, pulse PWM1 and PWM2 individually export, and do not have rising edge dead time.Finally controlled by switching logic
Circuit, i.e. the 5th schmitt inverter U5 and the 6th schmitt inverter U6 export pulse PWM1_OUT and PWM2_OUT.Logic
The fault-signal ERROR of failure protection module real-time monitoring system, when detecting ERROR signal by low get higher, the module is vertical
Pulse PWM1_OUT and PWM2_OUT pressure are pulled down to low level, guarantee driven power by the output for blocking pwm pulse
Switching tube is in an off state.
Claims (1)
1. a kind of circuit system applied to pwm pulse shaping, including two pwm pulse input terminals characterized by comprising
One power supply, for providing operating voltage,
One incoming level selecting module provides anti-phase input for selecting the multilevel type of input pulse, and for pwm pulse shaping
The reference voltage at end,
Two pwm pulse Shaping Modules filter out the false arteries and veins in signal for carrying out Shape correction to the pwm pulse of input
Punching,
One pwm pulse dead time generator and cascade system selecting module, two kinds of moulds for selecting two-way pwm pulse to work
Formula,
One logic fault protective module, if break down for operating circuit, block pwm pulse output, two switching logics
Control module, for making the pulse of output keep same phase with the pulse of input respectively；Described two pwm pulse operating mode packets
It includes: first, two-way input pwm pulse independently drives different loads；Second, the same load of two-way input pulse complementary drive；
The dead time of every road pwm pulse is respectively set in second of pwm pulse operating mode, guarantees synchronization two
Only one conducting of switching tube；
In two pwm pulse input terminals difference pull down resistors in parallel；
Incoming level selecting module includes power supply (VCC), first choice switch (S1), the 19th resistance (R19), the 20th resistance
(R20), transistor (Q3), the 18th resistance (R18), the 16th resistance (R16), the 17th resistance (R17), first capacitor
(C1), wherein
Power supply (VCC) is connected to GND through first choice switch (S1), the 19th resistance (R19), the 20th resistance (R20),
The base stage of transistor (Q3) is connected to the common end that the 19th resistance (R19) is connect with the 20th resistance (R20),
The emitter of transistor (Q3) is connected to GND,
The collector of transistor (Q3) is connected to power supply (VCC) through the 18th resistance (R18) and the 16th resistance (R16),
Connect with first capacitor (C1) one of 17th resistance (R17) is public to be connected to the 18th resistance (R18) and the 16th
The common end of resistance (R16) connection,
17th resistance (R17) connect with first capacitor (C1) another public be connected to GND.
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| CN1917369A (en) * | 2006-08-30 | 2007-02-21 | 广州金升阳科技有限公司 | IGBT drive, and process method for driving signal |
| CN102522971A (en) * | 2012-01-06 | 2012-06-27 | 河南华南医电科技有限公司 | Novel power field effect transistor drive |
| CN103516213A (en) * | 2013-09-09 | 2014-01-15 | 深圳市佳华利道新技术开发有限公司 | Bidirectional dc-dc converter circuit control system and hybrid power motor vehicle |
| CN205105181U (en) * | 2015-11-12 | 2016-03-23 | 中国船舶重工集团公司第七一六研究所 | Circuit system for PWM pulse shaping |
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| US9906147B2 (en) * | 2011-09-14 | 2018-02-27 | Futurewei Technologies, Inc. | Adaptive dead time control apparatus and method for switching power converters |
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| CN1917369A (en) * | 2006-08-30 | 2007-02-21 | 广州金升阳科技有限公司 | IGBT drive, and process method for driving signal |
| CN102522971A (en) * | 2012-01-06 | 2012-06-27 | 河南华南医电科技有限公司 | Novel power field effect transistor drive |
| CN103516213A (en) * | 2013-09-09 | 2014-01-15 | 深圳市佳华利道新技术开发有限公司 | Bidirectional dc-dc converter circuit control system and hybrid power motor vehicle |
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