CN105448861B - 芯片、其制作方法及层叠芯片的制作方法 - Google Patents

芯片、其制作方法及层叠芯片的制作方法 Download PDF

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CN105448861B
CN105448861B CN201410308869.2A CN201410308869A CN105448861B CN 105448861 B CN105448861 B CN 105448861B CN 201410308869 A CN201410308869 A CN 201410308869A CN 105448861 B CN105448861 B CN 105448861B
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chip
metal layer
medium area
layer
dielectric layer
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CN105448861A (zh
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陈福成
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to US14/717,606 priority patent/US9293430B2/en
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Abstract

本申请公开了一种芯片、其制作方法及层叠芯片的制作方法。其中，该芯片包括：芯片基板；介质层，设置于芯片基板上，介质层包括第一介质区和环绕在第一介质区外周的第二介质区，且第一介质区的上表面低于第二介质区的上表面；金属层，设置于第一介质区并贯穿介质层，且金属层与芯片基板连接。在上述芯片中通过降低围绕在金属层外周的第一介质区相对于金属层的高度，使得暴露在第一介质层外面的金属层的体积增加。将该芯片与其它芯片进行键合过程中，在键合压力不变的情况下金属层内部的应力会减小，使得金属层的延展程度得以减小，进而提高层叠芯片的可靠性。

Description

芯片、其制作方法及层叠芯片的制作方法
技术领域
本申请涉及半导体集成电路制作技术领域，具体而言，涉及一种芯片、其制作方法及层叠芯片的制作方法。
背景技术
随着半导体集成电路的集成度越来越高，芯片中晶体管的集成度逐渐达到上限。层叠芯片(3DIC)技术通过键合工艺实现多个芯片之间的垂直互连，增加了芯片的空间，提高了晶体管的集成度，同时还能提高集成电路的工作速度，降低集成电路的功耗。目前，层叠芯片技术已成为集成电路设计的重要方向之一。
在现有层叠芯片的制作过程中，通常先制作形成各个芯片。如图1所示，所形成的芯片包括芯片基板10′，设置于芯片基板10′上的介质层20′，以及设置于介质层20′中，并电连接芯片基板10′与外部电结构的金属层30′，介质层20′的上表面低于金属层30′的上表面。然后通过热压键合工艺将各个芯片键合在一起，形成层叠芯片。
上述对芯片进行热压键合的过程中，在键合压力的作用下金属层会发生延展，导致相邻的金属层之间产生连接，甚至导致芯片发生短路(如图2所示)等。随着层叠芯片技术的不断发展，芯片中金属层的密度越来越高，金属层之间的距离也越来越小，在这种情况下，金属层的延展现象将导致相邻金属层之间更容易产生连接。
技术人员尝试通过减小金属层的尺寸，以增加金属层之间的距离，进而避免相邻金属层之间产生连接。然而随着金属层尺寸的减小，芯片键合工艺中金属层的对准精度会降低，进而导致层叠芯片的成品率降低。
发明内容
本申请旨在提供一种芯片、其制作方法及层叠芯片的制作方法，以解决现有层叠芯片的制作过程中因金属延展所导致的相邻金属层之间易产生连接的问题，进而提高层叠芯片的可靠性。
为了实现上述目的，根据本申请的一个方面，提供了一种芯片，该芯片包括：芯片基板；介质层，设置于芯片基板上，介质层包括第一介质区和环绕在第一介质区外周的第二介质区，且第一介质区的上表面低于第二介质区的上表面；金属层，设置于第一介质区并贯穿介质层，且金属层与芯片基板连接。
进一步地，第一介质区的高度为第二介质区的高度的1/3～2/3。
进一步地，第一介质区相对于金属层一侧边的宽度为金属层的同方向宽度的1/10～1/2。
进一步地，第一介质区和第二介质区的材料选自SiO2、SiOC或Si3N4中的任一种；金属层的材料选自Cu或Sn。
本申请还提供了一种芯片的制作方法，包括以下步骤：提供芯片基板，在芯片基板上形成介质层，介质层包括第一介质区和环绕在第一介质区外周的第二介质区；在第一介质区中形成贯穿介质层并与芯片基板连接的金属层；刻蚀介质层使第一介质区的上表面低于第二介质区的上表面。
进一步地，刻蚀介质层的步骤包括：形成连续覆盖介质层和金属层的光刻胶层；光刻光刻胶层中相应于金属层的位置，形成宽度大于金属层的宽度的开口；沿开口刻蚀介质层，以使第一介质区的上表面低于第二介质区的上表面；去除剩余的光刻胶层。
进一步地，在刻蚀介质层的步骤中，刻蚀介质层以使第一介质区的高度为第二介质区的高度的1/3～2/3。
进一步地，在去除剩余的光刻胶层的步骤之前，清洗金属层，以去除金属层表面上的氧化物。
进一步地，介质层的材料选自SiO2、SiOC或Si3N4的任一种；金属层的材料选自Cu、Sn。
本申请还提供了一种层叠芯片的制作方法，该制作方法包括：提供第一芯片和第二芯片，且第一芯片和第二芯片中至少一个为本申请上述的芯片；以及将第一芯片的金属层和第二芯片的金属层进行键合连接。
进一步地，将第一芯片的金属层和第二芯片的金属层进行键合连接的步骤中，同时将第一芯片的介质层和第二芯片的介质层进行键合连接。
进一步地，在将第一芯片的金属层和第二芯片的金属层进行键合连接的步骤之后，对第一芯片和第一芯片进行退火处理。
应用本申请的技术方案，在该芯片中将介质层分为第一介质区和第二介质区，通过降低围绕在金属层外周的第一介质区相对于金属层和第二介质区的高度，使得暴露在第一介质层外面的金属层的体积增加(暴露在第一介质层外面的金属层的垂直于芯片基板表面的截面积S也增加)。因此，将该芯片与其它芯片进行键合形成层叠芯片的过程中，在键合压力(F)不变的情况下金属层内部的应力会减小(应力σ与F/S成正比)，使得金属层的延展程度得以减小，进而避免相邻金属层之间产生连接，提高层叠芯片的可靠性。同时，在键合的过程中向外延展的金属层会覆盖在第一介质区的表面上，并且受到第二介质区侧壁的阻挡作用力，进而阻止金属层的延展，避免相邻金属层之间产生连接，提高层叠芯片的可靠性。
附图说明
构成本申请的一部分的说明书附图用来提供对本申请的进一步理解，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1示出了现有芯片的剖面结构示意图；
图2示出了现有层叠芯片的SEM照片；
图3示出了根据本申请实施方式所提供的芯片的剖面结构示意图；
图4示出了根据本申请实施方式所提供的芯片的制作方法的流程示意图；
图5示出了在本申请提供的芯片的制作方法中，提供芯片基板，在芯片基板上形成介质层，介质层包括第一介质区和环绕在第一介质区外周的第二介质区后的基体的剖面结构示意图；
图6示出了在图5所示的第一介质区中形成贯穿介质层并与芯片基板连接的金属层后的基体的剖面结构示意图；
图7示出了刻蚀图6所示的刻蚀介质层使第一介质区的上表面低于第二介质区的上表面后的基体的剖面结构示意图；
图7-1示出了形成连续覆盖图5所示的介质层和金属层的光刻胶层；
图7-2示出了光刻图7-1所示的光刻胶层中相应于金属层的位置，形成宽度大于金属层的宽度的开口；以及
图7-3示出了沿图7-2所示的开口刻蚀介质层，以使第一介质区的上表面低于第二介质区的上表面。
具体实施方式
需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
需要注意的是，这里所使用的术语仅是为了描述具体实施方式，而非意图限制根据本申请的示例性实施方式。如在这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式，此外，还应当理解的是，当在本说明书中使用属于“包含”和/或“包括”时，其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
为了便于描述，在这里可以使用空间相对术语，如“在……之上”、“在……上方”、“在……上表面”、“上面的”等，用来描述如在图中所示的一个器件或特征与其他器件或特征的空间位置关系。应当理解的是，空间相对术语旨在包含除了器件在图中所描述的方位之外的在使用或操作中的不同方位。例如，如果附图中的器件被倒置，则描述为“在其他器件或构造上方”或“在其他器件或构造之上”的器件之后将被定位为“在其他器件或构造下方”或“在其他器件或构造之下”。因而，示例性术语“在……上方”可以包括“在……上方”和“在……下方”两种方位。该器件也可以其他不同方式定位(旋转90度或处于其他方位)，并且对这里所使用的空间相对描述作出相应解释。
正如背景技术中所介绍的，现有层叠芯片的制作过程中因金属延展所导致的相邻金属层之间易产生连接，并导致芯片发生短路的问题。本申请的申请人针对上述问题进行研究，提出了一种芯片、其制作方法及层叠芯片的制作方法。如图3所示，该芯片包括：芯片基板10；介质层20，设置于芯片基板10上，介质层20包括第一介质区21和环绕在第一介质区21外周的第二介质区22，且第一介质区21的上表面低于第二介质区22的上表面；金属层30，设置于第一介质区21并贯穿介质层20，且金属层30与芯片基板10连接。
在本申请上述的芯片中，第一介质区21的上表面低于第二介质区22的上表面，使得暴露在第一介质区21外面的金属层30的体积增加(暴露在第一介质层外面的金属层的垂直于芯片基板表面的截面积S也增加)。因此，将该芯片与其它芯片进行键合形成层叠芯片的过程中，在键合压力F不变的情况下金属层30内部的应力σ会减小(应力σ与F/S成正比)，使得金属层30的延展程度得以减小，进而避免相邻金属层30之间产生连接，提高层叠芯片的可靠性。同时，在键合的过程中向外延展的金属层30会覆盖在第一介质区21的表面上，并且受到第二介质区22侧壁的阻挡作用力，进而阻止金属层30的延展，避免相邻金属层30之间产生连接，提高芯片的可靠性。
在本申请上述的芯片中，上述键合时金属层30的延展程度与第一介质区21的高度有关，本领域的技术人员可以根据实际工艺需求设置第一介质区21的高度。优选地，第一介质区21的高度为第二介质区22的高度的1/3～2/3。假若第一介质区21的高度大于第二介质区22的高度的2/3，那么暴露在第一介质区21外面的金属层30的截面积S较小，使得金属层30内部的应力较大，金属层30的延展程度也较大，导致避免相邻金属层30之间产生连接的效果变差；假若第一介质区21的高度小于第二介质区22的高度的1/3，那么金属层30与第一介质区21之间的结合强度减小，可能会造成金属层30的松动，进而降低芯片的可靠性。
在本申请上述的芯片中，对上述金属层30进行键合时的工艺窗口与第一介质区21的宽度有关，本领域的技术人员可以根据实际工艺需求设置第一介质区21的宽度。优选地，该第一介质区21环绕在金属层30的外周，具有环形结构。其相对于金属层30一侧边的宽度(沿垂直于金属层30侧壁方向的一侧宽度)为金属层30同方向宽度的1/10～1/2。假若第一介质区21的一侧宽度小于金属层30的宽度的1/10，那么键合时向外延展的金属层30会对第二介质区22的侧壁产生较大的作用力，可能会使得第二介质区22受到损坏，进而降低芯片的可靠性；假若第一介质区21的一侧宽度大于金属层30的宽度的1/2，会使得同一芯片上布置的金属层30的数量减少，不利于提高半导体器件的集成度。
在本申请上述的芯片中，本领域的技术人员可以根据实际工艺需求设置介质层20和金属层30的种类。优选地，第一介质区21和第二介质区22的材料选自SiO2、SiOC或Si3N4中的任一种；金属层30的材料选自Cu、Sn。
同时，本申请还提供了一种芯片的制作方法。如图4所示，该制作方法包括以下步骤：提供芯片基板，在芯片基板上形成介质层，介质层包括第一介质区和环绕在第一介质区外周的第二介质区；在第一介质区中形成贯穿介质层并与芯片基板连接的金属层；刻蚀介质层使第一介质区的上表面低于第二介质区的上表面。
下面将更详细地描述根据本申请的示例性实施方式。然而，这些示例性实施方式可以由多种不同的形式来实施，并且不应当被解释为只限于这里所阐述的实施方式。应当理解的是，提供这些实施方式是为了使得本申请的公开彻底且完整，并且将这些示例性实施方式的构思充分传达给本领域普通技术人员，在附图中，为了清楚起见，扩大了层和区域的厚度，并且使用相同的附图标记表示相同的器件，因而将省略对它们的描述。
图5至图7示出了本申请提供的芯片的制作方法中，经过各个步骤后得到的基体的剖面结构示意图。下面将结合图5至图7，进一步说明本申请所提供的芯片的制作方法。
首先，提供芯片基板10，在芯片基板10上形成介质层20，介质层20包括第一介质区21和环绕在第一介质区21外周的第二介质区22，进而形成如图5所示的基体结构。其中，介质层20为绝缘材料，用于将后续形成的金属层隔离开。优选地，介质层的材料选自SiO2、SiOC或Si3N4的任一种。
形成上述介质层的工艺包括但不限于采用化学气相沉积、溅射和蒸镀。在本申请的一种可选实施方式中，采用化学气相沉积工艺在芯片基板10上形成SiO2，其工艺条件为：以四甲基硅烷和氧气为反应气体，四甲基硅烷的流量为1000～3000sccm，氧气的的流量为2000～5000sccm，基板沉积温度为500～800℃，沉积时间为1～3min。
上述芯片基板10上至少形成一种器件，比如晶体管、二极管、隔离沟槽和互连层等，本领域的技术人员可以根据实际工艺需求选择器件的类型及结构。形成上述器件的方法为本领域现有技术，在此不再赘述。
完成提供芯片基板10，在芯片基板10上形成介质层20，介质层20包括第一介质区21和环绕在第一介质区21外周的第二介质区22的步骤之后，在第一介质区21中形成贯穿介质层20并与芯片基板10连接的金属层30，进而形成如图6所述的基体结构。
在一种优选实施方式中，形成上述金属层30的步骤包括：在介质层20上形成图案化光刻胶层；沿图案化光刻胶层刻蚀在第一介质区21中介质层20至暴露出芯片基板10，在介质层20中形成通孔；填充通孔形成金属层30。上述金属层30为键合工艺常见的金属，优选为Cu或Sn。在形成上述金属层30后，还可以对金属层进行化学机械抛光(CMP)，上述CMP的具体工艺参数可以根据现有技术进行设定。需要注意的是，金属层30与芯片基板10中的器件相连。
在上述形成金属层30的步骤中，在通孔中形成金属层30之前，在通孔的底部和侧壁上形成阻挡层，以防止金属层30中的金属原子向介质层20扩散，同时增加金属层30与介质层20之间的粘合力；然后在阻挡层上形成金属种子层。上述阻挡层可以为TaN层、Ta层、或者TaN层和Ta层的叠层，上述金属种子层的材料为Cu。形成上述阻挡层和金属种子层的工艺可以为化学气相沉积或溅射。
在上述形成金属层30的步骤中，在形成金属层30后，还可以进一步刻蚀剩余的介质层20，以使位于介质层20表面以上金属层30的体积足够大，并保证后续金属层30充分键合。上述回蚀介质层20的工艺可以为湿法刻蚀，刻蚀液包括但不限于采用HF溶液。在本申请的一种可选实施方式中，采用质量分数为30％～50％的HF溶液进行上述回蚀时，回蚀的温度为25～50℃，时间为30～120秒。
完成在第一介质区21中形成贯穿介质层20并与芯片基板10连接的金属层30的步骤之后，刻蚀介质层20使第一介质区21的上表面低于第二介质区22的上表面，进而形成如图7所示的基体结构。在一种优选实施方式中，该步骤包括：形成连续覆盖介质层20和金属层30的光刻胶层40，进而形成如图7-1所示的基体结构；光刻光刻胶层40中相应于金属层30的位置，形成宽度大于金属层30的宽度的开口41，进而形成如图7-2所示的基体结构；沿开口41刻蚀介质层20，以使第一介质区21的上表面低于第二介质区22的上表面，进而形成如图7-3所示的基体结构；去除剩余的光刻胶层40，进而形成如图7所示的基体结构。
形成光刻胶层40的工艺可以包括但不限于采用旋涂或沉积，上述工艺为本领域现有技术，在此不再赘述。需要注意的是，在上述步骤中还可以在光刻胶层40的上方或下方形成抗反射涂层，以提高光刻图形的准确性。上述光刻光刻胶层40的步骤包括曝光和显影工艺，其具体工艺为本领域现有技术，在此不再赘述。
上述刻蚀介质层20的工艺可以采用湿法刻蚀，其中刻蚀液包括但不限于采用HF溶液。在本申请的一种可选实施方式中，采用质量分数为30％～50％的HF溶液进行上述刻蚀时，刻蚀的温度为25～50℃，时间为60～300秒。
优选地，在刻蚀介质层20的步骤中，刻蚀介质层20以使第一介质区21的高度为第二介质区22的高度的1/3～2/3。假若刻蚀去除的第一介质区21的高度小于第二介质区22的高度的1/3，那么暴露在形成的第一介质区21外面的金属层30的截面积S较小，使得金属层30内部的应力较大，金属层30的延展程度也较大，导致避免相邻金属层30之间产生连接的效果变差；假若刻蚀去除的第一介质区21的高度大于第二介质区22的高度的2/3，那么金属层30与形成的第一介质区21之间的结合强度减小，会造成金属层30的松动，进而降低芯片的可靠性。
上述去除剩余的光刻胶层40可以为湿法刻蚀工艺或灰化工艺。在本申请的一种可选实施方式中，采用氧等离子灰化工艺去除剩余的光刻胶层40，其工艺条件为：以O2和N2H2为反应气体，O2的流量为2000～5000sccm，N2H2的流量为200～400sccm，反应室压力为500～2000mT，激发功率为600～1000W，处理时间为30～90s。
在上述去除光刻胶层40的步骤之前，还可以清洗金属层30，以去除金属层30表面上的氧化物。清洗试剂包括但不限于采用SPM或SC1溶液。在本申请的一种可选实施方式中，采用SC1溶液进行上述清洗，其工艺条件为：SC1溶液中H2O2、NH4OH和H2O的体积比为1：2～10：20～50，SC1溶液的流量为1～3L/min，清洗的温度为20～45℃，时间为30～100秒。
本申请还提供了一种层叠芯片的制作方法，该制作方法包括：提供第一芯片和第二芯片，且第一芯片和第二芯片中的任一个或两个为本申请所提供的芯片；以及将第一芯片的金属层和第二芯片的金属层进行键合连接。按照上述方法得到的层叠芯片中金属层的延展程度得以减小，进而避免相邻金属层之间产生连接，提高层叠芯片的可靠性。
在本申请上述的层叠芯片的制作方法中，将第一芯片的金属层和第二芯片的金属层进行键合的同时，还可以将第一芯片的介质层和第二芯片的介质层进行键合连接。经过上述步骤后，第一芯片的介质层和第二芯片的介质层形成良好的接触界面，进而阻止金属层的延展，避免相邻金属层之间产生连接，提高层叠芯片的可靠性。
优选地，上述键合连接第一芯片的金属层和第二芯片的金属层，以及第一芯片的介质层和第二芯片的介质层的工艺为热压键合。在本申请的一种可选实施方式中，热压键合的温度为300～500℃，压力为1～5KN，时间为5～20min。
在本申请上述的层叠芯片的制作方法中，在上述键合连接的步骤之前，还可以清洗第一芯片和第二芯片的表面，以去除表面的缺陷，比如残留有机物等。在本申请的一种可选实施方式中，清洗试剂包括但不限于采用SPM或SC1溶液，清洗的方法可以包括但不限于采用旋转喷淋法或超声清洗法。在上述键合连接的步骤之后，还可以对第一芯片和第二芯片进行退火处理，以去除第一芯片和第二芯片中的缺陷，比如位错、晶格畸变或空穴等。上述工艺为本领域现有技术，在此不再赘述。
从以上的描述中，可以看出，本申请上述的实施例实现了如下技术效果：
(1)在本申请上述的芯片中第一介质区的上表面低于第二介质区的上表面，使得暴露在第一介质区外面的金属层的体积增加(垂直于芯片基板表面的截面积S也增加)。因此，将该芯片与其它芯片进行键合形成层叠芯片的过程中，在键合压力F不变的情况下金属层内部的应力σ会减小(应力σ与F/S成正比)，使得金属层的延展程度得以减小，进而避免相邻金属层之间产生连接，提高层叠芯片的可靠性。
(2)同时在键合的过程中向外延展的金属层会覆盖在第一介质区的表面上，并且受到第二介质区侧壁的阻挡作用力，进而阻止金属层的延展，避免相邻金属层之间产生连接，提高芯片的可靠性。
以上所述仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (8)

1.一种芯片，其特征在于，所述芯片包括：
芯片基板；
介质层，设置于所述芯片基板上，所述介质层包括第一介质区和环绕在所述第一介质区外周的第二介质区，且所述第一介质区的上表面低于所述第二介质区的上表面；
金属层，设置于所述第一介质区并贯穿所述介质层，且所述金属层与所述芯片基板连接；
其中所述第一介质区的高度为所述第二介质区的高度的1/3～2/3，所述第一介质区相对于所述金属层一侧边的宽度为所述金属层的同方向宽度的1/10～1/2。
2.根据权利要求1所述的芯片，其特征在于，所述第一介质区和第二介质区的材料选自SiO2、SiOC或Si3N4中的任一种；所述金属层的材料选自Cu或Sn。
3.一种芯片的制作方法，其特征在于，包括以下步骤：
提供芯片基板，在所述芯片基板上形成介质层，所述介质层包括第一介质区和环绕在所述第一介质区外周的第二介质区；
在所述第一介质区中形成贯穿所述介质层并与所述芯片基板连接的金属层；
刻蚀所述介质层使所述第一介质区的上表面低于所述第二介质区的上表面；
刻蚀所述介质层的步骤包括：
形成连续覆盖所述介质层和所述金属层的光刻胶层；
光刻所述光刻胶层中相应于所述金属层的位置，形成宽度大于所述金属层的宽度的开口；
沿所述开口刻蚀所述介质层，以使所述第一介质区的上表面低于所述第二介质区的上表面，并使所述第一介质区的高度为所述第二介质区的高度的1/3～2/3，且所述第一介质区相对于所述金属层一侧边的宽度为所述金属层的同方向宽度的1/10～1/2；
去除剩余的所述光刻胶层。
4.根据权利要求3所述的制作方法，其特征在于，在去除剩余的所述光刻胶层的步骤之前，清洗所述金属层，以去除所述金属层表面上的氧化物。
5.根据权利要求3或4所述的制作方法，其特征在于，所述介质层的材料选自SiO2、SiOC或Si3N4的任一种；所述金属层的材料选自Cu或Sn。
6.一种层叠芯片的制作方法，其特征在于，该制作方法包括：
提供第一芯片和第二芯片，且所述第一芯片和第二芯片中至少一个为权利要求1或2所述的芯片；以及
将所述第一芯片的金属层和第二芯片的金属层进行键合连接。
7.根据权利要求6所述的制作方法，其特征在于，将所述第一芯片的金属层和第二芯片的金属层进行键合连接的步骤中，同时将所述第一芯片的介质层和第二芯片的介质层进行键合连接。
8.根据权利要求6或7所述的制作方法，其特征在于，在将所述第一芯片的金属层和第二芯片的金属层进行所述键合连接的步骤之后，对所述第一芯片和第一芯片进行退火处理。
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