CN105448715A - Semiconductor device manufacturing method - Google Patents
Semiconductor device manufacturing method Download PDFInfo
- Publication number
- CN105448715A CN105448715A CN201410276851.9A CN201410276851A CN105448715A CN 105448715 A CN105448715 A CN 105448715A CN 201410276851 A CN201410276851 A CN 201410276851A CN 105448715 A CN105448715 A CN 105448715A
- Authority
- CN
- China
- Prior art keywords
- groove
- temperature
- annealing
- etching
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention provides a semiconductor device manufacturing method, and the method comprises the steps: providing a semiconductor substrate, and forming a grid structure on the semiconductor substrate; forming an arcuate groove at a part, at which a source-drain region is about to be formed, of the semiconductor substrate; carrying out high-temperature annealing, and enabling the arcuate groove to be changed into a U-shaped groove; etching the U-shaped groove formed after the high-temperature annealing so as to form a sigma-shaped groove, and carrying out low-temperature annealing of the sigma-shaped groove; and forming an embedded-type germanium silicon layer in the sigma-shaped groove. According to the invention, the method can further improve the distribution uniformity of the contour of the sigma-shaped groove and the thickness uniformity of the embedded-type germanium silicon layer formed later, reduces the selective epitaxial growth temperature of germanium-silicon, further improves the pressure stress to a device trench region from the embedded-type germanium silicon layer, and also can improve the distribution uniformity of electrical performances of a device in the wafer.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of method forming embedded germanium silicon.
Background technology
Along with the continuous reduction of dimensions of semiconductor devices, for metal-oxide semiconductor fieldeffect transistor (MOSFET), the various stress technique of usual employing increases through the electric current of MOS transistor, such as two line of tension (DSL), stress memory technique (SMT), embedded germanium silicon etc.
For PMOS transistor, in order to improve the mobility of charge carrier in its raceway groove, the part making groove that will form source/drain region in PMOS transistor has become with the technology of the embedded germanium silicon of epitaxial growth the focus widely paid close attention to.For there is 45nm with the semiconductor fabrication process of lower node, scaled due to device size, the length also corresponding shortening of device channel, therefore, the part that will form source/drain region in PMOS transistor makes sidewall effectively can shorten length from device channel to the groove of device channel direction indent to have correlative study to point out, meets the requirement that device size is scaled; Meanwhile, this groove has the feature of larger incision below grid gap wall, and thus, in this groove, epitaxially grown embedded germanium silicon can produce larger stress to device channel region.
Make the basic step with the groove of These characteristics to comprise: as shown in Figure 1A, first utilize dry etching in Semiconductor substrate 100, form bowl-shape groove 101; As shown in Figure 1B, the difference of the etch-rate of recycling wet etching on the different crystal orientations of the constituent material of Semiconductor substrate 100, namely the feature that etch-rate is fast, other direction etch-rate is slow of the level of the constituent material relative to Semiconductor substrate 100 that has of described wet etching and vertical direction, forms the groove 102 of described sidewall to device channel direction indent in Semiconductor substrate 100.After described dry etch process terminates, the impact of the sidewall of bowl-shape groove 101 and the surperficial subject plasma bombardment of bottom, generation distortion of lattice misplaces, and then silicon etching speed in the wet etch process causing next step to implement is uneven, cause the inhomogeneities of wafer inner groovy profile, thus make the distribution of device electrical performance in wafer there is greatest differences; Meanwhile, the surface of the sidewall of bowl-shape groove 101 also can be subject to the oxygen in the etching gas of described dry etching employing or the doping caused by nitrogen-atoms bombardment is polluted, and above-mentioned phenomenon all can make the surface appearance of the sidewall of bowl-shape groove 101 be deteriorated.Because the surface appearance of anisotropic wet etching to the sidewall of bowl-shape groove 101 of subsequent implementation is very responsive, namely the surface appearance of the sidewall of bowl-shape groove 101 is poorer, the effect of described wet etching is poorer, finally causes effectively forming the groove 102 of described sidewall to device channel direction indent.In addition, for the crystal orientation that etch-rate is relatively slow, the <111> crystal orientation of such as Semiconductor substrate 100, after described wet etch process terminates, described sidewall will produce the poor some position of physical property on the crystal face being positioned at this crystal orientation of the groove 102 of device channel direction indent, and these potential sources are in the bombardment of etching electricity slurry.In the process of the embedded germanium silicon of subsequently epitaxial growing, the germanium silicon growth technological temperature of needs is higher, and germanium silicon is affected in the growth of these some positions, easily occurs stacking fault defects, and then impact is to the control of the caliper uniformity of the embedded germanium silicon formed.Finally, each several part height of the embedded germanium silicon formed is deep mixed, and the stress that the channel region of its overall pair pmos transistor applies also can weaken.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, be formed with grid structure on the semiconductor substrate; Arciform groove will be formed will being formed in the part of source/drain region of described Semiconductor substrate; Perform the high temperature anneal, make described arciform groove transition be U-shaped groove; The U-shaped groove formed after etching described high annealing, to form ∑ shape groove, and implements process annealing process to described ∑ shape groove; Embedded germanium silicon layer is formed in described ∑ shape groove.
Further, the step forming described arciform groove comprises: first carry out dry etching to form groove to the part that will form source/drain region of described Semiconductor substrate, then carry out wet etching to described groove.
Further, described dry etching is the interconvertible two step etching be made up of isotropic etching and anisotropic etching of execution order.
Further, the technological parameter of described high annealing comprises: temperature is 600-1200 DEG C, and annealing time is 0-2 hour, and annealing atmosphere is H2, N2 or Ar, and pressure is 0-15MPa.
Further, described stress relief annealed technological parameter comprises: temperature is lower than the temperature of described high annealing, and the difference between the temperature of described high annealing and described stress relief annealed temperature is 300-700 DEG C, and annealing time is 0-2 hour, annealing atmosphere is H2, N2 or Ar, and pressure is 0-15MPa.
Further, described stress relief annealed temperature is 500-900 DEG C.
Further, before implementing described high annealing and described process annealing, perform wet cleaning processes respectively, to remove residue in described arciform groove and described ∑ shape groove and impurity respectively.
Further, described formation ∑ shape groove be etched to wet etching, the corrosive liquid of described wet etching is tetramethyl ammonium hydroxide solution.
Further, implement low temperature selective epitaxial growth technique and form described embedded germanium silicon layer, the temperature of described low temperature is 500-850 DEG C.
Further, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top
According to the present invention, the homogeneity of the thickness of the distributing homogeneity of described ∑ shape groove profile and the embedded germanium silicon layer of formation can be promoted further, reduce the temperature of selective epitaxial growth germanium silicon, and then the further compression strengthening embedded germanium silicon layer and device channel region is applied, also can improve the uniformity that device electrical performance distributes in wafer.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A is the schematic cross sectional view adopting prior art to form the bowl-shape groove formed in substrate in the process of embedded germanium silicon;
Figure 1B adopts prior art to form the sidewall that formed in substrate in the process of the embedded germanium silicon schematic cross sectional view to the groove of device channel direction indent;
The schematic cross sectional view of the device that Fig. 2 A-Fig. 2 E obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;
Fig. 3 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain the method for the embedded germanium silicon of formation that the present invention proposes.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment]
Below, with reference to Fig. 2 A-Fig. 2 E and Fig. 3, the detailed step that method according to an exemplary embodiment of the present invention forms embedded germanium silicon is described.
With reference to Fig. 2 A-Fig. 2 E, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, the constituent material of Semiconductor substrate 200 can to adopt on unadulterated monocrystalline silicon, monocrystalline silicon doped with impurity, silicon-on-insulator (SOI), insulator stacked SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc. on stacked silicon (SSOI), insulator.Exemplarily, in the present embodiment, the constituent material of Semiconductor substrate 200 selects monocrystalline silicon.In Semiconductor substrate 200, be formed with isolation structure and various trap (well) structure, in order to simplify, be omitted in diagram.Exemplarily, isolation structure is that shallow trench isolation is from (STI) structure or selective oxidation silicon (LOCOS) isolation structure.
Be formed with grid structure 201 on semiconductor substrate 200, exemplarily, grid structure 201 comprises gate dielectric 201a, the gate material layers 201b and grid hard masking layer 201c that stack gradually from bottom to top.Gate dielectric 201a comprises oxide skin(coating), such as silicon dioxide (SiO
2) layer.Gate material layers 201b comprise in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer one or more, wherein, the constituent material of metal level can be tungsten (W), nickel (Ni) or titanium (Ti); Conductive metal nitride layer comprises titanium nitride (TiN) layer; Conductive metal oxide layer comprises yttrium oxide (IrO
2) layer; Metal silicide layer comprises titanium silicide (TiSi) layer.Grid hard masking layer 201c comprise in oxide skin(coating), nitride layer, oxynitride layer and amorphous carbon one or more, wherein, the constituent material of oxide skin(coating) comprises boron-phosphorosilicate glass (BPSG), phosphorosilicate glass (PSG), tetraethoxysilane (TEOS), undoped silicon glass (USG), spin-coating glass (SOG), high-density plasma (HDP) or spin-on dielectric (SOD); Nitride layer comprises silicon nitride (Si
3n
4) layer; Oxynitride layer comprises silicon oxynitride (SiON) layer.Any prior art that the formation method of gate dielectric 201a, gate material layers 201b and grid hard masking layer 201c can adopt those skilled in the art to have the knack of, preferred chemical vapour deposition technique (CVD), as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition (RTCVD), plasma enhanced chemical vapor deposition (PECVD).
In addition, exemplarily, be also formed on semiconductor substrate 200 and be positioned at grid structure 201 both sides and near the offset by gap wall construction 202 of grid structure 201.Wherein, offset by gap wall construction 202 can comprise at least one oxide skin(coating) and/or nitride layer.
Then, as shown in Figure 2 B, arciform groove 203 will be formed will being formed in the part of source/drain region of Semiconductor substrate 200.The processing step forming arciform groove 203 comprises: first carry out dry etching to form groove to the part that will form source/drain region of Semiconductor substrate 200, then carry out wet etching to described groove.Described dry etching is the interconvertible two step etching be made up of isotropic etching and anisotropic etching of execution order, and wherein, the execution order of described two step etching can according to expecting that the overall size of the groove formed is determined.The source gas of the plasma that described dry etching adopts comprises: CF
4, CH
3f, HBr, NF
3, Cl
2, O
2, N
2deng, carrier gas comprises Ar, He etc.In a preferred embodiment, the processing step implementing described dry etching comprises: first adopt isotropic dry etching to etch Semiconductor substrate 200, to form groove will being formed in the part of source/drain region of Semiconductor substrate 200, the source gas of the plasma that described isotropic dry etching adopts is mainly CF
4, CH
3f, HBr, power 300-500W, bias voltage 50-200V, temperature 40-60 DEG C, the time determines according to etch depth; Adopt anisotropic dry etching to continue the described groove of etching again, described anisotropic dry etching adopts Cl
2and NF
3as the main source gas of plasma, power 100-500W, bias voltage 0-10V, temperature 40-60 DEG C, time 5-50s.
Next, perform wet cleaning processes, to remove the residue and impurity that above-mentioned etching process produces in arciform groove 203.The cleaning fluid that described wet cleaning processes adopts can be the combination of the mixture (SC1) of ammoniacal liquor, hydrogen peroxide and water and the hydrofluoric acid (DHF) of dilution, also can be the combination of Ozone Water, SC1 and DHF.The concentration of each cleaning fluid in combinations thereof and other condition of carrying out required for described wet-cleaned, such as temperature and processing time etc., the concentration values that those skilled in the art all can be selected to have the knack of and implementation condition, no longer exemplified at this.
Then, as shown in Figure 2 C, perform the high temperature anneal, make arciform groove 203 change U-shaped groove 203 ' into.Described high annealing can make the shrinkage degree of the constituent material of the Semiconductor substrate 200 be positioned at below grid structure 201 strengthen, thus change arch channel 203 into U-shaped groove 203 ', and then the compression that the embedded germanium silicon strengthening follow-up formation applies device channel region, can thoroughly remove the residues such as the C/O produced in previous process processing procedure simultaneously.The technological parameter of described high annealing comprises: temperature is 600-1200 DEG C, and annealing time is 0-2 hour, and annealing atmosphere is H2, N2 or Ar, and pressure is 0-15MPa.
Then, as shown in Figure 2 D, wet etching process is adopted to etch U-shaped groove 203 ', to form ∑ shape groove 204.The characteristic that utilizes the etch-rate of the etchant of described wet etching on the different crystal orientations of the material of Semiconductor substrate 200 different (etch-rate in such as 100 crystal orientation and 110 crystal orientation is higher than the etch-rate in 111 crystal orientation), the U-shaped groove 203 ' of expansion etching is to form ∑ shape groove 204.In a preferred embodiment, adopt tetramethyl ammonium hydroxide solution (TMAH) to process U-shaped groove 203 ', the processing time is 1-3min, and treatment temperature is 25-50 DEG C.
Next, perform another wet cleaning processes, to remove etch residues in ∑ shape groove 204 and impurity, thus be beneficial to the growth of follow-up embedded germanium silicon.The cleaning fluid that another wet cleaning processes described adopts can be the combination of the mixture (SC1) of ammoniacal liquor, hydrogen peroxide and water and the hydrofluoric acid (DHF) of dilution, also can be the combination of Ozone Water, SC1 and DHF.The concentration of each cleaning fluid in combinations thereof and carry out described other condition required for another wet-cleaned, such as temperature and processing time etc., the concentration values that those skilled in the art all can be selected to have the knack of and implementation condition, no longer exemplified at this.
Next, process annealing process is implemented to ∑ shape groove 204.Described stress relief annealed technological parameter comprises: temperature is lower than the temperature of described high annealing, difference between the temperature of described high annealing and described stress relief annealed temperature is 300-700 DEG C, described stress relief annealed temperature can be 500-900 DEG C, annealing time is 0-2 hour, annealing atmosphere is H2, N2 or Ar, and pressure is 0-15MPa.Implement described process annealing, the temperature of the selective epitaxial growth process of subsequent implementation can be reduced, be conducive to having the growth of the good germanium silicon layer more suppressing stress.
Then, as shown in Figure 2 E, selective epitaxial growth process is adopted to form embedded germanium silicon layer 205 in ∑ shape groove 204.Described selective epitaxial growth process can adopt the one in low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam epitaxy (MBE).In the present embodiment, described selective epitaxial growth process can be implemented at low temperatures, and the scope of described low temperature is 500-850 DEG C.
In the present embodiment, before forming embedded germanium silicon layer 205, first form inculating crystal layer (seedlayer) (in order to simplify, not give and illustrating in figure) in the bottom of ∑ shape groove 204, described inculating crystal layer is the germanium silicon layer that skim monocrystalline silicon layer or has low Ge content; After forming embedded germanium silicon layer 205, embedded germanium silicon layer 205 is formed cap layers (caplayer) (in order to simplify, not give and illustrating in figure), and described cap layers is the germanium silicon layer that a monocrystalline silicon layer or has low Ge content.
So far, the processing step that the method according to an exemplary embodiment of the present invention that completes is implemented, next, can complete the making of whole semiconductor device by subsequent technique.According to the present invention, the homogeneity of the thickness of the distributing homogeneity of ∑ shape groove profile and the embedded germanium silicon layer of formation can be promoted further, reduce the temperature of selective epitaxial growth germanium silicon, and then the further compression strengthening embedded germanium silicon layer and device channel region is applied, also can improve the uniformity that device electrical performance distributes in wafer.
The whole processing steps more than implementing the method for the formation embedded germanium silicon that the present invention proposes are described for PMOS transistor, and it will be appreciated by those skilled in the art that, PMOS transistor here can be the PMOS part of CMOS transistor.
With reference to Fig. 3, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.
In step 301, provide Semiconductor substrate, be formed with grid structure on a semiconductor substrate;
In step 302, arciform groove will be formed will being formed in the part of source/drain region of Semiconductor substrate;
In step 303, perform the high temperature anneal, make arciform groove transition be U-shaped groove;
In step 304, the U-shaped groove formed after etching described high annealing, to form ∑ shape groove, and implements process annealing process to ∑ shape groove;
In step 305, in ∑ shape groove, embedded germanium silicon layer is formed.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (10)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, is formed with grid structure on the semiconductor substrate;
Arciform groove will be formed will being formed in the part of source/drain region of described Semiconductor substrate;
Perform the high temperature anneal, make described arciform groove transition be U-shaped groove;
The U-shaped groove formed after etching described high annealing, to form ∑ shape groove, and implements process annealing process to described ∑ shape groove;
Embedded germanium silicon layer is formed in described ∑ shape groove.
2. method according to claim 1, is characterized in that, the step forming described arciform groove comprises: first carry out dry etching to form groove to the part that will form source/drain region of described Semiconductor substrate, then carry out wet etching to described groove.
3. method according to claim 2, is characterized in that, described dry etching is the interconvertible two step etching be made up of isotropic etching and anisotropic etching of execution order.
4. method according to claim 1, is characterized in that, the technological parameter of described high annealing comprises: temperature is 600-1200 DEG C, and annealing time is 0-2 hour, and annealing atmosphere is H2, N2 or Ar, and pressure is 0-15MPa.
5. method according to claim 1, it is characterized in that, described stress relief annealed technological parameter comprises: temperature is lower than the temperature of described high annealing, difference between the temperature of described high annealing and described stress relief annealed temperature is 300-700 DEG C, annealing time is 0-2 hour, annealing atmosphere is H2, N2 or Ar, and pressure is 0-15MPa.
6. method according to claim 5, is characterized in that, described stress relief annealed temperature is 500-900 DEG C.
7. method according to claim 1, is characterized in that, before implementing described high annealing and described process annealing, performs wet cleaning processes respectively, to remove residue in described arciform groove and described ∑ shape groove and impurity respectively.
8. method according to claim 1, is characterized in that, described formation ∑ shape groove be etched to wet etching, the corrosive liquid of described wet etching is tetramethyl ammonium hydroxide solution.
9. method according to claim 1, is characterized in that, implement low temperature selective epitaxial growth technique and form described embedded germanium silicon layer, the temperature of described low temperature is 500-850 DEG C.
10. method according to claim 1, is characterized in that, described grid structure comprises the gate dielectric, gate material layers and the grid hard masking layer that stack gradually from bottom to top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410276851.9A CN105448715B (en) | 2014-06-19 | 2014-06-19 | A kind of manufacturing method of semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410276851.9A CN105448715B (en) | 2014-06-19 | 2014-06-19 | A kind of manufacturing method of semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105448715A true CN105448715A (en) | 2016-03-30 |
| CN105448715B CN105448715B (en) | 2019-01-22 |
Family
ID=55558771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410276851.9A Active CN105448715B (en) | 2014-06-19 | 2014-06-19 | A kind of manufacturing method of semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105448715B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112768138A (en) * | 2020-12-18 | 2021-05-07 | 安捷利电子科技（苏州）有限公司 | Preparation method of pattern with narrow channel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100295127A1 (en) * | 2009-05-21 | 2010-11-25 | International Business Machines Corporation | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (soi) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
| CN103187269A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistor |
| CN103594370A (en) * | 2012-08-16 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
-
2014
- 2014-06-19 CN CN201410276851.9A patent/CN105448715B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100295127A1 (en) * | 2009-05-21 | 2010-11-25 | International Business Machines Corporation | Method of forming a planar field effect transistor with embedded and faceted source/drain stressors on a silicon-on-insulator (soi) wafer, a planar field effect transistor structure and a design structure for the planar field effect transistor |
| CN103187269A (en) * | 2011-12-30 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of transistor |
| CN103594370A (en) * | 2012-08-16 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112768138A (en) * | 2020-12-18 | 2021-05-07 | 安捷利电子科技（苏州）有限公司 | Preparation method of pattern with narrow channel |
| CN112768138B (en) * | 2020-12-18 | 2022-04-22 | 安捷利电子科技（苏州）有限公司 | Preparation method of pattern with narrow channel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105448715B (en) | 2019-01-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103594370B (en) | A kind of manufacture method of semiconductor device | |
| CN103187277B (en) | A kind of manufacture method of semiconductor device | |
| CN104425375B (en) | A kind of manufacture method of semiconductor devices | |
| CN102832128B (en) | Manufacturing method of semiconductor device | |
| CN108615731B (en) | Semiconductor device and manufacturing method thereof | |
| CN104217952B (en) | Manufacture method of semiconductor device | |
| CN103151264B (en) | A kind of manufacture method of semiconductor devices | |
| CN103943501A (en) | Manufacturing method of semiconductor device | |
| CN103681333B (en) | A kind of manufacture method of semiconductor devices | |
| CN102856199A (en) | Manufacturing method of semiconductor device | |
| CN105810583A (en) | Horizontal insulated gate bipolar transistor production method | |
| CN102903748B (en) | A kind of lateral double diffusion metal oxide semiconductor and manufacture method thereof | |
| CN103794546A (en) | Method for manufacturing semiconductor device | |
| CN105470296A (en) | Semiconductor device and manufacturing method thereof and electronic device | |
| CN105448715A (en) | Semiconductor device manufacturing method | |
| CN104979291A (en) | Manufacturing method of semiconductor device | |
| CN102915971A (en) | Manufacturing method of semiconductor device | |
| CN107665807B (en) | Semiconductor device and manufacturing method thereof | |
| CN106298779A (en) | A kind of semiconductor device and manufacture method, electronic installation | |
| CN104934323B (en) | A kind of manufacture method of semiconductor devices | |
| CN103151311A (en) | Manufacturing method of semiconductor device | |
| CN104681441A (en) | Method for preventing embedded germanium silicon top cap layer from etching pollution | |
| CN105304491A (en) | Method for forming embedded silicon germanium | |
| CN106257631A (en) | A kind of semiconductor device and manufacture method, electronic installation | |
| CN103903984A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |