CN105448704B - Lithographic method - Google Patents
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- CN105448704B CN105448704B CN201410522599.5A CN201410522599A CN105448704B CN 105448704 B CN105448704 B CN 105448704B CN 201410522599 A CN201410522599 A CN 201410522599A CN 105448704 B CN105448704 B CN 105448704B
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Abstract
The present invention provides a kind of lithographic methods, including：After forming the first mask layer on a semiconductor substrate, the second mask layer is formed on first mask layer, and after forming the first opening in second mask layer, cure process is carried out to being exposed to the first mask layer that first opening is exposed, hardened layer is formed in first mask layer；Later the hardened layer is etched along first opening, the second opening is formed in the hardened layer, there is larger hardness based on the hardened layer, the etch rate of the hardened layer of the sidewall sections close to first opening is set to be less than the etch rate of the hardened layer for the central part being open close to described first, to make, second opening has sloped sidewall and tip size is more than bottom size, and then after being subsequently open as semiconductor base formation third described in mask etching using remaining hardened layer, effectively reduce the third opening size.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly, to a kind of lithographic method.
Background technology
Lithography and etching step is the very important technique in semiconductor fabrication.With reference to figure 1, existing skill is shown
A kind of schematic diagram of photoetching process of art.Photoetching process includes：After forming photoresist layer on wafer 10, photoresist layer is exposed
Pattern on mask plate is transferred on photoresist layer by light, development treatment, to form photoresist mask 11, light described in Fig. 1
Resist mask has pattern openings 12.Etching refers to photoresist mask 11 for mask, and wafer 10 is etched along pattern openings 12,
To form the technique of pattern in wafer 10.
As semiconductor technology develops, feature sizes of semiconductor devices (Critical Dimension, CD) is smaller and smaller,
The integrated level of semiconductor devices is continuously increased.For this purpose, the density of formed pattern is continuously increased on wafer 10, and the size of pattern
Constantly reduce.And the density and size of the pattern of wafer 10 depend on the pattern openings density and size in photoresist mask, are
Formed pattern density on raising wafer 10, accordingly, it is necessary to improve in a lithographic process, the pattern in photoresist mask 11
Density.
In existing photoetching process, pattern density and opening size in photoresist mask 11 depend primarily on exposure and use
The factors such as the refractive index of the eyeglass used in beam wavelength, exposure, the precision of the pattern dimension on mask plate and exposure apparatus.So
And as semiconductor technology develops, be limited to accuracy of instrument and the limitation of photoresist self character (cannot form in such as photoresist
The excessively high pattern openings of density), the requirement to form high density patterns has been cannot be satisfied only by above-mentioned factor adjustment.For this purpose,
Those skilled in the art begins through process modification to improve photoetching quality.
In order to improve the density of the pattern openings on wafer, as shown in Fig. 2, can hard mask material first be formed on wafer 10
Layer (not shown) carries out above-mentioned lithography and etching technique to form the hard mask 17 for including opening 15 to layer of hard mask material
Afterwards, another photoresist layer 13 is formed in the hard mask 17, and is formed on the photoresist layer 13 through another photoetching process
Pattern openings 14；Later, in conjunction with reference to figure 3, the hard mask 12 is etched along the pattern openings 14, the shape in hard mask 12
The patterns of openings 16 of Cheng Xin to improve the opening density formed on photoresist, and then improves the opening density in hard mask 12,
It is later wafer 10 described in mask etching with the hard mask 12.
Above-mentioned technique is equivalent to the number by increasing the photoetching, etching technics, to form pattern openings density higher
Mask, later using the mask as mask etching wafer 10, to obtain density higher, the higher pattern of precision on wafer 10.
But only not only increases technique process by increasing the number of the photoetching, etching technics, improve process costs.This
Outside, the size for being eventually formed in wafer 10 is similarly limited to pattern openings size in photoresist mask.For this purpose, how to obtain more
The problem of pattern of small size is those skilled in the art's urgent need to resolve.
Invention content
Problems solved by the invention is to provide a kind of lithographic method, to reduce the size for etching the pattern formed after wafer.
To solve the above problems, the present invention provides a kind of lithographic method, including：
Semiconductor base is provided；
The first mask layer is formed on the semiconductor base；
The second mask layer is formed on first mask layer；
It forms first in second mask layer to be open, the first mask layer described in first opening exposed portion；
The first mask layer exposed to first opening carries out cure process, forms hardened layer；
The second opening is formed in the hardened layer, makes top of second opening with sloped sidewall and the second opening
Size is more than bottom size；
Third opening is formed by semiconductor base described in mask etching of remaining hardened layer.
Optionally, after forming the second opening in the hardened layer, the side wall that remaining hardened layer is open from described first is extremely
The first opening center thickness is gradually reduced.
Optionally, the material of first mask layer is macromolecule organic material.
Optionally, first mask layer is bottom anti-reflection layer.
Optionally, the method that the first mask layer exposed to first opening carries out cure process is electron beam spoke
Penetrate technique.
Optionally, the step of electron beam irradiation technique includes：Voltage be 300V~2000V, electric current be 1PA~
60PA, radiated time are 1ms~60s, and electron energy is 0.3kev~2kev.
Optionally, the thickness of the hardened layer and the first mask layer ratio is 1:5~1:1.
Optionally, the thickness of the hardened layer is 10 nanometers~200 nanometers.
Optionally, include the step of the second opening of formation in the hardened layer：Described in being etched using dry etch process
Hardened layer, to form second opening.
Optionally, the step of etching the hardened layer include：Using containing the gas of oxygen as etching gas, or adopt
Use the gas that contains nitrogen and hydrogen as etching gas.
Optionally, second mask layer is photoresist mask layer；
The step of the first opening is formed in second mask layer is, using exposure imaging technique in second mask
First opening is formed in layer.
Compared with prior art, technical scheme of the present invention has the following advantages：
After forming the first opening in the second mask layer on first mask layer, to being exposed in first opening
The first mask layer carry out cure process formed hardened layer, to improve be exposed to it is described first opening the first mask layer
The hardness of (i.e. hardened layer) therefore when etching the first mask layer (i.e. the hardened layer) along first opening, increases
The etch rate difference of hardened layer close to the hardened layer of the first opening center and close to first open side wall portions,
The etch rate of the hardened layer of the sidewall sections close to first opening is set to be less than the central part close to first opening
Hardened layer etch rate, to after etching the hardened layer, make the be formed in the hardened layer second opening have
Sloped sidewall and tip size are more than bottom size, that is, reduce the opening size of mask above the semiconductor base, to
After subsequently using remaining hardened layer as semiconductor base described in mask etching, it can effectively reduce and be subsequently formed in the semiconductor base
The size of interior third opening.
Still optionally further, the first mask layer is bottom anti-reflection layer, can be anti-in the bottom after the cure process
Hardened layer is formed in layer of reflective material, in the etching technics of semiconductor applications, forms anti-reflecting layer on a semiconductor substrate
Base on practicality field maturation process, and the present invention is not on the basis of increasing additional material layer, by opening exposing the second mask
Bottom anti-reflective material layer at mouthful carries out cure process, to obtain the hardened layer of high rigidity, to which simplification forms hardened layer
Technique, and then simplify etch process flow, it is low to reduce process costs.
Description of the drawings
A kind of existing structural schematic diagrams of lithographic method of Fig. 1 to Fig. 3；
Fig. 4 to Fig. 8 is the structural schematic diagram of one embodiment of lithographic method of the present invention；
Fig. 9 and Figure 10 is the structural schematic diagram of another embodiment of lithographic method of the present invention.
Specific implementation mode
As stated in the background art, as feature sizes of semiconductor devices is smaller and smaller, the integrated level of semiconductor devices is continuous
Increase, the size to reducing each component of semiconductor proposes new requirement.For this purpose, how to break through existing accuracy of instrument and material
Self character limits, and is a new challenge with the opening size further decreased in semiconductor base.
For this purpose, the present invention provides a kind of lithographic methods, including：After forming the first mask layer on a semiconductor substrate,
The second mask layer is formed on first mask layer, and in second mask layer after the first opening of formation, to being exposed to
The first mask layer for stating the exposing of the first opening carries out cure process, and hardened layer is formed in first mask layer；Later along
First opening etches the hardened layer, and the second opening is formed in the hardened layer, so that second opening is had and tilts
Side wall and tip size are more than bottom size, and form third as semiconductor base described in mask etching using remaining hardened layer and open
Mouthful.
After carrying out hardening process and forming the hardened layer, the first mask for being exposed to first opening is improved
The hardness of layer (i.e. hardened layer), therefore, when etching the first mask layer (the i.e. described hardened layer) along first opening,
Increase the etching speed of the hardened layer and the hardened layer close to first open side wall portions close to the first opening center
Rate difference makes the etch rate of the hardened layer of the sidewall sections close to first opening be less than in first opening
The etch rate of the hardened layer of center portion point, to after etching the hardened layer, make to be formed in second in the hardened layer and open
Mouth has sloped sidewall and tip size is more than bottom size, that is, reduces the opening of etching mask above the semiconductor base
Size can be effectively reduced and be subsequently formed in described after subsequently using remaining hardened layer as semiconductor base described in mask etching
The size of third opening in semiconductor base.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, below in conjunction with the accompanying drawings to the present invention
Specific implementation mode be described in detail.
The structural schematic diagram of one embodiment of lithographic method of the present invention in Fig. 4 to Fig. 8.
The present embodiment lithographic method includes：
With reference to figure 4, semiconductor base 20 is provided.
The semiconductor base 20 includes：Semiconductor substrate.Or the semiconductor base 20 include semiconductor substrate,
Dielectric layer, semiconductor material layer in the semiconductor substrate, and positioned at semiconductor substrate, dielectric layer, semiconductor material
The semiconductor component structures such as transistor, metal interconnecting wires in the bed of material.
The semiconductor substrate is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, insulator
Upper germanium (GOI) substrate, glass substrate or other III-V compound substrates.The present invention to the material of the semiconductor base with
And structure and doing does not limit.
With continued reference to Fig. 4, the first mask layer 21 is formed on the semiconductor base 20；On first mask layer 21
Form the second mask layer 22；
The first opening 23 is formed in second mask layer 22.First mask described in first opening, 23 exposed portion
Layer 21.
Optionally, the material of first mask layer 21 is macromolecule organic material.
In the present embodiment, first mask layer 21 is bottom anti-reflection layer (Bottom Anti-reflective
Coating, abbreviation Barc).
In the present embodiment, second mask layer 22 be photoresist layer, formed it is described first opening 23 the step of for exposure
Developing process.
The Barc layers 21 can be exposed developing process to form the mistake of the first opening 23 to the photoresist layer 22
Cheng Zhong can effectively reduce optical defects such as " standing wave effects ", to improve the be formed in the photoresist layer 22 first opening
Precision.
The material and the techniques such as formation process and exposure imaging of 21 and second mask layer of above-mentioned first mask layer are ability
The mature technology in domain, details are not described herein.
Referring next to Fig. 5, using the photoresist mask as mask, the Barc layers 21 exposed to first opening 23 carry out
Cure process, to form hardened layer 24, the hardness of the hardened layer 24 in the Barc layers 21 of first opening, 23 bottoms
More than original Barc layers 21.
In the present embodiment, the method for the cure process is electron beam irradiation technique.
In the present embodiment, first mask layer 21 is macromolecule organic material, in electron beam irradiation technique, described first
Crosslinking is combined and is strengthened between 21 inner macromolecule group of mask layer, finer and close three-dimensional structure is formed, to make hardness obtain
To reinforcement.
Specifically, in the present embodiment, first mask layer 21 is Barc layers, and existing Barc layers is mostly polyacrylic acid
The high-molecular organic material of esters, after the electron radiation technique, Barc layers of structure change, the macromolecule in Barc layers
Crosslinking between group, which combines, to be strengthened, and forms finer and close three-dimensional structure so that quality is hardened, to form the hardening
Layer 24.
In the present embodiment, in electron beam irradiation technique, photoresist layer is similarly subjected to radiate, and photoresist is mostly organic
Object, during electron beam irradiation, photoresist surface layer can be equally hardened, if the voltage of electron beam irradiation technique or electric current mistake
Greatly, electron beam radiant energy is excessive, and radiated time is long, and photoresist surface can be caused excessively to harden, be easy to cause glue residua
The problem of；If voltage or electric current are too small, electron beam radiant energy is too small, and radiated time is too short, can cause obtain sufficiently strong
The follow-up purpose for reducing and being formed in the opening size in hardened layer is not achieved in the hardened layer of hardness.
In the present embodiment, the electron beam irradiation technological parameter is：Voltage is 300~2000V, and electric current is 1~60PA.According to
It is 1ms~60s to penetrate the time, and electron energy is 0.3~2kev.But the invention is not limited in this regard, electron radiation technological parameter
It can also be not in this range.
In the etching technics of semiconductor applications, the field maturation that bases on practicality of anti-reflecting layer is formed on a semiconductor substrate
Technique, the present embodiment pass through the bottom anti-reflective material to exposing the first opening 23 on the basis of not increasing additional material layer
The bed of material carries out electron beam irradiation technique, to obtain the hardened layer with higher hardness, can effectively simplify the formation work of hardened layer
Skill, and then simplify etch process flow, it is low to reduce process costs.
It is mask with second mask layer 22 after forming the hardened layer 24 in conjunction with reference to figure 6, along described the
One opening, the 23 etching hardened layer 24, forms the second opening 25 in the hardened layer 24.
By taking the structure of the semiconductor devices described in Fig. 5 as an example, the hardened layer 24 is etched along first opening 23
In the process, the etching dynamics being subject to close to the hardened layer 24 of first open side wall portions is less than close to the first 23 centers of opening
The hardened layer 24 of position causes the etch rate of the hardened layer 24 close to first opening, 23 sidewall sections to be less than close to first
Be open the hardened layers 24 of 23 centers.
If the hardened layer 24 is easier to be etched, i.e. 24 etch rate of hardened layer is very fast, can reduce hardened layer 24 close to institute
State the side wall of the first opening 23 and the etch rate difference of central part so that described to be formed in the open side being etched in material
Wall near normal.
But in the present embodiment, after carrying out cure process to first mask 21 and forming hardened layer, increases and be exposed to
The hardness on 21 surface layer of the first mask layer in first opening 23, makes the hardness of the hardened layer 24 be far longer than described first
21 original hardness of mask layer.Thus, along described first be open 23 etch the hardened layer 24 when, increase close to described the
The hardened layer of the etch rate of the hardened layer 24 of the sidewall sections of one opening 23 and the central part close to first opening 23
24 etch rate difference makes the etch rate of the hardened layer 24 of the sidewall sections close to first opening 23 far smaller than lean on
The etch rate of the hardened layer 24 of the central part of nearly first opening 23, to make to be formed in first mask layer 21
It is described second opening 25 have sloped sidewall, and it is described second opening 25 tip size be more than bottom size.
In the present embodiment, after forming the second opening 25 in the hardened layer 24, remaining hardened layer 241 is opened from described first
The side wall of mouth 23 to first opening, 23 center thickness are gradually reduced.
In the present embodiment, the method for etching the hardened layer 24 is dry etching.The dry etch process includes：Using
Contain the gas of oxygen as etching gas, or use the gas for containing nitrogen and hydrogen as etching gas, to improve
Etch the rate of the hardened layer.
In the present embodiment, it is formed in the sidewall slope of the second opening 25 in the hardened layer 24, and the second opening 25
Tip size is more than bottom size.For this purpose, under second opening, 25 sidewall slope angle certain conditions, the hardened layer 24
There need to be enough thickness to reduce the be formed in the hardened layer second 25 bottom sizes of opening, that is, reduce the second opening
25 size.
If but the thickness of the hardened layer 24 is excessive, causes second opening, 25 bottom sizes too small, is unfavorable for follow-up
Etching technics carries out.
In the prior art, the thickness of the Barc layers 21 is described in the present embodiment between 50~200 nanometers (nm)
The thickness of the thickness of hardened layer 24 and the first mask layer ratio is 1:5~1:1.
In concrete technology, the hardened layer 24 has specific thickness according to the difference of material and cure process mode.
In the present embodiment, the thickness of the hardened layer 24 is greater than or equal to 10 nanometers (nm).Still optionally further, described hard
The thickness for changing layer 24 is 10 nanometers~200 nanometers (nm).
In the present embodiment, it is less than 1 in the thickness ratio of the hardened layer 24 and the Barc layers 21:1, thus in the hardening
24 lower section of layer still remains the Barc layers that part is not hardened processing.
It is mask with remaining hardened layer 241 referring next to Fig. 7, etching is not hardened the first mask layer 21 formation of processing
4th opening 26.
As shown in fig. 7, being more than bottom ruler based on the tip size for etching the second opening 25 formed after the hardened layer 24
It is very little, thus, with remaining hardened layer 241 for mask, etches the 4th formed after not being hardened the first mask layer 21 of processing and open
The size of mouth 26 is less than first opening, 23 sizes.
And the hardness based on the Barc layers for not being hardened processing is much smaller than the hardness of the hardened layer 24, the 4th opening
26 top and the dimension ratio of bottom, the dimension ratio on the top and bottom of far smaller than described second opening 25.
For this purpose, compared to the hardened layer 24 is not formed, directly along first opening, 23 etching first mask layer
After 21, the more smooth hatch frame of side wall can be formed in first mask layer 21, in the present embodiment, covered described first
The opening sidewalls formed in mold layer 21 have apparent hierarchic structure, and effectively reduce in first mask layer 21
Opening size.
It is semiconductor base 20 described in mask etching with remaining hardened layer 241 with reference to figure 8, forms third opening 27.
It is mask with remaining hardened layer 241 in the present embodiment, etching is not hardened the first mask layer 21 of processing and partly leads
The method of body substrate 20 is dry etch process, which is this field maturation process, and details are not described herein.
Thus compared with the prior art, compared to the first mask layer without cure process, it is hardened that treated the
The hardness of one mask layer (i.e. hardened layer) obviously increases, and therefore, first mask layer is being etched (i.e. along first opening
Hardened layer) when, increase the hardening of the hardened layer and close first open side wall portions close to the first opening center
The etch rate difference of layer makes the etch rate of the hardened layer of the sidewall sections close to first opening far smaller than close to institute
The etch rate of the hardened layer of the central part of the first opening is stated, it is described hard to after etching the hardened layer, make to be formed in
Change the second opening in layer with sloped sidewall and tip size is more than bottom size.It reduces above the semiconductor base
The opening size of etching mask can effectively reduce after subsequently using remaining hardened layer as semiconductor base described in mask etching
It is subsequently formed in the size of the third opening in the semiconductor base.
Fig. 9 and Figure 10 is the structural schematic diagram of another embodiment of lithographic method of the present invention.
In above-described embodiment, in cure process, electron beam irradiation hardens the Barc layers 21 of segment thickness, in the hardening
24 lower section of layer remains the Barc layers for not being hardened processing of segment thickness.
With reference to figure 9 and Figure 10, in another embodiment of lithographic method of the present invention, the thickness of the hardened layer and described the
The thickness ratio of one mask layer is 1:1.That is, during electron beam irradiation, the full depth that first opening is exposed has been radiated
First mask layer makes the thin hardened layer be equal to the thickness of first mask layer 21.
The hardened layer subsequently is being etched along the first opening in the second mask layer, second is formed in the hardened layer
It is directly semiconductor base 20 described in mask etching with remaining hardened layer 31, in the semiconductor base 20 after opening 30
Form the second opening 32.
It is worth noting that, present invention can apply to the tungsten electrode formation process of such as transistor or Damascus works
The metal interconnecting wires of skill are formed in the every field such as technique, and the present invention does not limit application field.
In addition, before forming first mask layer, silicon nitride (SiN) can be first formed by the semiconductor base
The hard mask layer of equal materials, forms first mask layer and the second mask layer on the hard mask layer later；Exist later
After forming the second opening in hardened layer, directly hard mask figure is formed by hard mask layer described in mask etching of remaining hardened layer
Case, then using hard mask layer as semiconductor base described in mask etching.It compares and the prior art, directed along the first opening etching institute
Hard mask layer is stated to form the technical solution of hard mask pattern, the technical solution provided through the invention, which can effectively reduce, to be formed
Pattern dimension in hard mask pattern, after reducing subsequently using the hard mask as semiconductor base described in mask etching, shape
At with the pattern dimension in semiconductor base.Above application is within the scope of the invention.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (11)
1. a kind of lithographic method, which is characterized in that including：
Semiconductor base is provided；
The first mask layer is formed on the semiconductor base；
The second mask layer is formed on first mask layer；
It forms first in second mask layer to be open, the first mask layer described in first opening exposed portion；
The first mask layer exposed to first opening carries out cure process, forms hardened layer；
The second opening is formed in the hardened layer, makes tip size of second opening with sloped sidewall and the second opening
More than bottom size；
Third opening is formed by semiconductor base described in mask etching of remaining hardened layer.
2. lithographic method as described in claim 1, which is characterized in that remaining after forming the second opening in the hardened layer
Hardened layer is gradually reduced from the side wall of first opening to the first opening center thickness.
3. lithographic method as described in claim 1, which is characterized in that the material of first mask layer is the organic material of macromolecule
Material.
4. lithographic method as described in claim 1, which is characterized in that first mask layer is bottom anti-reflection layer.
5. lithographic method as described in claim 1, which is characterized in that the first mask layer exposed to first opening
The method for carrying out cure process is electron beam irradiation technique.
6. lithographic method as claimed in claim 5, which is characterized in that the step of electron beam irradiation technique includes：Voltage
For 300V~2000V, electric current is 1PA~60PA, and radiated time is 1ms~60s, and electron energy is 0.3kev~2kev.
7. lithographic method as described in claim 1, which is characterized in that the thickness of the hardened layer and the first mask layer ratio is 1:
5~1:1.
8. lithographic method as described in claim 1, which is characterized in that the thickness of the hardened layer is 10 nanometers~200 nanometers.
9. lithographic method as described in claim 1, which is characterized in that the step of forming the second opening in the hardened layer is wrapped
It includes：The hardened layer is etched using dry etch process, to form second opening.
10. lithographic method as claimed in claim 9, which is characterized in that the step of etching the hardened layer include：Using containing
The gas of oxygen is as etching gas, or uses the gas for containing nitrogen and hydrogen as etching gas.
11. lithographic method as described in claim 1, which is characterized in that second mask layer is photoresist mask layer；
The step of the first opening is formed in second mask layer is, using exposure imaging technique in second mask layer
Form first opening.
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| CN201410522599.5A CN105448704B (en) | 2014-09-30 | 2014-09-30 | Lithographic method |
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|---|---|---|---|
| CN201410522599.5A CN105448704B (en) | 2014-09-30 | 2014-09-30 | Lithographic method |
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| CN105448704B true CN105448704B (en) | 2018-08-10 |
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| US6458663B1 (en) * | 2000-08-17 | 2002-10-01 | Micron Technology, Inc. | Masked nitrogen enhanced gate oxide |
| CN1314097C (en) * | 2003-09-25 | 2007-05-02 | 茂德科技股份有限公司 | Side wall doping method of isolating furrow |
| TWI305930B (en) * | 2006-06-19 | 2009-02-01 | Touch Micro System Tech | Method of fabricating suspended structure |
| CN102074495B (en) * | 2009-11-20 | 2013-10-09 | 中芯国际集成电路制造(上海)有限公司 | Forming method for shallow trench isolation (STI) |
| JP5768397B2 (en) * | 2011-02-16 | 2015-08-26 | 三菱電機株式会社 | Manufacturing method of semiconductor device |
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