CN105448348B - A kind of chip restorative procedure and device - Google Patents
A kind of chip restorative procedure and device Download PDFInfo
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- CN105448348B CN105448348B CN201410251439.1A CN201410251439A CN105448348B CN 105448348 B CN105448348 B CN 105448348B CN 201410251439 A CN201410251439 A CN 201410251439A CN 105448348 B CN105448348 B CN 105448348B
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Abstract
The present invention provides a kind of chip restorative procedure and devices, to solve the problem of that GBL reparation is unable to satisfy the promotion of chip yields and performance boost requirement.The described method includes: testing the main array memory cells in chip, the access unit address information to be broken down；According to the redundant storage unit in the access unit address information and chip to break down, chip is repaired；Wherein, redundant storage unit includes the first storage unit and the second storage unit；First storage unit and main array memory cells share trap, bit line and high address；Second storage unit and main array memory cells do not share trap, bit line and high address.The present invention increases the mode that a kind of pair of chip is repaired, when GBL reparation can not completely repair chip, can carry out the second reparation, meet the requirement of the promotion of chip yields and performance boost by increasing by the second storage unit in the chips.
Description
Technical field
The present invention relates to electronic technology fields, more particularly to a kind of chip restorative procedure and device.
Background technique
With the reduction of process node, the increase of chip area, the capacity of chip is obviously improved, and the yield of chip faces
Huge challenge.In present chip, there are thousands of to tens Flash storage units, due to the inconsistency of technique, with
And other various extraneous factors, it will inevitably cause individual storage units performance therein poor or even can not make
With.Such case is encountered, if not having repair function in chip, will lead to entire chip can not work, and be taken as waste paper.Work as addition
After repair function, error unit can be replaced using redundant resource automatically, being automatically repaired for bad point be realized, so that bad point is less
Chip become available normal chip, to improve the yield of product.
In the chip product of early stage, process node typically more falls behind, and chip capacity is not very big, storage unit number
Also relatively few, therefore be mostly to be repaired using global bit line (GBL), there are a fixed limit in the bad point number that can be repaired and position
System can be more than the range that GBL is repaired when locally having multiple bad points, and appearance part GBL reparation resource is not enough, and other
Position GBL repairs the not used situation of resource, so that failure nothing occurs in chip in the case where reparation resource fails complete use
The state of method work, fails the yield that product is promoted by GBL reparation.When process node further decreases, storage unit
Discreteness further increases, and after capacity increase leads to chip area increase, only can no longer meet chip yields with GBL reparation
The requirement of promotion and performance boost.
Summary of the invention
The present invention provides a kind of chip restorative procedure and device, and being unable to satisfy chip yields to solve GBL reparation is promoted,
And the problem of performance boost requirement.
To solve the above-mentioned problems, the present invention provides a kind of chip restorative procedures, comprising:
Main array memory cells in chip are tested, the access unit address information to be broken down；
According to the redundant storage unit in the access unit address information to break down and the chip, to described
Chip is repaired；
Wherein, the redundant storage unit includes the first storage unit and the second storage unit；First storage unit
Trap, bit line and high address are shared with the main array memory cells；Second storage unit and the main array storage are single
Member does not share trap, bit line and high address.
Preferably, the main array memory cells in chip are tested, the storage unit to be broken down
Address information, comprising:
Write-in tests information to the main array memory cells；
Read the storage information in the main array memory cells after said write tests information；
Determine that reading failure or storage the information main array memory cells different from information is tested is the storage broken down
Unit；
The access unit address information to break down described in preservation is into latch；Breaking down in the latch
Access unit address information and the redundant storage unit address information have mapping relations.
Preferably, the redundant storage in the access unit address information to break down according to and the chip
Unit repairs the chip, comprising:
According to the access unit address information to break down and first storage unit, the chip is carried out
First repairs；
After if described first repairs, there are still the storage unit to break down in the main array memory cells, according to
There are still the access unit address information to break down and second storage unit, the chip second repair
It is multiple.
Preferably, it described first repairs as global bit line reparation；
The basis there are still the access unit address information to break down and second storage unit, to described
Chip carries out second and repairs, comprising:
Determine it is described there are still the storage unit to break down concentrate where trouble block；
According to the ground of the access unit address information to break down and the redundant storage unit in the latch
The mapping relations of location information, it is determining with it is described there are still the corresponding second storage unit concentration of the storage unit to break down
The reparation block at place；
The reparation block is replaced the trouble block.
Preferably, second storage unit is provided with the sub- storage unit of redundancy, the sub- storage unit of redundancy for pair
Second storage unit carries out first and repairs.
Preferably, the chip includes Nor Flash.
The present invention also provides a kind of chip prosthetic devices, comprising:
Test module, for testing the main array memory cells in chip, the storage unit to be broken down
Address information；
Repair module, the access unit address information for breaking down according to are deposited with the redundancy in the chip
Storage unit repairs the chip；
Wherein, the redundant storage unit includes the first storage unit and the second storage unit；First storage unit
Trap, bit line and high address are shared with the main array memory cells；Second storage unit and the main array storage are single
Member does not share trap, bit line and high address.
Preferably, the test module, comprising:
It tests information and submodule is written, for test information to be written to the main array memory cells；
Information reading submodule is stored, for reading depositing in the main array memory cells after said write tests information
Store up information；
Trouble unit determines submodule, for determining that reading failure or storage the information main array different from information is tested deposits
Storage unit is the storage unit to break down；
Address information saves submodule, for saving the access unit address information to break down to latch
In；The address information of the access unit address information to break down and the redundant storage unit in the latch has
Mapping relations.
Preferably, the repair module, comprising:
First repairs submodule, access unit address information and first storage for breaking down according to
Unit carries out first to the chip and repairs；
Second repairs submodule, if after repairing submodule progress first reparation for described first, the main battle array
There are still the storage unit to break down in array storage unit, according to there are still the access unit address information to break down
With second storage unit, second is carried out to the chip and is repaired.
Preferably, it described first repairs as global bit line reparation；
Described second repairs submodule, comprising:
Trouble block determines sub-module, for determine it is described there are still the storage unit to break down concentrate where failure
Block；
Repair block determine sub-module, for according in the latch the access unit address information to break down with
The mapping relations of the address information of the redundant storage unit, it is determining with it is described there are still the storage unit to break down it is opposite
The second storage unit answered concentrates the reparation block at place；
Sub-module is replaced, for the reparation block to be replaced the trouble block.
Preferably, second storage unit is provided with the sub- storage unit of redundancy, the sub- storage unit of redundancy for pair
Second storage unit carries out first and repairs.
Preferably, the chip includes Nor Flash.
Compared with prior art, the present invention includes the following advantages:
Redundant storage unit is provided in chip in the present invention, redundant storage unit includes the first storage unit and second
Storage unit；First storage unit and main array memory cells share trap, bit line and high address, the first storage unit and can use
The storage unit to break down in main array memory cells carries out GBL reparation；Second storage unit and the storage of main array are single
The not shared trap of member, bit line and high address, the second storage unit can be to the storage lists to break down in main array memory cells
Member carries out block reparation.By increasing by the second storage unit in the chips, the mode that a kind of pair of chip is repaired is increased,
When GBL reparation can not completely repair chip, the second reparation can be carried out, meets the promotion of chip yields, Yi Jixing
The requirement that can be promoted.
Detailed description of the invention
Fig. 1 is one of embodiment of the present invention one chip restorative procedure flow chart；
Fig. 2 is one of embodiment of the present invention two chip restorative procedure flow chart；
Fig. 3 is the schematic diagram that first storage unit carries out GBL reparation in the embodiment of the present invention two；
Fig. 4 is the schematic diagram that second storage unit carries out BLOCK reparation in the embodiment of the present invention two；
Fig. 5 is one of embodiment of the present invention three chip prosthetic device structure chart；
Fig. 6 is one of embodiment of the present invention four chip prosthetic device structure chart.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
A kind of chip restorative procedure and dress provided by the invention is discussed in detail below by several specific embodiments are enumerated
It sets.
Embodiment one
The embodiment of the present invention one provides a kind of chip restorative procedure.
Referring to Fig.1, one of embodiment of the present invention one chip restorative procedure flow chart is shown.
Step 100, the main array memory cells in chip are tested, the access unit address to be broken down
Information.
The test can be some specific to main array memory cells write-in therein to carry out full sheet programming to chip
Information is such as all 0 or is all 1.Then chip is read, reading failure or reading obtained information not is write-in
The main array memory cells of specific information be the storage unit to break down, monitor the storage unit to be broken down
Address information.
Step 102, according to the redundant storage list in the access unit address information to break down and the chip
Member repairs the chip.
Wherein, the redundant storage unit may include the first storage unit and the second storage unit；First storage
Unit and the main array memory cells share trap, bit line and high address；Second storage unit is deposited with the main array
Storage unit does not share trap, bit line and high address.
First storage unit can be set in the two sides of main array memory cells, and first storage unit can be right
The storage unit to break down is repaired, but the quantity for the storage unit repaired and position have certain limitations.Because first
Storage unit is based on global bit line and is repaired, it will usually be corresponding one first storage of 32 or 64 main array memory cells
Unit.So the first storage unit will not be too many, generally respectively there are one to two groups in main array memory cells or so.
Except second storage unit is independently of main array, because of the second storage unit and the main array memory cells
Do not share trap, bit line and high address, thus the quantity for the storage unit to break down that the second storage unit can repair and
The freedom degree of position is higher.Second storage unit is mainly used for the multiple hairs of the storage unit to break down and part of large area
The reparation of the storage unit of raw failure.
The embodiment of the present invention is provided with redundant storage unit, redundant storage unit by using above scheme in the chip
Including the first storage unit and the second storage unit；First storage unit and main array memory cells share trap, bit line and a high position
Address, the first storage unit can be used for carrying out GBL reparation to the storage unit to break down in main array memory cells；Second
Storage unit and main array memory cells do not share trap, bit line and high address, the second storage unit and can store to main array
The storage unit to break down in unit carries out block reparation.By increasing by the second storage unit in the chips, it is a kind of right to increase
The mode that chip is repaired can carry out the second reparation, meet when GBL reparation can not completely repair chip
Chip yields is promoted and the requirement of performance boost.
Embodiment two
A kind of chip restorative procedure provided in an embodiment of the present invention is discussed in detail.
Referring to Fig. 2, one of embodiment of the present invention two chip restorative procedure flow chart is shown.
The chip may include Nor Flash.Nor Flash is a kind of current main non-volatile flash memory.In core
In piece design process, some redundant storage units can be added in the chips.The redundant storage unit may include first depositing
Storage unit and the second storage unit；First storage unit and the main array memory cells share trap, bit line and high-order ground
Location, for carrying out GBL reparation, Fig. 3 is the schematic diagram that the first storage unit carries out GBL reparation, when going out in main array memory cells
When storage unit (bad point) now to break down, it can use the first storage unit and repaired；Second storage unit with
The main array memory cells do not share trap, bit line and high address, repair for carrying out block (BLOCK), and Fig. 4 is the second storage
Unit carries out the schematic diagram of BLOCK reparation, when occurring the multiple bad points of the bad block of large area or part in main array memory cells
When, it can use the second storage unit and repaired.The sub- storage unit of redundancy has can be set in second storage unit, described
The sub- storage unit of redundancy is used to carry out first to second storage unit to repair, i.e. GBL is repaired.
Step 200, the main array memory cells in chip are tested, the access unit address to be broken down
Information.
Preferably, the step 200 may include:
Sub-step 2001, write-in test information to the main array memory cells.
Full sheet programming can be carried out to chip, specific test information is written to main array memory cells, such as full 0 or entirely
1。
Sub-step 2002 reads the storage information in the main array memory cells after said write tests information.
Normal read operation is carried out to the main array memory cells in chip.
Sub-step 2003 determines that reading failure or storage the information main array memory cells different from information is tested is to occur
The storage unit of failure.
In reading process, the storage unit (bad point) to break down is monitored automatically, obtains the address letter of bad point
Breath.
Sub-step 2004, the access unit address information to break down described in preservation is into latch.
The access unit address information to break down in the latch can be with the ground of the redundant storage unit
Location information has mapping relations.
Step 202, according to the redundant storage list in the access unit address information to break down and the chip
Member repairs the chip.
Preferably, the step 202 may include: preferential execution sub-step 2021.
Sub-step 2021 is right according to the access unit address information to break down and first storage unit
The chip carries out first and repairs.
Preferably, it described first repairs and can be repaired for global bit line (GBL), GBL reparation can repair local bad point, together
When the first storage unit shared by chip area it is little.
When GBL reparation is unable to satisfy chip requirement, that is, there are still break down in main array memory cells after repairing
When storage unit, illustrates that bad point quantity has had exceeded the range of GBL reparation, execute sub-step 2022.
Sub-step 2022, according to there are still the access unit address information to break down and second storage it is single
Member carries out second to the chip and repairs.
Preferably, the sub-step 2022 may include:
Step by step 20221, determine it is described there are still the storage unit to break down concentrate where trouble block.
For example, there are still storage unit h1, h2, h3, h4 for breaking down concentrate where trouble block be g1.
Step by step 20222, according to the access unit address information to break down and the redundancy in the latch
The mapping relations of access unit address information, it is determining with it is described there are still the storage unit to break down corresponding second
Storage unit concentrates the reparation block at place.
It is described there are still storage unit h1, h2, h3, h4 for breaking down address information respectively with the second storage unit
The address information of c1, c2, c3, c4 are corresponding, and it is x1 that described second storage unit c1, c2, c3, c4, which concentrate the block at place, then
Block x1 is the reparation block of trouble block g1.
Step by step 20223, the reparation block is replaced the trouble block.
Block x1 will be repaired and replace trouble block g1.
The embodiment of the present invention repairs GBL and BLOCK reparation is used cooperatively, and the storage list of mistake can will occur when reparation
Member disabling, by the address information in latch be written one it is specific repair in resource array, each chip power on after from specific
Reparation resource array in address information is read out, be deposited into latch.The embodiment of the present invention can also be according to reality
The test condition of situation modification chip is repeatedly repaired, and the storage unit to break down in chip is replaced, and is sacrificing some cores
On the basis of piece area, the yields and performance of chip are promoted.
The embodiment of the present invention is provided with redundant storage unit, redundant storage unit by using above scheme in the chip
Including the first storage unit and the second storage unit；First storage unit and main array memory cells share trap, bit line and a high position
Address, the first storage unit can be used for carrying out GBL reparation to the storage unit to break down in main array memory cells；Second
Storage unit and main array memory cells do not share trap, bit line and high address, the second storage unit and can store to main array
The storage unit to break down in unit carries out block reparation.By increasing by the second storage unit in the chips, it is a kind of right to increase
The mode that chip is repaired can carry out the second reparation, meet when GBL reparation can not completely repair chip
Chip yields is promoted and the requirement of performance boost.
BLOCK repair function is added, configures redundant storage unit more freely, recoverable bad point number
Amount and position have clear improvement, and GBL is repaired and BLOCK reparation is used cooperatively, effectively promotion remediation efficiency, is occupying redundancy
Under the premise of storage unit is least, bad points more as far as possible is repaired.
Embodiment three
A kind of chip prosthetic device of the offer of the embodiment of the present invention three is provided.
Referring to Fig. 5, one of embodiment of the present invention three chip prosthetic device structure chart is shown.
A kind of chip prosthetic device may include following modules:
Test module 300, and, repair module 302.
The relationship between the function and each module of each module is described in detail below.
Test module 300, for testing the main array memory cells in chip, the storage list to be broken down
The address information of member.
Repair module 302, access unit address information for breaking down according to it is superfluous in the chip
Balance storage unit repairs the chip.
Wherein, the redundant storage unit may include the first storage unit and the second storage unit；First storage
Unit and the main array memory cells share trap, bit line and high address；Second storage unit is deposited with the main array
Storage unit does not share trap, bit line and high address.
The embodiment of the present invention is provided with redundant storage unit, redundant storage unit by using above scheme in the chip
Including the first storage unit and the second storage unit；First storage unit and main array memory cells share trap, bit line and a high position
Address, the first storage unit can be used for carrying out GBL reparation to the storage unit to break down in main array memory cells；Second
Storage unit and main array memory cells do not share trap, bit line and high address, the second storage unit and can store to main array
The storage unit to break down in unit carries out block reparation.By increasing by the second storage unit in the chips, it is a kind of right to increase
The mode that chip is repaired can carry out the second reparation, meet when GBL reparation can not completely repair chip
Chip yields is promoted and the requirement of performance boost.
Example IV
A kind of chip prosthetic device of the offer of the embodiment of the present invention four is provided.
Referring to Fig. 6, one of embodiment of the present invention four chip prosthetic device structure chart is shown.
The chip may include Nor Flash.A kind of chip prosthetic device may include following modules, submodule
And sub-module:
Test module 400, and, repair module 402.
Wherein, above-mentioned test module 400 may include following submodule:
It tests information and submodule 4001 is written, store information reading submodule 4002, trouble unit determines submodule 4003,
And address information saves submodule 4004.
Above-mentioned repair module 402 may include following submodule:
First repairs submodule 4021, and, second repairs submodule 4022.
Above-mentioned second reparation submodule may include following sub-module:
Trouble block determines sub-module 40221, repairs block and determines sub-module 40222, and, replace sub-module 40223.
Be described in detail below each module, the function of each submodule and each sub-module and each module, each submodule and
Relationship between each sub-module.
Test module 400, for testing the main array memory cells in chip, the storage list to be broken down
The address information of member.
Preferably, the test module 400 may include:
It tests information and submodule 4001 is written, for test information to be written to the main array memory cells.
Information reading submodule 4002 is stored, for reading in the main array memory cells after said write tests information
Storage information.
Trouble unit determines submodule 4003, reads failure or storage the information main battle array different from information is tested for determining
Array storage unit is the storage unit to break down.
Address information saves submodule 4004, for saving the access unit address information to break down to latch
In device.
The access unit address information to break down in the latch can be with the ground of the redundant storage unit
Location information has mapping relations.
Repair module 402, access unit address information for breaking down according to it is superfluous in the chip
Balance storage unit repairs the chip.
Wherein, the redundant storage unit may include the first storage unit and the second storage unit；First storage
Unit and the main array memory cells share trap, bit line and high address；Second storage unit is deposited with the main array
Storage unit does not share trap, bit line and high address.The sub- storage unit of redundancy has can be set in second storage unit, described superfluous
Minor storage unit is used to carry out first to second storage unit to repair.
Preferably, the repair module 402 may include:
First repairs submodule 4021, the access unit address information for breaking down according to and described first
Storage unit carries out first to the chip and repairs.
First reparation can be global bit line reparation.
Second repairs submodule 4022, if after carrying out first reparation for the first reparation submodule 4021,
In the main array memory cells there are still the storage unit to break down, according to there are still the storage unit to break down
Address information and second storage unit carry out second to the chip and repair.
Preferably, the second reparation submodule 4022 may include:
Trouble block determines sub-module 40221, for determine it is described there are still the storage unit to break down concentrate where
Trouble block.
It repairs block and determines sub-module 40222, for according to the access unit address to break down in the latch
The mapping relations of the address information of information and the redundant storage unit, it is determining with it is described there are still the storage list to break down
Corresponding second storage unit of member concentrates the reparation block at place.
Sub-module 40223 is replaced, for the reparation block to be replaced the trouble block.
The embodiment of the present invention repairs GBL and BLOCK reparation is used cooperatively, and the storage list of mistake can will occur when reparation
Member disabling, by the address information in latch be written one it is specific repair in resource array, each chip power on after from specific
Reparation resource array in address information is read out, be deposited into latch.The embodiment of the present invention can also be according to reality
The test condition of situation modification chip is repeatedly repaired, and the storage unit to break down in chip is replaced, and is sacrificing some cores
On the basis of piece area, the yields and performance of chip are promoted.
The embodiment of the present invention is provided with redundant storage unit, redundant storage unit by using above scheme in the chip
Including the first storage unit and the second storage unit；First storage unit and main array memory cells share trap, bit line and a high position
Address, the first storage unit can be used for carrying out GBL reparation to the storage unit to break down in main array memory cells；Second
Storage unit and main array memory cells do not share trap, bit line and high address, the second storage unit and can store to main array
The storage unit to break down in unit carries out block reparation.By increasing by the second storage unit in the chips, it is a kind of right to increase
The mode that chip is repaired can carry out the second reparation, meet when GBL reparation can not completely repair chip
Chip yields is promoted and the requirement of performance boost.
BLOCK repair function is added, configures redundant storage unit more freely, recoverable bad point number
Amount and position have clear improvement, and GBL is repaired and BLOCK reparation is used cooperatively, effectively promotion remediation efficiency, is occupying redundancy
Under the premise of storage unit is least, bad points more as far as possible is repaired.
For device embodiment, since it is basically similar to the method embodiment, related so being described relatively simple
Place illustrates referring to the part of embodiment of the method.
For the aforementioned method embodiment, for simple description, therefore, it is stated as a series of action combinations, still
Those skilled in the art should understand that the present invention is not limited by the sequence of acts described, because according to the present invention, it is certain
Step can be performed in other orders or simultaneously.Secondly, those skilled in the art should also know that, it is described in the specification
Embodiment belong to preferred embodiment, it is related that actions and modules are not necessarily necessary for the present invention.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.
It is provided for the embodiments of the invention a kind of chip restorative procedure and device above, is described in detail, herein
In apply that a specific example illustrates the principle and implementation of the invention, the explanation of above example is only intended to sides
Assistant solves method and its core concept of the invention；At the same time, for those skilled in the art, think of according to the present invention
Think, there will be changes in the specific implementation manner and application range, in conclusion the content of the present specification should not be construed as pair
Limitation of the invention.
Claims (10)
1. a kind of chip restorative procedure characterized by comprising
Main array memory cells in chip are tested, the access unit address information to be broken down；
According to the redundant storage unit in the access unit address information to break down and the chip, to the chip
It is repaired；
Wherein, the redundant storage unit includes the first storage unit and the second storage unit；First storage unit and institute
It states main array memory cells and shares trap, bit line and high address；Second storage unit and the main array memory cells are not
Share trap, bit line and high address；
Redundant storage unit in the access unit address information to break down according to and the chip, to described
Chip is repaired, comprising:
According to the access unit address information to break down and first storage unit, first is carried out to the chip
It repairs；
After if described first repairs, there are still the storage unit to break down in the main array memory cells, according to still depositing
The access unit address information to break down and second storage unit, to the chip carry out second repair.
2. the method according to claim 1, wherein the main array memory cells in chip are surveyed
Examination, the access unit address information to be broken down, comprising:
Write-in tests information to the main array memory cells；
Read the storage information in the main array memory cells after said write tests information；
Determine that reading failure or storage the information main array memory cells different from information is tested is the storage unit to break down；
The access unit address information to break down described in preservation is into latch；In the latch break down deposit
The address information of storage unit and the address information of the redundant storage unit have mapping relations.
3. the method according to claim 1, wherein described first repairs as global bit line reparation；
The basis there are still the access unit address information to break down and second storage unit, to the chip
Second is carried out to repair, comprising:
Determine it is described there are still the storage unit to break down concentrate where trouble block；
According to the address information of the access unit address information to break down and the redundant storage unit in latch
Mapping relations, it is determining with it is described there are still corresponding second storage unit of the storage unit to break down concentrate repairing for place
Multiblock；
The reparation block is replaced the trouble block.
4. according to the method described in claim 3, it is characterized in that, second storage unit is provided with redundancy storage list
Member, the sub- storage unit of redundancy are used to carry out first to second storage unit to repair.
5. the method according to claim 1, wherein the chip includes Nor Flash.
6. a kind of chip prosthetic device characterized by comprising
Test module, for testing the main array memory cells in chip, the ground of the storage unit to be broken down
Location information；
Repair module, the redundant storage list in access unit address information and the chip for breaking down according to
Member repairs the chip；
Wherein, the redundant storage unit includes the first storage unit and the second storage unit；First storage unit and institute
It states main array memory cells and shares trap, bit line and high address；Second storage unit and the main array memory cells are not
Share trap, bit line and high address；
The repair module, comprising:
First repairs submodule, and the access unit address information and first storage for breaking down according to are single
Member carries out first to the chip and repairs；
Second repairs submodule, if the main array is deposited after repairing submodule progress first reparation for described first
There are still the storage unit to break down in storage unit, according to there are still the access unit address information to break down and institute
The second storage unit is stated, second is carried out to the chip and is repaired.
7. device according to claim 6, which is characterized in that the test module, comprising:
It tests information and submodule is written, for test information to be written to the main array memory cells；
Information reading submodule is stored, for reading the storage letter in the main array memory cells after said write tests information
Breath；
Trouble unit determines submodule, for determining that reading failure or storage the information main array different from information is tested store list
Member is the storage unit to break down；
Address information saves submodule, for saving the access unit address information to break down into latch；Institute
The address information for stating the access unit address information to break down and the redundant storage unit in latch has mapping
Relationship.
8. device according to claim 6, which is characterized in that described first repairs as global bit line reparation；
Described second repairs submodule, comprising:
Trouble block determines sub-module, for determine it is described there are still the storage unit to break down concentrate where trouble block；
It repairs block and determines sub-module, for according to the access unit address information to break down and the redundancy in latch
The mapping relations of access unit address information, it is determining with it is described there are still the storage unit to break down corresponding second
Storage unit concentrates the reparation block at place；
Sub-module is replaced, for the reparation block to be replaced the trouble block.
9. device according to claim 8, which is characterized in that it is single that second storage unit is provided with the storage of redundancy
Member, the sub- storage unit of redundancy are used to carry out first to second storage unit to repair.
10. device according to claim 6, which is characterized in that the chip includes Nor Flash.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410251439.1A CN105448348B (en) | 2014-06-06 | 2014-06-06 | A kind of chip restorative procedure and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201410251439.1A CN105448348B (en) | 2014-06-06 | 2014-06-06 | A kind of chip restorative procedure and device |
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| CN106098103B (en) * | 2016-06-03 | 2019-10-18 | 北京兆易创新科技股份有限公司 | The replacement method of bad point unit in a kind of nonvolatile memory |
| CN110556157B (en) * | 2018-05-30 | 2021-06-22 | 北京兆易创新科技股份有限公司 | Nonvolatile semiconductor memory repairing method and device |
| KR102565920B1 (en) * | 2018-07-18 | 2023-08-11 | 에스케이하이닉스 주식회사 | Storage device and operating method thereof |
| CN110968455B (en) * | 2018-09-29 | 2024-03-29 | 嘉楠明芯(北京)科技有限公司 | Nonvolatile memory repairing method and device |
| CN109741782B (en) * | 2018-12-29 | 2020-10-16 | 西安紫光国芯半导体有限公司 | DRAM (dynamic random Access memory) repairing method |
| CN110797072B (en) * | 2019-10-31 | 2021-09-21 | 西安紫光国芯半导体有限公司 | DRAM chip repairing method |
| CN111428280B (en) * | 2020-06-09 | 2020-11-17 | 浙江大学 | SoC (System on chip) security chip key information integrity storage and error self-repairing method |
| CN112415932B (en) * | 2020-11-24 | 2023-04-25 | 海光信息技术股份有限公司 | Circuit module, driving method thereof and electronic equipment |
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| US20130215695A1 (en) * | 2009-08-12 | 2013-08-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-repairing memory |
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