CN110556157B - Nonvolatile semiconductor memory repairing method and device - Google Patents
Nonvolatile semiconductor memory repairing method and device Download PDFInfo
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- CN110556157B CN110556157B CN201810538821.9A CN201810538821A CN110556157B CN 110556157 B CN110556157 B CN 110556157B CN 201810538821 A CN201810538821 A CN 201810538821A CN 110556157 B CN110556157 B CN 110556157B
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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Abstract
The invention discloses a method and a device for repairing a nonvolatile semiconductor memory, which relate to the technical field of chip storage, and the method comprises the following steps: counting the number of bad bit lines in a to-be-repaired storage column of the target storage; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. The technical problems that the number of bad bit lines is small in the conventional nonvolatile semiconductor memory repairing mode under the condition that the number of redundant memory columns is limited, so that the redundant memory columns are wasted and the yield of the memory is reduced are solved. The method has the advantages of improving the utilization rate of the redundant memory columns in the nonvolatile semiconductor memory and improving the yield of the memory.
Description
Technical Field
The invention relates to the technical field of chip storage, in particular to a nonvolatile semiconductor memory repairing method and device.
Background
With the continuous development and progress of integrated circuit technology, the performance requirements for the yield, the service life and the like of non-volatile semiconductor memories such as Nor-Flash, Nand-Flash, EEPROM (Electrically Erasable Programmable Read-Only Memory) and the like are higher and higher. Although the manufacturing process of the memory chip is continuously improved, the nonvolatile semiconductor memory still causes some inevitable defects during the manufacturing process, wherein the defects of Bit Lines (BL) in the memory columns can cause data not to be correctly stored and read.
Therefore, some redundant columns, i.e. redundant columns (rdn columns), are reserved in the design stage of the memory, and one column (rdn) includes a plurality of bit lines. Then, when the nonvolatile semiconductor memory is detected, the defective memory column can be replaced by the redundant memory column, and the repair of the defective memory column is completed.
In the conventional repair method, repair and replacement are performed when a defective memory column is detected, regardless of the number of defective bit lines in the defective memory column. Therefore, when the number of redundant memory columns is limited, the number of defective repair bit lines is small, which results in waste of the redundant memory columns and further reduces the yield of the memory.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a nonvolatile semiconductor memory repair method and a corresponding nonvolatile semiconductor memory repair apparatus that overcome or at least partially solve the above problems.
According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory repair method including:
counting the number of bad bit lines in a to-be-repaired storage column of the target storage;
and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low.
Optionally, the step of counting the number of bad bit lines in a to-be-repaired memory column of the target memory includes:
dividing the data area of the target memory into N memory segments;
and counting the number of the bad bit lines in the to-be-repaired storage column of the storage section.
Optionally, the step of performing replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in the order from high to low in the number of the bad bit lines includes:
respectively counting the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage sections aiming at the storage sections;
and replacing and repairing the storage column to be repaired by using the redundant storage column of the target memory.
Optionally, the step of performing replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in the order from high to low in the number of the bad bit lines includes:
and replacing and repairing the to-be-repaired storage column containing at least two bad bit lines in the storage section by using the redundant storage column, and simultaneously replacing and repairing the to-be-repaired storage column containing one bad bit line appearing at the L-th position in the storage section.
Optionally, the step of performing replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in the order from high to low in the number of the bad bit lines includes:
dividing the redundant storage column into a plurality of redundant storage units by taking P bit lines as a group;
replacing and repairing the bad bit lines in the corresponding to-be-repaired storage columns through the redundant storage units according to the sequence of the number of the bad bit lines from high to low;
or, according to the sequence of the number of the bad bit lines from low to high, the bad bit lines in the corresponding to-be-repaired storage columns are replaced and repaired through the redundant storage units.
According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory repair apparatus including:
the bad bit line counting module is used for counting the number of bad bit lines in a to-be-repaired storage column of the target memory;
and the repair module is used for replacing and repairing the corresponding storage columns to be repaired through the redundant storage columns of the target memory according to the sequence of the number of the bad bit lines from high to low.
Optionally, the bad bit line statistics module comprises:
a data region partitioning module for partitioning the data region of the target memory into N memory segments;
and the bad bit line counting submodule is used for counting the number of bad bit lines in the to-be-repaired storage column of the storage section.
Optionally, the repair module includes:
the to-be-repaired storage column counting submodule is used for respectively counting the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage sections aiming at the storage sections;
and the first repair submodule is used for replacing and repairing the storage column to be repaired by using the redundant storage column of the target memory.
Optionally, the repair module includes:
and the second repair submodule is used for replacing and repairing a to-be-repaired storage column containing at least two bad bit lines in the storage segment by using the redundant storage column and simultaneously replacing and repairing an L-th to-be-repaired storage column containing one bad bit line in the storage segment.
Optionally, the repair module includes:
the redundancy storage column dividing submodule is used for dividing the redundancy storage column into a plurality of redundancy storage units by taking P bit lines as a group;
the third repair submodule is used for replacing and repairing the bad bit lines in the corresponding to-be-repaired storage columns through the redundant storage units according to the sequence of the number of the bad bit lines from high to low;
or, the fourth repair submodule is used for performing replacement repair on the bad bit lines in the corresponding to-be-repaired storage column through the redundant storage units according to the sequence from low to high of the number of the bad bit lines.
According to the nonvolatile semiconductor memory repairing method, the number of bad bit lines in a to-be-repaired storage column of a target memory can be counted; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. Therefore, the technical problems that the number of bad bit lines is small in the conventional nonvolatile semiconductor memory repairing method under the condition that the number of redundant memory columns is limited, so that the redundant memory columns are wasted and the yield of the memory is reduced are solved. The method has the advantages of improving the utilization rate of the redundant memory columns in the nonvolatile semiconductor memory and improving the yield of the memory.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 shows a flow chart of steps of a method of repairing a non-volatile semiconductor memory according to one embodiment of the invention;
FIG. 2 is a flow chart illustrating the steps of a method for repairing a non-volatile semiconductor memory according to one embodiment of the present invention;
FIG. 3 is a diagram illustrating a structure of a memory page according to an embodiment of the present invention;
FIG. 4 illustrates a schematic diagram of partitioning a data region of a memory into memory segments, according to one embodiment of the present invention;
FIG. 5 is a flow chart illustrating the steps of a method for repairing a non-volatile semiconductor memory according to one embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention;
FIG. 7 is a schematic diagram showing the structure of a nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention; and
fig. 8 is a schematic structural diagram showing a nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example one
A method for repairing a nonvolatile semiconductor memory according to an embodiment of the present invention is described in detail.
Referring to fig. 1, a flow chart of steps of a method for repairing a nonvolatile semiconductor memory according to an embodiment of the present invention is shown.
In step 110, the number of bad bit lines in the to-be-repaired memory column of the target memory is counted.
The memory column to be repaired in the target memory can be understood as a damaged memory column in the target memory which needs to be repaired. For example, a memory column with a defective bit line is a memory column to be repaired. In the embodiment of the present invention, any available method or device may be used to detect and determine the to-be-repaired memory column in the target memory, which is not limited to this embodiment of the present invention. In addition, in the embodiment of the present invention, any available method may be used to count the number of bad bit lines in the memory column to be repaired, and the embodiment of the present invention is not limited thereto. The target Memory may be any nonvolatile semiconductor Memory, such as Nor-Flash, Nand-Flash, EEPROM (Electrically Erasable Programmable Read-Only-Memory), and so on. Of course, the method for repairing a nonvolatile semiconductor memory according to the embodiment of the present invention may also be applied to other available memories, and the embodiment of the present invention is not limited thereto.
And step 120, replacing and repairing the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence from high to low of the number of the bad bit lines.
In order to improve the utilization efficiency of the redundant memory columns, if the redundant memory columns repair the defective bit lines as many as possible, the corresponding to-be-repaired memory columns can be replaced and repaired through the redundant memory columns of the target memory according to the sequence from high to low of the number of the defective bit lines in the to-be-repaired memory columns.
For example, assume that for a target memory, three of the memory ranks A, B, C to be repaired are detected. The number of defective bit lines in a is 1, the number of defective bit lines in B is 2, and the number of defective bit lines in C is 3. If three redundant storage columns are arranged in the target memory, the redundant storage columns can be used for carrying out replacement repair on a storage column C to be repaired, a storage column B to be repaired and a storage column A to be repaired in sequence; if two redundant storage columns are arranged in the target memory, the redundant storage column can be used for replacing and repairing the storage column C to be repaired and the storage column B to be repaired in sequence.
The replacement and repair can specifically replace the redundant storage column used for performing the replacement and repair with the corresponding storage column to be repaired in the target memory. For example, for the above target memory, if a redundant memory rank is used to replace and repair the to-be-repaired memory rank a, then the redundant memory rank can be used as a new memory rank a to play a role in the target memory. Specifically, the data stored in the to-be-repaired storage column a is transferred to the redundant storage column, and in the subsequent use process, the to-be-repaired storage column a is replaced by the redundant storage column, and so on.
Optionally, in an embodiment of the present invention, the step 120 further includes:
the substep 121 divides the redundant memory column into a plurality of redundant memory cells with the P bit lines as a group.
In practical applications, the redundant memory column is also formed by a bit line, and the memory column may generally include a plurality of bit lines. Individual or partial bit lines in the memory columns to be repaired are generally damaged, the number of the bad bit lines in the memory columns to be repaired is generally far less than the total number of the bit lines in the redundant memory columns, and if the memory columns to be repaired are replaced and repaired by complete redundant memory columns, the utilization rate of the bit lines in the redundant memory columns is still not high. Therefore, in the embodiment of the present invention, in order to further improve the utilization rate of the redundant memory columns, the redundant memory columns may be further divided. Specifically, the redundant storage columns in the target memory can be divided into a plurality of redundant storage units by grouping P bit lines. P may be preset according to a requirement, and the embodiment of the present invention is not limited thereto.
For example, there may be 8 bit lines in a group, or 4 bit lines in a group, or 1 bit line in a group, etc. The fewer bit lines included in the redundant memory cells, the higher the utilization rate of the redundant memory columns, and taking 1 bit line as a group as an example, each redundant memory cell can repair a bad bit line, and the utilization rate of the redundant memory columns is the highest. However, the decoding circuit is very large, which increases the area and power consumption of the target memory.
And a substep a122, performing replacement repair on the bad bit lines in the corresponding to-be-repaired memory column through the redundant memory cells according to the sequence from high to low of the number of the bad bit lines.
Or, in the substep B122, the defective bit lines in the corresponding to-be-repaired memory column are replaced and repaired through the redundant memory cells according to the sequence from low to high of the number of the defective bit lines.
After the redundant memory columns are divided, the defective bit lines in the memory columns to be repaired can be replaced and repaired by using the redundant memory cells. If the replacement repair is preferentially performed on the memory columns to be repaired, which are damaged more seriously, the defective bit lines in the corresponding memory columns to be repaired can still be replaced and repaired through the redundant memory cells according to the sequence from high to low of the number of the defective bit lines in the memory columns to be repaired. And if the aim is to repair more to-be-repaired storage columns as far as possible, at this time, the to-be-repaired storage columns with lighter damage can be repaired preferentially, and specifically, the defective bit lines in the corresponding to-be-repaired storage columns can be replaced and repaired through the redundant storage units according to the sequence from low to high of the number of the defective bit lines in each to-be-repaired storage column.
For example, for the aforementioned target memory, three of the columns of memory to repair A, B, C are detected. The number of defective bit lines in a is 1, the number of defective bit lines in B is 2, and the number of defective bit lines in C is 3. Assume that the redundant memory column in the target memory is divided into 5 redundant memory cells by using 4 bit lines as a group at this time. If the defective bit lines in the corresponding to-be-repaired storage columns are replaced and repaired through the redundant storage units according to the sequence from high to low of the number of the defective bit lines in each to-be-repaired storage column, 3 defective bit lines in the to-be-repaired storage column C can be replaced and repaired by 3 redundant storage units, and then 2 defective bit lines in the to-be-repaired storage column B can be replaced and repaired by 2 redundant storage units. And if the defective bit lines in the corresponding to-be-repaired storage columns are replaced and repaired through the redundant storage units according to the sequence that the number of the defective bit lines in each to-be-repaired storage column is from low to high, 1 defective bit line in the to-be-repaired storage column A can be replaced and repaired by 1 redundant storage unit, 2 defective bit lines in the to-be-repaired storage column B can be replaced and repaired by 2 redundant storage units, and 2 defective bit lines in the to-be-repaired storage column C can be replaced and repaired by the remaining 2 redundant storage units.
Specifically, the replacement and repair of the to-be-repaired memory rank according to the sub-step a122 or the sub-step B122 may be preset according to a requirement, which is not limited in this embodiment of the present invention. In addition, in the embodiment of the present invention, the defective bit line in the to-be-repaired memory column may also be replaced and repaired by the redundant memory cell based on other reasons, which is not limited in the embodiment of the present invention.
Moreover, in the embodiment of the present invention, if the remaining available redundant memory cells in the target memory are not enough to repair all the defective bit lines in the to-be-repaired memory column, the to-be-repaired memory column may not be set to be subjected to replacement repair, and the to-be-repaired memory column including the largest number of defective bit lines and the number of defective bit lines not greater than the number of currently remaining available redundant memory cells may be continuously repaired by using the remaining available redundant memory cells in the target memory.
For example, for a target memory, three of the columns of memory to repair A, B, C, D are detected. The number of defective bit lines in a is 1, the number of defective bit lines in B is 2, the number of defective bit lines in C is 3, and the number of defective bit lines in D is 4. Assume that the redundant memory column in the target memory is divided into 5 redundant memory cells by using 4 bit lines as a group at this time. If the defective bit lines in the corresponding to-be-repaired storage columns are replaced and repaired through the redundant storage units according to the sequence from high to low of the number of the defective bit lines in each to-be-repaired storage column, 4 defective bit lines in the to-be-repaired storage column D can be replaced and repaired by 4 redundant storage units. At this time, the remaining available redundant memory cells are 1, and 1 redundant memory cell is not enough to replace and repair all the bad bit lines in the memory columns C and B to be repaired, so that the target memory may not be repaired. And the remaining available redundant memory cells in the target memory can be used to continuously repair the to-be-repaired memory column which contains the largest number of defective bit lines and the number of defective bit lines is not more than the number of currently remaining available redundant memory cells, for example, 1 defective bit line in the to-be-repaired memory column a can be replaced and repaired by 1 currently remaining available redundant memory column.
In the embodiment of the invention, the number of the bad bit lines in the to-be-repaired storage column of the target memory can be counted; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. Therefore, the utilization rate of redundant memory columns in the nonvolatile semiconductor memory and the yield of the memory can be improved.
Moreover, in the embodiment of the present invention, the redundant memory column may be divided into a plurality of redundant memory cells by using P bit lines as a group; replacing and repairing the bad bit lines in the corresponding to-be-repaired storage columns through the redundant storage units according to the sequence of the number of the bad bit lines from high to low; or, according to the sequence of the number of the bad bit lines from low to high, the bad bit lines in the corresponding to-be-repaired storage columns are replaced and repaired through the redundant storage units. Therefore, the utilization rate of redundant storage columns in the nonvolatile semiconductor memory and the yield of the memory can be further improved.
Example two
A method for repairing a nonvolatile semiconductor memory according to an embodiment of the present invention is described in detail.
Referring to fig. 2, a flow chart of steps of a method for repairing a nonvolatile semiconductor memory according to an embodiment of the present invention is shown.
In practical applications, the memory may include at least one Page (Page), and the structure of the Page may include, as shown in fig. 3, a data area (data line), a spare area (spare line), and a redundant area (rdn/redundant line) in one Page, and may include at least one column (column) in a different storage area. When the target memory is used, the target memory is usually encoded in a segment (segment) composed of a plurality of storage columns, and in order to be more adaptive to the actual use condition of the target memory, in the embodiment of the present invention, the data area of the target memory may be divided into N segments. The specific value of N may be preset according to a requirement, and the embodiment of the present invention is not limited thereto. For example, as shown in fig. 4, the data area is divided into n memory segments, and each memory segment includes m memory columns, and one memory column may include k bit lines.
After the data area of the target memory is divided into N memory segments, the number of bad bit lines in the to-be-repaired memory column of each memory segment may be further counted, and the specific manner may be similar to the foregoing step 210, which is not described herein again.
At this time, in order to ensure that the defective rates of the memory columns in the memory segments can be relatively even, the redundant memory columns can be used to respectively replace and repair the memory columns to be repaired, which have higher defective bit lines in the memory segments. At this time, the first M to-be-repaired memory columns with the highest number of bad bit lines in each memory segment can be counted respectively for each memory segment. The value of M may be preset according to a requirement, and the embodiment of the present invention is not limited.
And 240, replacing and repairing the storage column to be repaired by using the redundant storage column of the target memory.
After the first M to-be-repaired memory columns with the highest number of bad bit lines in each memory segment are determined, the M to-be-repaired memory columns determined in each memory segment can be subjected to replacement repair by using the redundant memory columns of the target memory.
In the embodiment of the present invention, the redundant memory column may be divided into a plurality of redundant memory cells by grouping P bit lines, and the data area of the target memory may be divided into N memory segments. And then respectively counting the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage sections aiming at the storage sections. And replacing and repairing each bad bit line in the storage column to be repaired by using the redundant storage unit of the target storage.
In the embodiment of the invention, the number of the bad bit lines in the to-be-repaired storage column of the target memory can be counted; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. Therefore, the utilization rate of redundant memory columns in the nonvolatile semiconductor memory and the yield of the memory can be improved.
Moreover, in the embodiment of the present invention, the data area of the target memory may be further divided into N memory segments; and counting the number of the bad bit lines in the to-be-repaired storage column of the storage section. Respectively counting the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage sections aiming at the storage sections; and replacing and repairing the storage column to be repaired by using the redundant storage column of the target memory. Therefore, the use habit of a user on the memory can be more approached, the bad conditions of each memory segment in the memory are balanced, and the utilization rate of redundant memory columns in the memory and the yield of the memory are further improved.
EXAMPLE III
A method for repairing a nonvolatile semiconductor memory according to an embodiment of the present invention is described in detail.
Referring to fig. 5, a flowchart of steps of a method for repairing a nonvolatile semiconductor memory according to an embodiment of the present invention is shown.
At step 310, the data area of the target memory is divided into N memory segments.
In step 320, the number of bad bit lines in the to-be-repaired memory column of the memory segment is counted.
And 330, replacing and repairing the to-be-repaired storage column containing at least two bad bit lines in the storage section by using the redundant storage column, and simultaneously replacing and repairing the to-be-repaired storage column containing one bad bit line appearing at the L-th position in the storage section.
In the embodiment of the present invention, replacement repair may be performed on a to-be-repaired memory column including at least two bad bit lines in each memory column, and replacement repair may be performed on an L-th to-be-repaired memory column including one bad bit line in each memory segment. The specific value of L may be preset according to a requirement, and the embodiment of the present invention is not limited thereto.
In addition, during specific execution, the detected to-be-repaired memory columns meeting the repair condition in step 330 may be replaced and repaired while detecting the bad bit lines in each memory segment, or after completing the detection statistics of the bad bit lines in all the memory segments of the target memory, the to-be-repaired memory columns meeting the repair condition in step 330 may be replaced and repaired in a unified manner, which is not limited in the embodiment of the present invention.
In the embodiment of the invention, the number of the bad bit lines in the to-be-repaired storage column of the target memory can be counted; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. Therefore, the utilization rate of redundant memory columns in the nonvolatile semiconductor memory and the yield of the memory can be improved.
Moreover, in the embodiment of the present invention, the data area of the target memory may be further divided into N memory segments; and counting the number of the bad bit lines in the to-be-repaired storage column of the storage section. And replacing and repairing the to-be-repaired storage column containing at least two bad bit lines in the storage section by using the redundant storage column, and simultaneously replacing and repairing the to-be-repaired storage column containing one bad bit line appearing at the L-th position in the storage section. The method can also be closer to the use habit of a user on the memory, and the bad conditions of each memory segment in the memory are more balanced, so that the utilization rate of redundant memory columns in the memory and the yield of the memory are further improved.
For simplicity of explanation, the method embodiments are described as a series of acts or combinations, but those skilled in the art will appreciate that the embodiments are not limited by the order of acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the embodiments of the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no particular act is required to implement the invention.
Example four
A nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention is described in detail.
Referring to fig. 6, a schematic structural diagram of a nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention is shown. The method specifically comprises the following steps:
and a bad bit line counting module 410, configured to count the number of bad bit lines in a to-be-repaired memory column of the target memory.
And the repair module 420 is configured to perform replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in the order from high to low in the number of the bad bit lines.
Optionally, in an embodiment of the present invention, the repairing module 420 further includes:
the redundancy memory column division submodule 421 is configured to divide the redundancy memory column into a plurality of redundancy memory cells by using P bit lines as a group.
And the third repair submodule a422 is configured to perform replacement repair on the bad bit lines in the corresponding to-be-repaired memory column through the redundant memory cells in the order from high to low in the number of the bad bit lines.
Or, the fourth repair submodule B422 is configured to, according to the order from low to high of the number of the bad bit lines, perform replacement repair on the bad bit lines in the corresponding to-be-repaired memory column through the redundant memory cells.
In the embodiment of the invention, the number of the bad bit lines in the to-be-repaired storage column of the target memory can be counted; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. Therefore, the utilization rate of redundant memory columns in the nonvolatile semiconductor memory and the yield of the memory can be improved.
Moreover, in the embodiment of the present invention, the redundant memory column may be divided into a plurality of redundant memory cells by using P bit lines as a group; replacing and repairing the bad bit lines in the corresponding to-be-repaired storage columns through the redundant storage units according to the sequence of the number of the bad bit lines from high to low; or, according to the sequence of the number of the bad bit lines from low to high, the bad bit lines in the corresponding to-be-repaired storage columns are replaced and repaired through the redundant storage units. Therefore, the utilization rate of redundant storage columns in the nonvolatile semiconductor memory and the yield of the memory can be further improved.
EXAMPLE five
A nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention is described in detail.
Referring to fig. 7, a schematic structural diagram of a nonvolatile semiconductor memory repair apparatus in an embodiment of the present invention is shown. The method specifically comprises the following steps:
and a bad bit line counting module 510 for counting the number of bad bit lines in the to-be-repaired memory column of the target memory.
Optionally, in an embodiment of the present invention, the bad bit line statistics module 510 further includes:
a data region partitioning module 511, configured to partition the data region of the target memory into N memory segments.
And the bad bit line counting submodule 512 is used for counting the number of the bad bit lines in the to-be-repaired memory column of the memory segment.
And a repair module 520, configured to perform replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in an order from high to low in the number of the bad bit lines.
Optionally, in an embodiment of the present invention, the repairing module 520 further includes:
and the to-be-repaired storage column counting submodule 521 is configured to, for each storage segment, respectively count the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage segment.
And the first repair submodule 522 is configured to perform replacement repair on the to-be-repaired storage column by using the redundant storage column of the target memory.
In the embodiment of the invention, the number of the bad bit lines in the to-be-repaired storage column of the target memory can be counted; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. Therefore, the utilization rate of redundant memory columns in the nonvolatile semiconductor memory and the yield of the memory can be improved.
Moreover, in the embodiment of the present invention, the data area of the target memory may be further divided into N memory segments; and counting the number of the bad bit lines in the to-be-repaired storage column of the storage section. Respectively counting the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage sections aiming at the storage sections; and replacing and repairing the storage column to be repaired by using the redundant storage column of the target memory. Therefore, the use habit of a user on the memory can be more approached, the bad conditions of each memory segment in the memory are balanced, and the utilization rate of redundant memory columns in the memory and the yield of the memory are further improved.
EXAMPLE six
A nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention is described in detail.
Referring to fig. 8, a schematic structural diagram of a nonvolatile semiconductor memory repair apparatus according to an embodiment of the present invention is shown. The method specifically comprises the following steps:
and a bad bit line counting module 610, configured to count the number of bad bit lines in a to-be-repaired memory column of the target memory.
Optionally, in an embodiment of the present invention, the bad bit line statistics module 610 further includes:
a data region partitioning module 611 for partitioning the data region of the target memory into N memory segments.
And the bad bit line counting submodule 612 is configured to count the number of bad bit lines in the to-be-repaired memory column of the memory segment.
And a repair module 620, configured to perform replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in an order from high to low in the number of the bad bit lines.
Optionally, in an embodiment of the present invention, the repairing module 620 may further include:
the second repair submodule 621 is configured to perform replacement repair on a to-be-repaired storage column including at least two bad bit lines in the storage segment by using the redundant storage column, and perform replacement repair on an L-th to-be-repaired storage column including one bad bit line in the storage segment.
In the embodiment of the invention, the number of the bad bit lines in the to-be-repaired storage column of the target memory can be counted; and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low. Therefore, the utilization rate of redundant memory columns in the nonvolatile semiconductor memory and the yield of the memory can be improved.
Moreover, in the embodiment of the present invention, the data area of the target memory may be further divided into N memory segments; and counting the number of the bad bit lines in the to-be-repaired storage column of the storage section. And replacing and repairing the to-be-repaired storage column containing at least two bad bit lines in the storage section by using the redundant storage column, and simultaneously replacing and repairing the to-be-repaired storage column containing one bad bit line appearing at the L-th position in the storage section. The method can also be closer to the use habit of a user on the memory, and the bad conditions of each memory segment in the memory are more balanced, so that the utilization rate of redundant memory columns in the memory and the yield of the memory are further improved.
For the device embodiment, since it is basically similar to the method embodiment, the description is simple, and for the relevant points, refer to the partial description of the method embodiment.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus. Various general purpose systems may also be used with the teachings herein. The required structure for constructing such a system will be apparent from the description above. Moreover, the present invention is not directed to any particular programming language. It is appreciated that a variety of programming languages may be used to implement the teachings of the present invention as described herein, and any descriptions of specific languages are provided above to disclose the best mode of the invention.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in a non-volatile semiconductor memory repair device in accordance with embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
Claims (10)
1. A non-volatile semiconductor memory repair method, comprising:
counting the number of bad bit lines in a to-be-repaired storage column of the target storage;
and performing replacement repair on the corresponding memory columns to be repaired through the redundant memory columns of the target memory according to the sequence of the number of the bad bit lines from high to low.
2. The method of claim 1, wherein the step of counting the number of bad bit lines in the to-be-repaired memory column of the target memory comprises:
dividing the data area of the target memory into N memory segments;
and counting the number of the bad bit lines in the to-be-repaired storage column of the storage section.
3. The method according to claim 2, wherein the step of performing replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in the order from high to low of the number of the bad bit lines comprises:
respectively counting the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage sections aiming at the storage sections;
and replacing and repairing the storage column to be repaired by using the redundant storage column of the target memory.
4. The method according to claim 2, wherein the step of performing replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in the order from high to low of the number of the bad bit lines comprises:
and replacing and repairing the to-be-repaired storage column containing at least two bad bit lines in the storage section by using the redundant storage column, and simultaneously replacing and repairing the to-be-repaired storage column containing one bad bit line appearing at the L-th position in the storage section.
5. The method according to claim 1, wherein the step of performing replacement repair on the corresponding to-be-repaired memory columns through the redundant memory columns of the target memory in the order from high to low of the number of the bad bit lines comprises:
dividing the redundant storage column into a plurality of redundant storage units by taking P bit lines as a group;
and replacing and repairing the bad bit lines in the corresponding to-be-repaired storage columns through the redundant storage units according to the sequence of the number of the bad bit lines from high to low.
6. A nonvolatile semiconductor memory repair device comprising:
the bad bit line counting module is used for counting the number of bad bit lines in a to-be-repaired storage column of the target memory;
and the repair module is used for replacing and repairing the corresponding storage columns to be repaired through the redundant storage columns of the target memory according to the sequence of the number of the bad bit lines from high to low.
7. The apparatus of claim 6, wherein the bad bit line statistics module comprises:
a data region partitioning module for partitioning the data region of the target memory into N memory segments;
and the bad bit line counting submodule is used for counting the number of bad bit lines in the to-be-repaired storage column of the storage section.
8. The apparatus of claim 7, wherein the repair module comprises:
the to-be-repaired storage column counting submodule is used for respectively counting the first M to-be-repaired storage columns with the highest number of bad bit lines in the storage sections aiming at the storage sections;
and the first repair submodule is used for replacing and repairing the storage column to be repaired by using the redundant storage column of the target memory.
9. The apparatus of claim 7, wherein the repair module comprises:
and the second repair submodule is used for replacing and repairing a to-be-repaired storage column containing at least two bad bit lines in the storage segment by using the redundant storage column and simultaneously replacing and repairing an L-th to-be-repaired storage column containing one bad bit line in the storage segment.
10. The apparatus of claim 6, wherein the repair module comprises:
the redundancy storage column dividing submodule is used for dividing the redundancy storage column into a plurality of redundancy storage units by taking P bit lines as a group;
and the third repair submodule is used for replacing and repairing the bad bit lines in the corresponding to-be-repaired storage columns through the redundant storage units according to the sequence from high to low of the number of the bad bit lines.
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| US11797371B2 (en) | 2020-08-18 | 2023-10-24 | Changxin Memory Technologies, Inc. | Method and device for determining fail bit repair scheme |
| CN114078563B (en) * | 2020-08-18 | 2023-09-12 | 长鑫存储技术有限公司 | Repair method and device for failure bit |
| US11791010B2 (en) | 2020-08-18 | 2023-10-17 | Changxin Memory Technologies, Inc. | Method and device for fail bit repairing |
| US11881278B2 (en) | 2021-03-31 | 2024-01-23 | Changxin Memory Technologies, Inc. | Redundant circuit assigning method and device, apparatus and medium |
| US11791012B2 (en) | 2021-03-31 | 2023-10-17 | Changxin Memory Technologies, Inc. | Standby circuit dispatch method, apparatus, device and medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423284A (en) * | 2001-11-20 | 2003-06-11 | 松下电器产业株式会社 | Semiconductor integrated circuit comprising storage macro |
| CN101202116A (en) * | 2006-12-11 | 2008-06-18 | 三星电子株式会社 | Semiconductor memory device and method for repairing the same |
| CN102163465A (en) * | 2010-02-19 | 2011-08-24 | 三星电子株式会社 | Nonvolatile memory device and system performing repair operation for defective memory cell |
| CN103177771A (en) * | 2011-12-20 | 2013-06-26 | 财团法人工业技术研究院 | Repairable multi-layer memory chip stack and method thereof |
| CN103871450A (en) * | 2012-08-27 | 2014-06-18 | 三星电子株式会社 | Semiconductor memory device and system having redundancy cells |
| CN105448348A (en) * | 2014-06-06 | 2016-03-30 | 北京兆易创新科技股份有限公司 | Chip repair method and chip repair apparatus |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9870835B2 (en) * | 2015-03-04 | 2018-01-16 | Macronix International Co., Ltd. | Memory repairing method and memory device applying the same |
| KR102336458B1 (en) * | 2015-07-30 | 2021-12-08 | 삼성전자주식회사 | Non-volatile memory device and test system therof |
-
2018
- 2018-05-30 CN CN201810538821.9A patent/CN110556157B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423284A (en) * | 2001-11-20 | 2003-06-11 | 松下电器产业株式会社 | Semiconductor integrated circuit comprising storage macro |
| CN101202116A (en) * | 2006-12-11 | 2008-06-18 | 三星电子株式会社 | Semiconductor memory device and method for repairing the same |
| CN102163465A (en) * | 2010-02-19 | 2011-08-24 | 三星电子株式会社 | Nonvolatile memory device and system performing repair operation for defective memory cell |
| CN103177771A (en) * | 2011-12-20 | 2013-06-26 | 财团法人工业技术研究院 | Repairable multi-layer memory chip stack and method thereof |
| CN103871450A (en) * | 2012-08-27 | 2014-06-18 | 三星电子株式会社 | Semiconductor memory device and system having redundancy cells |
| CN105448348A (en) * | 2014-06-06 | 2016-03-30 | 北京兆易创新科技股份有限公司 | Chip repair method and chip repair apparatus |
Non-Patent Citations (2)
| Title |
|---|
| Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor;Brian Zimmer;《IEEE Journal of Solid-State Circuits》;20170718;2589-2600 * |
| 基于内容可寻址存储器的存储器内建自修复方法;谢远江等;《第五届中国测试学术会议论文集》;20080531;144-150 * |
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