CN105446934A - Moving-target and constant false-alarm rate detection system based on multi-core DSP - Google Patents
Moving-target and constant false-alarm rate detection system based on multi-core DSP Download PDFInfo
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Abstract
The invention brings forward a moving-target and constant false-alarm rate detection system based on a multi-core DSP.The multi-core DSP comprises a main core and more than two sub cores. In the more than two sub cores, one of sub cores is independently developed for data reception and used for responding to external interrupt and receiving radar signal data via a high speed interface. Others are developed as sub cores used for processing radar signal data. Two storage regions are developed in external DDR for the data receiving sub core and used for storing and receiving radar signal data. Two storage regions developed in each data processing sub core are used for storing received radar signal data. The moving-target and constant false-alarm rate detection system based on the multi-core DSP has following beneficial effects: problems such as high calculating complexity, time consumption of operation and poor data communication when a single-chip structure and multiple sheets of DSP are combined for processing are solved; and the system is advantaged by being fine in real-time performance, simple in structure, and high in communication efficiency and processing capability.
Description
Technical field
The invention belongs to Radar Signal Processing Technology field, specifically relate to a kind of moving-target based on multi-core DSP and CFAR detection system.
Background technology
Along with Radar Technology and with the fast development of FPGA and the DSP digital signal processing chip that is representative, Radar Signal Processing Technology have also been obtained develop rapidly.This is not only embodied in flexible, complicated radar signal form and Radar Signal Processing algorithm, is also embodied in the use of high-performance digital signal processor part and the appearance of multi-signal process framework.
Typical radar signal processor generally adopts single DSP signal processing platform, merely based on FPGA or FPGA+DSP framework now.In patent CN101561501A, describe a kind of radar target tracking recognizer based on DSP, it is advantageous that and without the need to adopting special chip in addition, be conducive to reducing production cost.But the Signal Pretreatment algorithm process data volume running into bottom is large, but the relatively simple situation of operating structure, and when requiring high situation to processing speed, the framework of single DSP has not obviously had advantage.The most frequently used is DSP+FPGA structure now, there is the advantage of two kinds of processors, take into account speed and dirigibility, and can be applied in different Radar Signal Processing System, there is very strong versatility in " a kind of realization of a radar general signal processing system and application " literary composition of " electronics technology ", describe a kind of signal transacting framework adding four DSP (TS201) based on a slice FPGA (EP2S60F1020), this framework has that versatility is good, processing power strong, data communication rates advantages of higher.But this signal processing structure has chip uses the shortcomings such as communication between many, the chip of number is complicated, PCB placement-and-routing difficulty is large.
Summary of the invention
The object of the present invention is to provide a kind of moving-target based on multi-core DSP and CFAR detection system, the problems such as the computation complexity existed when solving single-chip framework and multi-DSP Combined Treatment is high, computing is consuming time, data communication is difficult, have the advantages such as real-time is good, structure is simple, communication efficiency is high, processing power is strong.
In order to solve the problems of the technologies described above, the invention provides a kind of moving-target based on multi-core DSP and CFAR detection system, described multi-core DSP comprises a main core and plural from core, wherein:
Main core be responsible for the process control of system process radar signal, signal transmission, data-moving and tracking target information generate;
Plural from core, open up separately one from core as data receiver from core, data receiver from core be used for response external interrupt and by high-speed interface from FPGA receiving radar signal data; Other from core as data processing from core, data processing is used for the process of radar signal data from core;
Data receiver opens up two storage areas for depositing the radar signal data of reception from core among outside DDR, and each data processing opens up two storage areas for depositing the radar signal data of reception from core in oneself core.
Compared with prior art, its remarkable advantage is in the present invention: (1) is opened up separately a core and responded GPIO frequently and to interrupt and from external reception data, thus improves the execution efficiency of CPU; (2) avoid multiple core for a long time to DDR bus access, reduce the overhead that DDR bus access conflict brings; (3) intercore communication adopts the technology such as zone bit, IPC interruption, DMA data-moving simultaneously, the reliability communicated between guarantee multinuclear and rapidity; (4) store employing ping-pong structure from Nuclear Data, decrease data latency time.
Accompanying drawing explanation
Fig. 1 is the workflow diagram of main core in the present invention.
Fig. 2 be in the present invention data receiver from the workflow diagram of core.
Fig. 3 be in the present invention signal transacting from the workflow diagram of core.
Embodiment
The present invention is based on moving target detect (MTD) and CFAR detection (CFAR) system of multi-core DSP, described multi-core DSP comprises a main core and plural from core, wherein:
Main core be responsible for the process control of system process radar signal, signal transmission, data-moving and tracking target information generate, the information of tracking target comprises the information such as distance, speed;
Plural from core, open up separately one from core be specifically designed to response external interrupt and by high-speed interface (SRIO) from FPGA receiving radar signal data, namely open up separately one from core as data receiver from core; Other is used for the process of radar signal data from core, namely in radar signal data, carries out moving target detect and CFAR detection to tracking target, namely other from core as signal transacting from core;
Data receiver opens two storage areas from core among outside DDR (Double Data Rate synchronous DRAM), whole signal transacting opens up two storage areas from core in oneself core, namely comprise the first storage area and the second storage area, store to realize ping-pong structure.
Embodiment
In multi-core DSP, select seven cores to build the moving-target and the CFAR detection system that the present invention is based on multi-core DSP, wherein definite kernel 0 is main core, core 1 to core 5 as the signal transacting of process radar signal data from core, open up separately core 6 responsively external interrupt the data receiver of receiving radar signal data from core.
Composition graphs 1, the process using the present invention to carry out moving target detect and CFAR detection to tracking target in radar signal data is as follows:
The first step, carries out initialization to main core with from core.The initialization of main core core 0 comprises the configurations such as dsp system clock, DDR (Double Data Rate synchronous DRAM), IPC (intercore communication) interruption; The initialization of core 1 to core 5 comprises intercore communication zone bit initialize; The initialization of core 6 comprises SRIO initial configuration, GPIO (general purpose I/O port) interrupt configuration.Core 1 to core 6 each after core initialization completes, corresponding zone bit is drawn high, core 0 detects core 1 to core 6, and each enters into normal mode of operation after the zone bit that core initialization completes is drawn high.
Second step, after FPGA often completes a ripple radar signal data receiver, all send a GPIO rising edge look-at-me to data receiver from core core 6, core 6 just carries out a SRIO read operation after often receiving a look-at-me in break in service function, reads radar signal data and is stored in outside DDR.
Core 6 reads and the method storing radar signal data is specially: during beginning, core 6 is judging whether to receive the external interrupt signal from FPGA always, after core 6 receives first look-at-me, respond the external interrupt from FPGA, and read data by SRIO interface from outside.Core 6 judges the data of reading to be stored in the first storage area or the second storage area by the odd even of the number of times of current reception data.Such as the first wave radar signal data of reading are stored in the first storage area in outside DDR, when judging to be drawn high by its zone bit after these ripple radar signal data store, but now core 6 does not stop receive interruption data, continue to read next ripple radar signal data and the second storage area be stored in outside DDR.Circulation like this realizes ping-pong structure and stores.The size of the radar signal data volume that the every ripple of core 6 reads needs to hold storage resources to reach an agreement on according to reading rate and FPGA.Data receiver from the workflow of core core 6 as shown in Figure 2.
3rd step, in the process of carrying out step 2, after main core core 0 detects that the zone bit of core 6 is drawn high, start to carry out DMA (immediate data storage) data-moving, namely core 0 by core 6 the radar signal data be stored in outside DDR move the core memory space of each data processing of core 1 to core 5 from core successively.Detailed process is: core 0 first gives the first storage area DMA radar signal data of the core memory space of core 1 to core 5, and then give each data processing from the second storage area DMA radar signal data of the core memory space of core, realize ping-pong structure operation, main core core 0 just waits for that after starting to move radar signal data the IPC that each core of core 1 to core 5 produces after data processing completes interrupts always.Have no progeny when main core core 0 receives in IPC, judge IPC interrupts coming from which core in core 1 to core 5, and carry out radar data process to this core next wave datum DMA.When main core core 0 detect all data all by signal transacting from after core completes, carry out the determination of the information such as target range, speed from the result that core returns according to each signal transacting.The workflow diagram of main core core 0 as shown in Figure 1.
Consider the core memory space resource-constrained of core 1 to core 5, and be divided into two storage areas do ping-pong structure store, therefore when a wave datum is very large, can not by disposable for every wave datum whole DMA to each data processing from core; Meanwhile, considering that core 1 to core 5 is when doing moving target detect and CFAR detection, is independently between each range unit, and therefore, core 0, when giving data processing from core DMA data, carries out data-moving in units of range unit.In the present embodiment, core 0 each DMA is to the data of data processing from core 3 range units, data processing from core after moving target detect and CFAR detection process are carried out to the data of these 3 range units, interrupt to main core core 0 one IPC (intercore communication), require that core 0 continues the data of other 3 range units of DMA from DDR.Circulation like this until all data from outside DDR DMA to core 1 to core 5.
4th step, data processing from the workflow of core as shown in Figure 3.The each data processing of core 1 to core 5, from after core receives the data that main core core 0DMA comes, carries out moving target detect and CFAR detection process.CFAR detection process adopts CA-CFAR; a protected location is each side got at measuring point to be checked; the left survey of the protected location again in got left side and measure some points on the right side of the protected location on got right side and accumulate (taken point number is relevant with the false-alarm probability of selection); compare with signal after generating detection threshold; the value exceeding thresholding retains; be less than counting of thresholding and be set to 0, the target amplitude maximal value detected and corresponding positional information are turned back to the shared storage space of agreement by each signal transacting of core 1 to core 5 from core.If know the velocity information of the radar target of last time, owing to being the CFAR doing speed dimension, can suitably reduce speed unit CFAR detection sensing range according to the velocity information of last time.
5th step, data divide by main core core 0 in units of range unit, then can obtain total range unit number, then need the range unit number assignment of data to be processed each from core to core 5 to core 1 to core 5 is each from core core 1, then can know that core 1 provides in process DMA the number needed process from core to core 5 is each further.When main core core 0DMA data are given after 5 signal transacting all reach each self-corresponding DMA the number of each core from the number of times of core, the now data-moving work of main core core 0 completes, wait for 5 complete from core process after mark draw high.
After data processing processes all data from core, by respective result by core 1 in the shared storage space that is stored in and specifies of putting in order of core 5, and the zone bit that respective Radar Signal Processing completes is drawn high, main core core 0 detects that 5 data processings are from after the zone bit of core is all drawn high, the result of each core is read from shared storage space, the information of line trace target of going forward side by side generates, and comprises the information such as the distance of target, speed.
In order to the advantage of the present invention in computing velocity is described, use the inventive method, DSP selects TI company model to be the high-performance 8 core DSP of TMS320C6678, the FPGA that data are XC7K325T by the model of XILINX company passes to DSP by SRIO, range unit gets 59, each interrupting receive 59*32*2*4=15014 data, interrupt composition CPI packet 256 times and process, total amount of data is 59*8192*8.Be assigned to core 1 to core 5 by 59 range units, then each core distribution of core 1 to core 4 obtains 12 range unit data, and core 5 obtains 11 range unit data, and by each DMA3 range unit, then core 1 to core 5 all needs DMA4 secondary data.Process in use the inventive method, can find out from the CLOCK timing tool the CCS software of TI only needs about 5.45ms.The present invention also only carries out monokaryon process with a core under above-mentioned experimental situation, can find out that the processing time is approximately 28.67ms by CLOCK.By comparing, the present invention improves more than 5 times relative to monokaryon operation time, and the time of saving mainly comes from the frequent interruption reading of data and the realization of multinuclear algorithm.
Claims (7)
1. based on moving-target and the CFAR detection system of multi-core DSP, it is characterized in that, described multi-core DSP comprises a main core and plural from core, wherein:
Main core be responsible for the process control of system process radar signal, signal transmission, data-moving and tracking target information generate;
Plural from core, open up separately one from core as data receiver from core, data receiver from core be used for response external interrupt and by high-speed interface from FPGA receiving radar signal data; Other from core as data processing from core, data processing is used for the process of radar signal data from core;
Data receiver opens up two storage areas for depositing the radar signal data of reception from core among outside DDR, and each data processing opens up two storage areas for depositing the radar signal data of reception from core in oneself core.
2. as claimed in claim 1 based on moving-target and the CFAR detection system of multi-core DSP, it is characterized in that, use this system in radar signal data to the process that tracking target carries out moving target detect and CFAR detection to be:
Step one, carries out initialization to main core with from core, and main core initialization comprises dsp system clock, DDR, IPC interrupt configuration; Data processing comprises intercore communication zone bit initialize from core initialization; Data receiver comprises SRIO initial configuration, GPIO interrupt configuration from core initialization; All after core initialization completes, corresponding zone bit is drawn high; Normal mode of operation is entered into after the zone bit all completed from core initialization is drawn high when main core detects;
Step 2, after FPGA often completes a ripple radar signal data receiver, all send a GPIO rising edge look-at-me to data receiver from core, data receiver often receives after a look-at-me from core and just break in service function, carries out a SRIO read operation, reads radar signal data and is stored in outside DDR;
Step 3, in the process of carrying out step 2, when main core detects that data receiver is from after the zone bit of core is drawn high, main core adopts the mode of DMA data-moving that data receiver is moved the core memory space of each data processing from core successively from the core radar signal data be stored in its outside DDR;
Step 4, each data processing, from after core receives the data that main core DMA comes, is carried out moving target detect and CFAR detection process, and result is turned back to the shared storage space of agreement, then drawn high by the zone bit that respective Radar Signal Processing completes;
Step 5, after main core detects that each data processing is drawn high from the zone bit of core, reads the result of each nuclear data processing from core from the shared storage space of agreement, and the information of line trace target of going forward side by side generates.
3. as claimed in claim 2 based on moving-target and the CFAR detection system of multi-core DSP, it is characterized in that, in step 2, when after first external interrupt signal that data receiver to receive from core from FPGA, respond this external interrupt, and read data by SRIO interface from outside; The first wave radar signal data of reading are first stored in the first storage area outside DDR by data receiver from core, after these ripple radar signal data store, its zone bit is drawn high, but do not stop receive interruption data, continue to read next ripple radar signal data and the second storage area be stored in outside DDR.
4. as claimed in claim 2 based on moving-target and the CFAR detection system of multi-core DSP, it is characterized in that, in step 3, main core first gives each data processing from the first storage area DMA radar signal data of the core memory space of core, and then gives each data processing from the second storage area DMA radar signal data of the core memory space of core; Main core just waits for that after starting to move radar signal data the IPC that each data processing produces after data processing completes from core interrupts always; Main core one receives one of them data processing and has no progeny from the IPC of core, just gives this data processing from core next wave datum DMA.
5. as claimed in claim 2 based on moving-target and the CFAR detection system of multi-core DSP, it is characterized in that, in step 3, main core, when giving data processing from core DMA data, carries out data-moving in units of range unit.
6. as claimed in claim 2 based on moving-target and the CFAR detection system of multi-core DSP; it is characterized in that; in step 4; CFAR detection process adopts CA-CFAR; a protected location is each side got at measuring point to be checked, the more left survey of protected location in got left side and measure some points on the right side of the protected location on got right side and accumulate, compare with signal after generating detection threshold; the value exceeding thresholding retains, and is less than counting of thresholding and is set to 0.
7. as claimed in claim 2 based on moving-target and the CFAR detection system of multi-core DSP, it is characterized in that, in step 5, from the number of times of core, main core judges whether data-moving work completes to each data processing according to its DMA data.
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107193230A (en) * | 2017-05-10 | 2017-09-22 | 合肥晟泰克汽车电子股份有限公司 | Car radar signal processing system and method |
| CN107885585A (en) * | 2016-09-30 | 2018-04-06 | 罗伯特·博世有限公司 | A kind of dynamic task scheduling device in multinuclear electronic control unit |
| CN108717187A (en) * | 2018-05-23 | 2018-10-30 | 桂林电子科技大学 | Based on multinuclear digital signal processor through-wall radar motion target tracking imaging method |
| CN109324995A (en) * | 2018-08-24 | 2019-02-12 | 江西洪都航空工业集团有限责任公司 | A method of configuration DSP initialization |
| CN109587484A (en) * | 2017-09-28 | 2019-04-05 | 北京航空航天大学 | Multi-mode HEVC Video Encoder Design method based on biplate DSP |
| CN111830478A (en) * | 2020-07-08 | 2020-10-27 | 哈尔滨工程大学 | FPGA (field programmable Gate array) implementation method for MTD (maximum Transmission Difference) processing of LFMCW (Linear frequency modulation and continuous phase) radar |
| CN111858457A (en) * | 2020-07-15 | 2020-10-30 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
| CN113281709A (en) * | 2021-04-21 | 2021-08-20 | 中国海洋大学 | Radar performance evaluation method based on area coupling forecasting system |
| CN113325398A (en) * | 2021-05-13 | 2021-08-31 | 英博超算(南京)科技有限公司 | Multi-core communication system of ultrasonic radar and use method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101561501A (en) * | 2009-05-13 | 2009-10-21 | 天津理工大学 | Radar target tracking recognizer based on DSP |
| US20110273325A1 (en) * | 2010-05-07 | 2011-11-10 | U.S. Government as represented by the Secreatry of the Army | Radar system and antenna with delay lines and method thereof |
-
2014
- 2014-08-14 CN CN201410401783.4A patent/CN105446934B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101561501A (en) * | 2009-05-13 | 2009-10-21 | 天津理工大学 | Radar target tracking recognizer based on DSP |
| US20110273325A1 (en) * | 2010-05-07 | 2011-11-10 | U.S. Government as represented by the Secreatry of the Army | Radar system and antenna with delay lines and method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 曹阳: "基于6678多核DSP的相位编码雷达信号处理", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
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| CN107193230A (en) * | 2017-05-10 | 2017-09-22 | 合肥晟泰克汽车电子股份有限公司 | Car radar signal processing system and method |
| CN109587484A (en) * | 2017-09-28 | 2019-04-05 | 北京航空航天大学 | Multi-mode HEVC Video Encoder Design method based on biplate DSP |
| CN109587484B (en) * | 2017-09-28 | 2021-04-27 | 北京航空航天大学 | Multi-mode HEVC video encoder design method based on double-chip DSP |
| CN108717187A (en) * | 2018-05-23 | 2018-10-30 | 桂林电子科技大学 | Based on multinuclear digital signal processor through-wall radar motion target tracking imaging method |
| CN109324995A (en) * | 2018-08-24 | 2019-02-12 | 江西洪都航空工业集团有限责任公司 | A method of configuration DSP initialization |
| CN111830478A (en) * | 2020-07-08 | 2020-10-27 | 哈尔滨工程大学 | FPGA (field programmable Gate array) implementation method for MTD (maximum Transmission Difference) processing of LFMCW (Linear frequency modulation and continuous phase) radar |
| CN111830478B (en) * | 2020-07-08 | 2022-06-17 | 哈尔滨工程大学 | FPGA (field programmable Gate array) implementation method for MTD (maximum Transmission Difference) processing of LFMCW (Linear frequency modulation and continuous phase) radar |
| CN111858457A (en) * | 2020-07-15 | 2020-10-30 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
| CN111858457B (en) * | 2020-07-15 | 2023-01-10 | 苏州浪潮智能科技有限公司 | Data processing method, device and system and FPGA |
| CN113281709A (en) * | 2021-04-21 | 2021-08-20 | 中国海洋大学 | Radar performance evaluation method based on area coupling forecasting system |
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