CN106484642A - A kind of direct memory access controller with operational capability - Google Patents
A kind of direct memory access controller with operational capability Download PDFInfo
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- CN106484642A CN106484642A CN201610879937.XA CN201610879937A CN106484642A CN 106484642 A CN106484642 A CN 106484642A CN 201610879937 A CN201610879937 A CN 201610879937A CN 106484642 A CN106484642 A CN 106484642A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The present invention relates to field of data search, more particularly, to a kind of direct memory access controller, including a data/address bus, an address bus and hardware computational unit, hardware computational unit is connected with data/address bus and address bus respectively, calculation process can be carried out to the data through direct memory access controller, direct memory access controller is made to possess calculation function, range of application is more extensive.
Description
Technical field
The present invention relates to field of data search, more particularly, to a kind of direct memory access controller.
Background technology
DMA（Direct Memory Access, direct memory access）Controller be a kind of be used in internal storage it
Between, between inside and outside memorizer, carry out the peripheral hardware of data exchange between various standard peripherals and memorizer.A kind of simple
Dma controller structure is as shown in Figure 1, including an address bus, a data bus, enumerator, the first depositor and interruption
Module.Enumerator is used for depositing the address calculating for exchange data.First depositor is used for the data of temporary transmission every time, in
Disconnected module is used for applying for bus control right to CPU or MCU or returns interruption report.Dma controller passes through address bus
Data bus is carried out during data exchange it is not necessary to through central processing unit or microcontroller, therefore just eliminate CPU or MCU
Instruction fetch, fetch data, send data etc. operate.In data transfer procedure, there is no a saving scene, the operation of restoring scene etc,
So it is more a lot of soon than CPU or MCU speed with dma controller moving data.And, during DMA moving data, CPU or
Person MCU can also do other thing, thus substantially increases the efficiency of CPU or MCU.
But, traditional dma controller does not often have the arithmetical operation of CPU or MCU and the ability of relational calculus.
Content of the invention
For the problems referred to above, the present invention proposes a kind of direct memory access controller, including：
One data/address bus and an address bus；
Hardware computational unit, is connected with described data/address bus and described address bus respectively, and described hardware computational unit is to process
The data of described direct memory access controller carries out calculation process.
Above-mentioned direct memory access controller, wherein, described hardware computational unit includes：
First EBI, is connected with described data/address bus；
Second EBI, is connected with described address bus；
Arithmetical operation module, is connected with described first EBI, with by described first EBI and described data/address bus
Carry out data transmission；
Described arithmetical operation module is also connected with described second EBI, with by described second EBI in described address
Address is searched on bus；
Described arithmetical operation module is used for carrying out arithmetical operation to the data receiving；
Relational calculus module, is connected with described first EBI, with by described first EBI and described data/address bus
Carry out data transmission；
Described relational calculus module is also connected with described second EBI, with by described second EBI in described address
Address is searched on bus；
Described relational calculus module is used for carrying out relational calculus to the data receiving.
Above-mentioned direct memory access controller, wherein, described hardware computational unit also includes：
First depositor, is respectively connecting at described first EBI and described second EBI, for supplying user input
Configuration-direct, is configured with the mode of operation to described hardware computational unit.
Above-mentioned direct memory access controller, wherein, described arithmetical operation module has execution first kind computing
Function.
Above-mentioned direct memory access controller, wherein, described first kind computing includes adding computing and subtracts computing, each
Described plus computing or described subtract computing and all control complete within a clock cycle.
Above-mentioned direct memory access controller, wherein, described arithmetical operation module has execution Equations of The Second Kind computing
Function.
Above-mentioned direct memory access controller, wherein, described Equations of The Second Kind computing includes multiplication, division operation and delivery
Computing, each described multiplication or division operation or described modulo operation all control and complete within N number of clock cycle, and N is scalable
A preset value, and N >=2, N is positive integer.
Above-mentioned direct memory access controller, wherein, described relational calculus module have execution more than relational calculus,
Equal to relational calculus, it is less than relational calculus, is more than or equal to relational calculus, is less than or equal to relational calculus and is not equal to relational calculus
Function.
Above-mentioned direct memory access controller, also includes a data buffer register；Described data buffer register
It is connected with the external equipment outside described data/address bus and described direct memory access controller respectively, be used for being temporarily stored in institute
State the data of transmission between external equipment and described data/address bus；
Described data buffer register includes one first deposit unit and one second deposit unit；
Described first deposit unit is connected with described data/address bus and described external equipment respectively, and described second deposit unit
It is connected with described data/address bus and described external equipment respectively so that described data/address bus is double to described first register memory storage
Ping-pong operation is supported in keyword or double order.
Beneficial effect：A kind of direct memory access controller proposed by the present invention has calculation function, and range of application is more
Plus extensively.
Brief description
Fig. 1 is the structural representation of existing direct memory access controller；
Fig. 2 is the structural representation of direct memory access controller in one embodiment of the invention；
Fig. 3 is the structural representation of hardware computational unit in one embodiment of the invention；
Fig. 4 is the clock cycle figure of plus and minus calculation in one embodiment of the invention；
Fig. 5 is the clock cycle figure of multiplication and division modulo operation in one embodiment of the invention；
Fig. 6 is the clock cycle figure of table tennis computing in one embodiment of the invention.
Specific embodiment
With reference to the accompanying drawings and examples the present invention is further described.
In a preferred embodiment, as shown in Figure 2 it is proposed that a kind of direct memory access controller 200, permissible
Including：
One data/address bus and an address bus；
Hardware computational unit 210, can be connected with data/address bus and address bus, hardware computational unit 210 can be to warp respectively
The data crossing direct memory access controller 200 carries out calculation process.
Wherein, data buffer register 220, interrupt module can also be included in this direct memory access controller 200
240th, enumerator 250, interrupt module 240 can be used for sending interrupt requests to system bus, and enumerator 250 can be used for depositing
Calculate the address of the exchange data needing；Data buffer register 220 can be connected with data/address bus, for temporal data bus
On data；Data buffer register 220 can also be connected with external equipment 230, be used for being temporarily stored in data/address bus and outside sets
The data of transmission between standby 230；Preferably, data buffer register 220 can also be directly connected to hardware computational unit 210,
With transmission data direct between data buffer register 220 and hardware computational unit 210 and/or order.
In a preferred embodiment, as shown in figure 3, hardware computational unit 300 can include：
First EBI 311, can be connected with data/address bus；
Second EBI 312, can be connected with address bus；
Arithmetical operation module 320, can be connected with the first EBI 311, with by the first EBI 311 and data/address bus
Carry out data transmission；
Arithmetical operation module 320 can also be connected with the second EBI, with by the second EBI 312 on address bus
Search address；
Arithmetical operation module 320 can be used for carrying out arithmetical operation to the data receiving；
Relational calculus module 330, can be connected with the first EBI 311, with by the first EBI 311 and data/address bus
Carry out data transmission；
Relational calculus module 330 can also be connected with the second EBI 312, with total in address by the second EBI 312
Address is searched on line；
Relational calculus module 330 can be used for carrying out relational calculus to the data receiving.
It is preferable that as shown in figure 3, hardware computational unit 300 can also include in above-described embodiment：
Configuration register 340, can be respectively connecting at the first EBI 311 and the second EBI 312, can be used for supplying
User input configuration-direct, is configured with the mode of operation to hardware computational unit 300.
It is preferable that arithmetical operation module can have the function of execution first kind computing in above-described embodiment.
It is preferable that as shown in figure 4, first kind computing can include adding computing and subtract computing, each adds in above-described embodiment
Computing or subtract computing and all control and complete within a clock cycle.
It is preferable that arithmetical operation module can have the function of execution Equations of The Second Kind computing in above-described embodiment.
It is preferable that as shown in figure 5, Equations of The Second Kind computing can include multiplication, division operation and delivery fortune in above-described embodiment
Calculate, each multiplication or division operation or modulo operation all control and complete within N number of clock cycle, N is an adjustable preset value,
And N >=2, N is positive integer.
In a preferred embodiment, relational calculus module have execution more than relational calculus, be equal to relational calculus, little
In relational calculus, it is more than or equal to relational calculus, is less than or equal to relational calculus and the function of being not equal to relational calculus.
In a preferred embodiment, this direct memory access controller can also include a data buffer
Device；Data buffer register can respectively with the external equipment outside data/address bus and direct memory access controller even
Connect, for being temporarily stored in the data of transmission between external equipment and data/address bus；
Data buffer register can include one first deposit unit and one second deposit unit；First deposit unit respectively with number
Connect according to bus and external equipment, and the second deposit unit is connected so that data is total with data/address bus and external equipment respectively
Line supports ping-pong operation to the first register memory double keywords of storage or double order.
Specifically, this ping-pong operation can be for example double keywords to be split as the first keyword and the second keyword, the
First keyword is stored in the first deposit unit by one step, and the second keyword is stored in the second deposit unit and by by second step
The first keyword output in one deposit unit, follow-up storing step the like.Direct memory access in the present invention
Controller can be considered as a kind of Smart dma controller, and process is taken advantage of, and removes, and needs multiple DMA clock cycle during modulo operation,
When realizing rnultidock cycle computing in the present invention, set using software programming.User's posting in hardware computational unit in advance
Suitable value is set, then hardware computational unit is taken advantage of in process, removes, during modulo operation, according to the value setting, hardware meter in storage
Calculate unit and can calculate data within the corresponding clock cycle.
In the present invention, the relational calculus function embodiment of hardware computational unit exists, when data input or output, Smart DMA
Relational calculus module in controller hardware computing unit is according to the data of input or output, and needs to deposit or read data
Address, judges this data the need of transmission, and judges the address needing to access.
Data, through Smart dma controller, sends system bus to or is destined to inside or outer in the present invention
During portion's equipment, the transmission of data is as shown in Figure 6 by the way of ping-pong operation.When data transmits through Smart dma controller
When, first DMA clock cycle, first data buffer storage in the first depositor 1.Second DMA clock cycle, by
Data in one depositor 1 is sent in hardware computational unit and processes, simultaneously by next data buffer storage to the first depositor 2
In.The 3rd DMA clock cycle, the data in the first depositor 2 is sent in hardware computational unit and processes, will simultaneously
Next data buffer storage in data register 1, circular treatment successively.
In sum, the present invention proposes a kind of direct memory access controller, total including a data/address bus, an address
Line and hardware computational unit, hardware computational unit is connected with data/address bus and address bus respectively, can be to through direct storage
The data of device access controller carries out calculation process, and range of application is more extensive.
By explanation and accompanying drawing, give the exemplary embodiments of the ad hoc structure of specific embodiment, based on present invention essence
God, also can make other conversions.Although foregoing invention proposes existing preferred embodiment, however, these contents are not intended as
Limitation.
For a person skilled in the art, after reading described above, various changes and modifications undoubtedly will be evident that.
Therefore, appending claims should regard whole variations and modifications of the true intention covering the present invention and scope as.In power
In the range of sharp claim, any and all scope of equal value and content, are all considered as still belonging to the intent and scope of the invention.
Claims (9)
1. a kind of direct memory access controller is it is characterised in that include：
One data/address bus and an address bus；
Hardware computational unit, is connected with described data/address bus and described address bus respectively, and described hardware computational unit is to process
The data of described direct memory access controller carries out calculation process.
2. direct memory access controller according to claim 1 is it is characterised in that described hardware computational unit bag
Include：
First EBI, is connected with described data/address bus；
Second EBI, is connected with described address bus；
Arithmetical operation module, is connected with described first EBI, with by described first EBI and described data/address bus
Carry out data transmission；
Described arithmetical operation module is also connected with described second EBI, with by described second EBI in described address
Address is searched on bus；
Described arithmetical operation module is used for carrying out arithmetical operation to the data receiving；
Relational calculus module, is connected with described first EBI, with by described first EBI and described data/address bus
Carry out data transmission；
Described relational calculus module is also connected with described second EBI, with by described second EBI in described address
Address is searched on bus；
Described relational calculus module is used for carrying out relational calculus to the data receiving.
3. direct memory access controller according to claim 2 is it is characterised in that described hardware computational unit also wraps
Include：
Configuration register, is respectively connecting at described first EBI and described second EBI, for supplying user input
Configuration-direct, is configured with the mode of operation to described hardware computational unit.
4. direct memory access controller according to claim 2 is it is characterised in that described arithmetical operation module has
The function of execution first kind computing.
5. direct memory access controller according to claim 4 is it is characterised in that described first kind computing includes adding
Computing and subtract computing, each described plus computing or described subtract computing and all control complete within a clock cycle.
6. direct memory access controller according to claim 2 is it is characterised in that described arithmetical operation module has
The function of execution Equations of The Second Kind computing.
7. direct memory access controller according to claim 6 is it is characterised in that described Equations of The Second Kind computing includes taking advantage of
Computing, division operation and modulo operation, each described multiplication or division operation or described modulo operation all controlled in N number of clock cycle
Inside complete, N is an adjustable preset value, and N >=2, N is positive integer.
8. direct memory access controller according to claim 2 is it is characterised in that described relational calculus module has
Execution is more than relational calculus, is equal to relational calculus, is less than relational calculus, is more than or equal to relational calculus, is less than or equal to relational calculus
With the function of being not equal to relational calculus.
9. direct memory access controller according to claim 1, also includes a data buffer register；Its feature exists
In, described data buffer register respectively with outside described data/address bus and described direct memory access controller outside
Equipment connects, for being temporarily stored in the data of transmission between described external equipment and described data/address bus；
Described data buffer register includes one first deposit unit and one second deposit unit；
Described first deposit unit is connected with described data/address bus and described external equipment respectively, and described second deposit unit
It is connected with described data/address bus and described external equipment respectively so that described data/address bus is double to described first register memory storage
Ping-pong operation is supported in keyword or double order.
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| CN201610879937.XA CN106484642B (en) | 2016-10-09 | 2016-10-09 | Direct memory access controller with operation capability |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108388527A (en) * | 2018-02-02 | 2018-08-10 | 上海兆芯集成电路有限公司 | Direct memory access (DMA) engine and its method |
| CN108885714A (en) * | 2017-11-30 | 2018-11-23 | 深圳市大疆创新科技有限公司 | The control method of computing unit, computing system and computing unit |
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| US6185634B1 (en) * | 1996-09-27 | 2001-02-06 | Emc Corporation | Address triggered DMA controller with an indicative signal including circuitry for calculating a new trigger address value based on the sum of the current trigger address and the descriptor register data with a trigger address register |
| CN101303677B (en) * | 2008-05-04 | 2010-06-02 | 华为技术有限公司 | Method and system for controlling accessing direct memory as well as controller |
| CN102222316A (en) * | 2011-06-22 | 2011-10-19 | 北京航天自动控制研究所 | Double-buffer ping-bang parallel-structure image processing optimization method based on DMA (direct memory access) |
| CN104133790A (en) * | 2013-03-14 | 2014-11-05 | 英飞凌科技股份有限公司 | Conditional links for direct memory access controllers |
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| US6185634B1 (en) * | 1996-09-27 | 2001-02-06 | Emc Corporation | Address triggered DMA controller with an indicative signal including circuitry for calculating a new trigger address value based on the sum of the current trigger address and the descriptor register data with a trigger address register |
| CN101303677B (en) * | 2008-05-04 | 2010-06-02 | 华为技术有限公司 | Method and system for controlling accessing direct memory as well as controller |
| CN102222316A (en) * | 2011-06-22 | 2011-10-19 | 北京航天自动控制研究所 | Double-buffer ping-bang parallel-structure image processing optimization method based on DMA (direct memory access) |
| CN104133790A (en) * | 2013-03-14 | 2014-11-05 | 英飞凌科技股份有限公司 | Conditional links for direct memory access controllers |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108885714A (en) * | 2017-11-30 | 2018-11-23 | 深圳市大疆创新科技有限公司 | The control method of computing unit, computing system and computing unit |
| WO2019104639A1 (en) * | 2017-11-30 | 2019-06-06 | 深圳市大疆创新科技有限公司 | Calculation unit, calculation system and control method for calculation unit |
| CN108388527A (en) * | 2018-02-02 | 2018-08-10 | 上海兆芯集成电路有限公司 | Direct memory access (DMA) engine and its method |
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