CN105430413A - Four-block hardware scanning method applicable for integer motion estimation in HEVC (High Efficiency Video Coding) standard - Google Patents
Four-block hardware scanning method applicable for integer motion estimation in HEVC (High Efficiency Video Coding) standard Download PDFInfo
- Publication number
- CN105430413A CN105430413A CN201510787964.XA CN201510787964A CN105430413A CN 105430413 A CN105430413 A CN 105430413A CN 201510787964 A CN201510787964 A CN 201510787964A CN 105430413 A CN105430413 A CN 105430413A
- Authority
- CN
- China
- Prior art keywords
- scanning
- piecemeal
- reference pixel
- pixel
- raster scan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention belongs to the technical field of high-definition digital video compression coding and decoding, and particularly discloses a four-block hardware scanning method applicable for integer motion estimation in an HEVC (High Efficiency Video Coding) standard. The four-block hardware scanning method applicable for the integer motion estimation in the HEVC standard comprises the steps of firstly segmenting an image processing block which is 64*64 in size into four 16*64 blocks and then performing raster scanning in sequence, wherein the raster scanning process is to scan according to a zigzag mode, that is to say, to start scanning from a first pixel in a horizontal (vertical) direction until the scanning reaches to a border; and the direction is called as the raster scanning direction; then translating a pixel in a direction which is vertical to the raster scanning direction, and then scanning again according to the raster scanning direction until the scanning reaches to the border; and repeating the process until the translation also reaches to the border. Through such the four-block scanning, the integer motion estimation under the HEVC standard can be finished by using a relatively small number of registers.
Description
Technical field
The invention belongs to high-definition digital video compression coding and decoding technical field, be specially a kind of four piecemeal hardware scanning methods being applicable to integer estimation in HEVC standard.
Background technology
HEVC(HighEfficiencyVideoCoding) be the video encoding and decoding standard of future generation organizing JCTVC to propose of being combined establishment by International Telecommunication Union (ITU) and Motion Picture Experts Group (MPEG).Target is under the prerequisite of identical visual effect, and compared to previous generation standard, i.e. H.264/AVC standard, compression ratio doubles.
Based on the video encoder of HEVC, form primarily of with lower module: infra-frame prediction, inter prediction, conversion, quantification, inverse quantization, inverse transformation, reconstruction, deblocking filter, the compensation of self adaptation sampling point etc.Wherein, inter prediction utilizes the correlation in consecutive frame between pixel, takes integer estimation, and fraction movement is estimated, a series of mode such as motion compensation, to reduce temporal redundancy, thus reaches the effect of compression.Due in HEVC, the maximum coding units (LCU) of image processing block has reached 64 × 64 pieces, therefore, if according to commonsense method scanned image block, will need very many registers in hardware processor.
In the process of interframe encode, need in the contiguous frames search block of pixels comparatively close on pixel value with current pixel block, and the relative displacement both drawing on locus.This relative displacement is exactly motion vector, and the process of search is exactly estimation.Under HEVC standard, the size of image processing block (LCU) can be one 64 × 64 pieces, each image processing block (LCU) can be divided into the predicting unit (PU) that the degree of depth is at most 3, and each predicting unit will have at least one motion vector according to its predictive mode adopted.This proposes very large challenge for how reducing the quantity of register on sheet.In order to tackle this challenge, the present invention proposes hardware scanning method image processing block (LCU) being divided into four pieces.By four such blocked scans, the present invention can complete the integer estimation under HEVC standard with lower register number.
Summary of the invention
The object of the invention is to propose a kind of four piecemeal hardware scanning methods that can overcome prior art deficiency, that effectively can be applicable to integer estimation in HEVC standard.
The present invention proposes the four piecemeal hardware scanning methods being applicable to integer estimation in HEVC standard, is first that the image processing block (LCU) of 64 × 64 is divided into 4 16 × 64 pieces by size, thus carries out raster scan successively.
Wherein, length be 16 limit should be parallel to the direction of raster scan, length be 64 limit should perpendicular to the direction of raster scan.Described raster scan procedures is: scan according to zigzag mode, namely from the 1st pixel to scan the direction of level (or vertical), until arrive border, this direction is referred to as the direction of raster scan; Then, to direction translation 1 pixel perpendicular to raster scan, again scan according to the direction of raster scan, until arrive border; Repeat said process, until translation also reaches border.
It should be noted that and always first completed the scanning for first piecemeal each, then complete the scanning for second piecemeal before direction translation 1 pixel perpendicular to raster scan, until the 4th piecemeal, whole process as shown in Figure 1.
In the process of scanning, reference pixel and original pixels are stored in two sizes separately and are all in the systolic arrays of 16 × 64
(an array stores original pixels, another array stores reference pixel).When each switching search piecemeal, the systolic arrays corresponding to original pixels all should read in the data of new piecemeal.And in the search procedure for current piecemeal, systolic arrays corresponding to reference pixel all should read in the data of a new row perpendicular to scanning direction, and by original reference pixel opposite direction translation pixel to scanning direction, thus forming new reference pixel block in the mode of saving bandwidth most, whole process is as shown in Figure 2.
The data of two fluctuation arrays, after computing, can obtain the difference of this original pixels block and reference pixel block.That this computing can select the difference of two squares according to system for the requirement of performance and (SSD), absolute difference and (SAD) etc.
Scanning block is divided into the scan mode of four pieces by the present invention, can reduce the size of systolic arrays in a large number, thus reduces the number of register on sheet.
Accompanying drawing explanation
Fig. 1: the four blocked scan orders that the present invention proposes.
Fig. 2: the Data Update of systolic arrays.
Fig. 3: the piecemeal of image processing block.
Embodiment
Below by example, specifically describe the inventive method further.
Suppose that hunting zone is [-11,12], so the size of reference pixel block should be 88 × 88, i.e. 64+24.Make the upper left corner of reference pixel block be initial point, level is to the right positive transverse axis, is the positive longitudinal axis vertically downward, and supposes that raster scan direction is for vertically downward.Once according to moment simulation search process.
In the moment 0, two systolic arrayses read in original pixels and reference pixel respectively.This original pixels block is positioned at the top of present image processing block (LCU), is denoted as piecemeal 1, as shown in Figure 3.The upper left corner of reference pixel is then positioned at coordinate (0,0), and its horizontal length is 64, and vertical length is 16.Now, hardware processor can according to the numerical value of two systolic arrayses with the difference of two squares and (SSD), absolute difference and the mode such as (SAD) calculate both difference.
In the moment 1, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,1), and herein, 0 is abscissa, and 1 is ordinate, lower same.
In the moment 2, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,2).
……。
In the moment 24, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,24).
The line of 1 is labeled as in moment 0-24 corresponding diagram 1.
In the moment 25, upgrade the original pixels in systolic arrays and reference pixel.After renewal, this original pixels block is updated to piecemeal 2; The upper left corner of reference pixel is positioned at coordinate (0,16).
In the moment 26, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,17).
In the moment 27, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,18).
……。
In the moment 49, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,40).
The line of 2 is labeled as in moment 25-49 corresponding diagram 1.
In the moment 50, upgrade the original pixels in systolic arrays and reference pixel.After renewal, this original pixels block is updated to piecemeal 3; The upper left corner of reference pixel is positioned at coordinate (0,32).
In the moment 51, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,33).
In the moment 52, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,34).
……。
In the moment 74, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,56).
The line of 3 is labeled as in moment 50-74 corresponding diagram 1.
In the moment 75, upgrade the original pixels in systolic arrays and reference pixel.After renewal, this original pixels block is updated to piecemeal 4; The upper left corner of reference pixel is positioned at coordinate (0,48).
In the moment 76, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,49).
In the moment 77, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,50).
……。
In the moment 99, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (0,72).
The line of 4 is labeled as in moment 75-99 corresponding diagram 1.
In the moment 100, upgrade the original pixels in systolic arrays and reference pixel.After renewal, this original pixels block is updated to piecemeal 1; The upper left corner of reference pixel is positioned at coordinate (1,0).
In the moment 101, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (1,1).
In the moment 102, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (1,50).
……。
In the moment 124, keep the original pixels in systolic arrays constant, upgrade the reference pixel in systolic arrays.After renewal, the upper left corner of reference pixel is positioned at coordinate (1,72).
The line of 5 is labeled as in moment 100-124 corresponding diagram 1.
……。
Perform until the end of scan according to said process scanning, that is execute in Fig. 1 the line being labeled as 100.
Claims (4)
1. be applicable to four piecemeal hardware scanning methods of integer estimation in HEVC standard, it is characterized in that, be first that the image processing block of 64 × 64 is divided into 4 16 × 64 pieces by size, thus carry out raster scan successively;
Wherein, length be 16 limit should be parallel to the direction of raster scan, length be 64 limit should perpendicular to the direction of raster scan; Described raster scan scans according to zigzag mode, namely from the 1st pixel to scan the direction of level (or vertical), until arrive border, this direction is referred to as the direction of raster scan; Then, to direction translation 1 pixel perpendicular to raster scan, again scan according to the direction of raster scan, until arrive border; Repeat said process, until translation also reaches border.
2. the four piecemeal hardware scanning methods being applicable to integer estimation in HEVC standard according to claim 1, it is characterized in that, each to before direction translation 1 pixel perpendicular to raster scan, always first complete the scanning for first piecemeal, complete the scanning for second piecemeal again, until the 4th piecemeal.
3. the four piecemeal hardware scanning methods being applicable to integer estimation in HEVC standard according to claim 1, is characterized in that, in the process of scanning, reference pixel and original pixels are stored in two sizes separately and are all in the systolic arrays of 16 × 64; When each switching search piecemeal, the systolic arrays corresponding to original pixels all reads in the data of new piecemeal; And in the search procedure for current piecemeal, systolic arrays corresponding to reference pixel all reads in the data of a new row perpendicular to scanning direction, and by original reference pixel opposite direction translation pixel to scanning direction, thus form new reference pixel block in the mode of saving bandwidth most.
4. the four piecemeal hardware scanning methods being applicable to integer estimation in HEVC standard according to claim 1, it is characterized in that, the data of two fluctuation arrays are after computing, obtain the difference of this original pixels block and reference pixel block, this difference be the difference of two squares and, or absolute difference and.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510787964.XA CN105430413B (en) | 2015-11-17 | 2015-11-17 | A kind of four piecemeal hardware scanning methods of the integer estimation suitable for HEVC standard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510787964.XA CN105430413B (en) | 2015-11-17 | 2015-11-17 | A kind of four piecemeal hardware scanning methods of the integer estimation suitable for HEVC standard |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105430413A true CN105430413A (en) | 2016-03-23 |
| CN105430413B CN105430413B (en) | 2018-12-11 |
Family
ID=55508298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510787964.XA Active CN105430413B (en) | 2015-11-17 | 2015-11-17 | A kind of four piecemeal hardware scanning methods of the integer estimation suitable for HEVC standard |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105430413B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107169968A (en) * | 2017-03-23 | 2017-09-15 | 天津理工大学 | A kind of image block and processing method based on raster scanning principle |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080126278A1 (en) * | 2006-11-29 | 2008-05-29 | Alexander Bronstein | Parallel processing motion estimation for H.264 video codec |
| CN101951521A (en) * | 2010-10-30 | 2011-01-19 | 上海交通大学 | Video image motion estimation method for extent variable block |
| US20110293012A1 (en) * | 2010-05-27 | 2011-12-01 | The Hong Kong University Of Science And Technology | Motion estimation of images |
| CN102647594A (en) * | 2012-04-18 | 2012-08-22 | 北京大学 | Integer pixel precision motion estimation method and system for same |
-
2015
- 2015-11-17 CN CN201510787964.XA patent/CN105430413B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080126278A1 (en) * | 2006-11-29 | 2008-05-29 | Alexander Bronstein | Parallel processing motion estimation for H.264 video codec |
| US20110293012A1 (en) * | 2010-05-27 | 2011-12-01 | The Hong Kong University Of Science And Technology | Motion estimation of images |
| CN101951521A (en) * | 2010-10-30 | 2011-01-19 | 上海交通大学 | Video image motion estimation method for extent variable block |
| CN102647594A (en) * | 2012-04-18 | 2012-08-22 | 北京大学 | Integer pixel precision motion estimation method and system for same |
Non-Patent Citations (2)
| Title |
|---|
| CHING-YEH CHEN 等: "Analysis and Architecture Design of Variable Block-Size Motion Estimation for H.264/AVC", 《 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS》 * |
| NAM-KHANH DANG 等: "An Efficient Hardware Architecture for Inter-Prediction in H.264/AVC Encoders", 《17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107169968A (en) * | 2017-03-23 | 2017-09-15 | 天津理工大学 | A kind of image block and processing method based on raster scanning principle |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105430413B (en) | 2018-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9202290B2 (en) | Apparatus and method for encoding/decoding images for intra-prediction | |
| KR101795332B1 (en) | Image decoding apparatus, image encoding apparatus, image decoding method, image encoding method, and recording medium for recording data structure of encoded data | |
| CN102131091B (en) | Methods for decoder-side motion vector derivation | |
| CN101500161B (en) | Inter-frame prediction method and apparatus based on adaptive block transformation | |
| CN102970543A (en) | Methods for decoder-side motion vector derivation | |
| BR112013016961A2 (en) | image encoding and decoding devices, image encoding and decoding methods and image prediction device | |
| KR102138368B1 (en) | Method and apparatus for hierarchical motion estimation based on adaptive sampling | |
| CN103051892B (en) | Embedded loop filter method and embedded loop filter | |
| CN104125466A (en) | GPU (Graphics Processing Unit)-based HEVC (High Efficiency Video Coding) parallel decoding method | |
| CN111541896B (en) | VVC-based intra-frame prediction mode optimization method and system | |
| CN107360433B (en) | Inter-frame prediction coding method and device | |
| US20160050431A1 (en) | Method and system for organizing pixel information in memory | |
| CN105306957A (en) | Adaptive loop filtering method and device | |
| JPWO2014049981A1 (en) | Moving picture encoding apparatus, moving picture decoding apparatus, moving picture encoding method, and moving picture decoding method | |
| US10979712B2 (en) | Block-based video decoding method using pre-scan and apparatus thereof | |
| CN105430413A (en) | Four-block hardware scanning method applicable for integer motion estimation in HEVC (High Efficiency Video Coding) standard | |
| CN105376586A (en) | Three-level flow line hardware architecture suitable for integer motion estimation in HEVC standard | |
| KR20090041944A (en) | Method and apparatus for motion estimation using mode information of neighbor blocks | |
| CN104602026B (en) | A kind of reconstruction loop structure being multiplexed entirely encoder under HEVC standard | |
| CN109168000B (en) | HEVC intra-frame prediction rapid algorithm based on RC prediction | |
| CN114390289A (en) | Reference pixel candidate list construction method, device, equipment and storage medium | |
| CN104363455A (en) | Hardware on-chip storage method applicable to infra-frame prediction reference pixels in HEVC (high efficiency video coding) standard | |
| KR20160106348A (en) | Video Coding Method and Apparatus thereof | |
| JPWO2014049982A1 (en) | Moving picture encoding apparatus, moving picture decoding apparatus, moving picture encoding method, and moving picture decoding method | |
| Segall et al. | Parallel intra prediction for video coding |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |