CN105428474A - Simple manufacturing method of high-efficient light emitting diode chip - Google Patents
Simple manufacturing method of high-efficient light emitting diode chip Download PDFInfo
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- CN105428474A CN105428474A CN201510916691.4A CN201510916691A CN105428474A CN 105428474 A CN105428474 A CN 105428474A CN 201510916691 A CN201510916691 A CN 201510916691A CN 105428474 A CN105428474 A CN 105428474A
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- 238000004519 manufacturing process Methods 0.000 title abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 238000000034 method Methods 0.000 claims abstract description 34
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 17
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 17
- 238000001704 evaporation Methods 0.000 claims abstract description 14
- 230000008020 evaporation Effects 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims abstract description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 4
- 239000010410 layer Substances 0.000 claims description 101
- 238000005530 etching Methods 0.000 claims description 18
- 238000001514 detection method Methods 0.000 claims description 9
- 239000012811 non-conductive material Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 6
- 230000001934 delay Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 239000000523 sample Substances 0.000 claims description 3
- 238000004020 luminiscence type Methods 0.000 abstract 3
- 238000010586 diagram Methods 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/14—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
- H01L33/145—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
The invention discloses a simple manufacturing method of a high-efficient light emitting diode chip. The method comprises the following steps that an epitaxial luminescence structure is formed on a substrate; a non-conducting material is evaporated on an ohmic contact layer so as to be taken as a current barrier layer; silicon dioxide is evaporated on an epitaxial luminescence structure surface and a side surface; all the photoresists on the surface are removed and evaporation is performed on the surface to form an ITO conducting layer; an etchant solution is used to remove the silicon dioxide on the epitaxial luminescence structure side surface and an N-type electrode manufacturing area; silicon nitride is evaporated on a chip surface, a side surface and an electrode isolation groove between an N-type electrode and an epitaxial layer to form a chip protection layer and an electrode isolation layer; a P-type electrode manufacturing area and the N-type electrode manufacturing area are defined on the chip surface; the photoresist is evaporated on and peeled off the P-type electrode manufacturing area and the N-type electrode manufacturing area; the chip is splintered and is separated into independent chip grains. By using method in the invention, a chip manufacturing technology is effectively simplified; chip process time is shortened; chip manufacturing cost is reduced and chip quality is increased.
Description
Technical field
The present invention relates to the technical field of light-emitting diode, a kind of simple making method of efficient LED chip is provided especially.
Background technology
Light-emitting diode has the little and high reliability of low-power consumption, size, and comparatively fast developed as main light source, the field that utilizes of light-emitting diode is expanded rapidly in recent years.Along with LED industry competition is more and more fierce, improves the brightness of light-emitting diode and reduce costs and become its important directions.
In order to make brightness and the better reliability of chip; chip fabrication technique traditional at present: be included in below P-type electrode and make current barrier layer (CurrentBlockingLayer); evaporation N, P electrode, and make chip protection layer (PV).But adopt traditional manufacture method usually to need to carry out five step photoetching, cause chip technology flow time longer, chip cost raises and fraction defective increases.
Summary of the invention
The present invention, for solving the problem, provides a kind of simple making method of efficient LED chip.
To achieve these goals, the technical solution used in the present invention is:
A simple making method for efficient LED chip, comprises the following steps:
S01: provide a substrate, forms extension ray structure over the substrate;
S02: evaporation non-conducting material serves as current barrier layer on ohmic contact layer;
S03: go out N-type electrode at current barrier layer surface definition and make region and Cutting Road; Adopt ICP to etch N-type electrode and make region and Cutting Road, the degree of depth mixes part to the height of N-type conductive layer;
S04: steam coating silicon dioxide delays photo structure surface and side outside; Then make region in P-type electrode and define current barrier layer area; Adopt ICP to etch away the current barrier layer in non-P-type electrode making region, expose ohmic contact layer;
S05: remove surperficial all photoresists, forms ITO conductive layer at surperficial evaporation;
S06: adopt etchant solution to remove the silicon dioxide in extension ray structure side and N-type electrode making region, equally also remove the ITO conductive layer on this region silicon dioxide, the N-type conduction floor height exposing N-type electrode making region mixes part;
S07: at chip surface, side and the electrode isolation groove evaporation silicon nitride between N-type electrode and epitaxial loayer, forms chip protection layer and electrode isolation layers;
S08: define P-type electrode at chip surface and make region and N-type electrode making region; Adopt ICP etching to remove N-type electrode to make region and P-type electrode and make chip protection layer on region, make the N-type conduction floor height that the current barrier layer in region, ITO conductive layer and N-type electrode make region mix part until expose P-type electrode;
S09: make evaporation on region and N-type electrode making region and stripping photoresist in P-type electrode respectively, form P-type electrode and N-type electrode;
S10: carry out sliver to chip, is separated into independently core grain, and final formation has the light-emitting diode of specular removal.
Preferably, in described step S01, described extension ray structure comprises resilient coating, involuntary doped layer, N-type conductive layer, active layer, electronic barrier layer, P-type conduction layer and ohmic contact layer.
Preferably, in described step S02, described current barrier layer is that non-conductive material is made.
Preferably, in described step S02, described non-conductive material comprises SiN, Ti
2o
3and Al
2o
3.
Preferably, in described step S04, described employing ICP etches away in the current barrier layer in non-P-type electrode region, the ICP etching machines that it adopts has epitaxial loayer element detection function, after having removed the current barrier layer on top layer, by the epitaxial loayer element under probe current barrier layer, if detect epitaxial loayer element and the concentration of epitaxial loayer element reaches the corresponding order of magnitude, then stop etching at once.
Preferably, in described step S04, described epitaxial loayer element is Ga element.
Preferably; in described step S08; N-type electrode making region is removed in described employing ICP etching and P-type electrode makes in the chip protection layer on region; the ICP etching machines that it adopts has epitaxial loayer element detection function; after having removed the chip protection layer on top layer; by the epitaxial loayer element under detection chip protective layer, if detect epitaxial loayer element and the concentration of epitaxial loayer element reaches the corresponding order of magnitude, then stop etching at once.
Preferably, in described step S08, described epitaxial loayer element is Ga element.
Preferably, in described step S06, the etchant solution of described employing is only for removing the silicon dioxide in extension ray structure side and N-type electrode making region and the ITO conductive layer on this region silicon dioxide.
The present invention, by the OVERALL OPTIMIZA-TION DESIGN FOR to chip fabrication technique flow process, only need adopt three step photoetching just can realize producing the efficient LED chip including current barrier layer, chip protection layer, N, P electrode.The chip structure that the technological process of contrast traditional die needs employing five step photoetching process to realize, manufacture method of the present invention can realize facilitating chip technological process effectively, and shortens the chip manufacturing time and reduce chip manufacturing cost, promotes the quality of chip.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms a part of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is step S01 schematic diagram of the present invention;
Fig. 2 is step S02 schematic diagram of the present invention;
Fig. 3 is step S03 schematic diagram of the present invention;
Fig. 4 is step S04 schematic diagram of the present invention;
Fig. 5 is step S05 schematic diagram of the present invention;
Fig. 6 is step S06 schematic diagram of the present invention;
Fig. 7 is step S07 schematic diagram of the present invention;
Fig. 8 is step S08 schematic diagram of the present invention;
Fig. 9 is step S09 schematic diagram of the present invention.
Embodiment
In order to make technical problem to be solved by this invention, technical scheme and beneficial effect clearly, understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figures 1 to 9, the invention provides a kind of simple making method of efficient LED chip, comprise the following steps:
S01: provide a substrate, forms extension ray structure over the substrate;
S02: evaporation non-conducting material serves as current barrier layer on ohmic contact layer;
S03: the mask, the photoetching process that adopt standard, goes out N-type electrode at current barrier layer surface definition and makes region and Cutting Road; Adopt ICP to etch N-type electrode and make region and Cutting Road, the degree of depth mixes part to the height of N-type conductive layer (GaN);
S04: steam coating silicon dioxide delays photo structure surface and side outside; Then adopt the mask of standard, photoetching process, make region in P-type electrode and define current barrier layer area; Adopt ICP to etch away the current barrier layer in non-P-type electrode making region, expose ohmic contact layer (P type contact layer);
S05: remove surperficial all photoresists, delays photo structure surface evaporation outside and forms ITO conductive layer;
S06: adopt etchant solution to remove the silicon dioxide in extension ray structure side and N-type electrode making region, equally also remove the ITO conductive layer on this region silicon dioxide, N-type conductive layer (GaN) height exposing N-type electrode making region mixes part;
S07: at chip surface, side and the electrode isolation groove evaporation silicon nitride between N-type electrode and epitaxial loayer, forms chip protection layer and electrode isolation layers;
S08: the mask, the photoetching process that adopt standard, defines P-type electrode at chip surface and makes region and N-type electrode making region; Adopt ICP etching to remove N-type electrode to make region and P-type electrode and make chip protection layer on region, make N-type conductive layer (GaN) height that the current barrier layer in region, ITO conductive layer and N-type electrode make region mix part until expose P-type electrode;
S09: make evaporation on region and N-type electrode making region and stripping photoresist in P-type electrode, form P-type electrode and N-type electrode;
S10: carry out sliver to chip, is separated into independently core grain, and final formation has the light-emitting diode of specular removal.
In described step S01, described extension ray structure comprises resilient coating, involuntary doped layer, N-type conductive layer, active layer, electronic barrier layer, P-type conduction layer and ohmic contact layer (P type contact layer).
In described step S02, described current barrier layer is that non-conductive material is made, and non-conductive material preferably includes SiN, Ti
2o
3and Al
2o
3deng, adopt non-conductive material to deaden the sense of current of P electrode, effectively improve current expansion effect.
In described step S04, described employing ICP etches away in the current barrier layer in non-P-type electrode region, the ICP etching machines that it adopts has epitaxial loayer element detection function, after having removed the current barrier layer on top layer, by the epitaxial loayer element under probe current barrier layer, the molar concentration as detected Ga element reaches 1E10
4mol/m
3, then stop etching at once, avoid the ohmic contact layer of epi-layer surface also to get rid of.
Similarly; in described step S08; N-type electrode making region is removed in described employing ICP etching and P-type electrode makes in the chip protection layer on region; the ICP etching machines that it adopts has epitaxial loayer element detection function; after having removed the chip protection layer on top layer; by the epitaxial loayer element under detection chip protective layer, the molar concentration as detected Ga element reaches 1E10
4mol/m
3, then stop etching at once.
In described step S06, the etchant solution of described employing, can not to current barrier layer constituent material SiN, Ti only for removing the silicon dioxide in extension ray structure side and N-type electrode making region and the ITO conductive layer on this region silicon dioxide
2o
3, Al
2o
3play corrosiveness, to avoid removing current barrier layer, cause chip structure change and reduce current expansion effect.
The present invention, by the OVERALL OPTIMIZA-TION DESIGN FOR to chip fabrication technique flow process, only need adopt three step photoetching just can realize producing the efficient LED chip including current barrier layer, chip protection layer, N, P electrode.The chip structure that the technological process of contrast traditional die needs employing five step photoetching process to realize, manufacture method of the present invention can realize facilitating chip technological process effectively, and shortens the chip manufacturing time and reduce chip manufacturing cost, promotes the quality of chip.
Above-mentioned explanation illustrate and describes the preferred embodiments of the present invention, as previously mentioned, be to be understood that the present invention is not limited to the form disclosed by this paper, should not regard the eliminating to other embodiments as, and can be used for other combinations various, amendment and environment, and can in invention contemplated scope described herein, changed by the technology of above-mentioned instruction or association area or knowledge.And the change that those skilled in the art carry out and change do not depart from the spirit and scope of the present invention, then all should in the protection range of claims of the present invention.
Claims (9)
1. a simple making method for efficient LED chip, is characterized in that; Comprise the following steps:
S01: provide a substrate, forms extension ray structure over the substrate;
S02: evaporation non-conducting material serves as current barrier layer on ohmic contact layer;
S03: go out N-type electrode at current barrier layer surface definition and make region and Cutting Road; Adopt ICP to etch N-type electrode and make region and Cutting Road, the degree of depth mixes part to the height of N-type conductive layer;
S04: steam coating silicon dioxide delays photo structure surface and side outside; Then make region in P-type electrode and define current barrier layer area; Adopt ICP to etch away the current barrier layer in non-P-type electrode making region, expose ohmic contact layer;
S05: remove surperficial all photoresists, forms ITO conductive layer at surperficial evaporation;
S06: adopt etchant solution to remove the silicon dioxide in extension ray structure side and N-type electrode making region, equally also remove the ITO conductive layer on this region silicon dioxide, the N-type conduction floor height exposing N-type electrode making region mixes part;
S07: at chip surface, side and the electrode isolation groove evaporation silicon nitride between N-type electrode and epitaxial loayer, forms chip protection layer and electrode isolation layers;
S08: define P-type electrode at chip surface and make region and N-type electrode making region; Adopt ICP etching to remove N-type electrode to make region and P-type electrode and make chip protection layer on region, make the N-type conduction floor height that the current barrier layer in region, ITO conductive layer and N-type electrode make region mix part until expose P-type electrode;
S09: make evaporation on region and N-type electrode making region and stripping photoresist in P-type electrode respectively, form P-type electrode and N-type electrode;
S10: carry out sliver to chip, is separated into independently core grain, and final formation has the light-emitting diode of specular removal.
2. the simple making method of a kind of efficient LED chip according to claim 1, it is characterized in that: in described step S01, described extension ray structure comprises resilient coating, involuntary doped layer, N-type conductive layer, active layer, electronic barrier layer, P-type conduction layer and ohmic contact layer.
3. the simple making method of a kind of efficient LED chip according to claim 1, is characterized in that: in described step S02, and described current barrier layer is that non-conductive material is made.
4. the simple making method of a kind of efficient LED chip according to claim 3, it is characterized in that: in described step S02, described non-conductive material comprises SiN, Ti
2o
3and Al
2o
3.
5. the simple making method of a kind of efficient LED chip according to claim 1, it is characterized in that: in described step S04, described employing ICP etches away in the current barrier layer in non-P-type electrode region, the ICP etching machines that it adopts has epitaxial loayer element detection function, after having removed the current barrier layer on top layer, by the epitaxial loayer element under probe current barrier layer, if detect epitaxial loayer element and the concentration of epitaxial loayer element reaches the corresponding order of magnitude, then stop etching at once.
6. the simple making method of a kind of efficient LED chip according to claim 5, is characterized in that: in described step S04, and described epitaxial loayer element is Ga element.
7. the simple making method of a kind of efficient LED chip according to claim 1; it is characterized in that: in described step S08; N-type electrode making region is removed in described employing ICP etching and P-type electrode makes in the chip protection layer on region; the ICP etching machines that it adopts has epitaxial loayer element detection function; after having removed the chip protection layer on top layer; by the epitaxial loayer element under detection chip protective layer; if detect epitaxial loayer element and the concentration of epitaxial loayer element reaches the corresponding order of magnitude, then stop etching at once.
8. the simple making method of a kind of efficient LED chip according to claim 7, is characterized in that: in described step S08, and described epitaxial loayer element is Ga element.
9. the simple making method of a kind of efficient LED chip according to claim 1, it is characterized in that: in described step S06, the etchant solution of described employing is only for removing the silicon dioxide in extension ray structure side and N-type electrode making region and the ITO conductive layer on this region silicon dioxide.
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| CN107658372A (en) * | 2017-09-21 | 2018-02-02 | 山西飞虹微纳米光电科技有限公司 | Deep etching Cutting Road flip LED chips and preparation method, LED display |
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| CN108183153A (en) * | 2017-12-28 | 2018-06-19 | 聚灿光电科技股份有限公司 | The preparation method of LED chip |
| CN109524521A (en) * | 2018-09-27 | 2019-03-26 | 华灿光电（浙江）有限公司 | A kind of LED epitaxial slice and its manufacturing method |
| JP2022070407A (en) * | 2020-10-27 | 2022-05-13 | 日機装株式会社 | Nitride semiconductor light-emitting element and method of manufacturing the same |
| CN116169215A (en) * | 2023-04-24 | 2023-05-26 | 江西兆驰半导体有限公司 | Current blocking layer, preparation method thereof and LED chip |
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| CN116169215A (en) * | 2023-04-24 | 2023-05-26 | 江西兆驰半导体有限公司 | Current blocking layer, preparation method thereof and LED chip |
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| CN105428474B (en) | 2017-12-08 |
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