CN105391497A - 433M digital frequency modulation receiver - Google Patents

Abstract

The invention relates to the field of digital frequency modulation receivers, and particularly relates to a 433M digital frequency modulation receiver, which comprises a low-noise amplifier and a 433M filter part at the input end, a 392.3M local oscillator source signal circuit part, a frequency mixer and an intermediate frequency filter part, a demodulation secondary frequency reduction circuit part, a single chip micro processing part, and a power control and ground part for the entire circuit diagram. The 433M digital frequency modulation receiver provided by the invention has the advantages that the design is clever; the layout is reasonable; the power consumption is low; the sensitivity is high; the dynamic range is large; and by adopting a 2FSK modulation and demodulation mode, real-time communication with a 433M digital frequency modulation transmitter can be well carried out. The 433M digital frequency modulation receiver has a high scientific research value in the ultra-short wave communication field and has a certain project application value.

Description

A kind of 433M digital FM receiver

Technical field

Patent of the present invention relates to digital FM receiver field, is specifically related to a kind of 433M digital FM receiver.

Background technology

Existing receiver type mainly contains phase modulation, FM receiver and AM receiver, and FM receiver is the most conventional.Wherein FM receiver kind has following several, has superhet frequency conversion receiver, image frequency suppression receiver, zero intermediate frequency reciver and digital radio frequency receiver etc.The function of coursing digital radio frequency receiver is best.

For superhet frequency conversion receiver, its main advantage is, structure is simple, be easy to realize, although its structure is simple, up to the present, superhet frequency conversion receiver remains the most frequently used version of engineers.The shortcoming of superhet frequency conversion receiver is that superhet frequency conversion receiver needs more high performance filter and frequency mixer to complete whole receiving system, this receiver volume just causing volume other kind relative of superhet frequency conversion receiver is comparatively large, and this manufacturing cost also just thereupon causing it is higher than the receiver of other kind certainly.Superhet frequency conversion receiver can by the technical indicator such as good frequency selectivity and receiver sensitivity selecting suitable IF-FRE value and intermediate-frequency filter to obtain, so superhet double conversion receiving system is considered to the most reliable receiver structure, certain utilization is also the most widely.Patent 433M digital FM receiver of the present invention also has double conversion.

For zero intermediate frequency reciver, its main advantage is, volume is little, cost is low, be easy to single-chip integration etc.The good Image interference rejection ability of zero intermediate frequency reciver structural requirement, because the power level of its image disturbing signal necessarily requires the power level being less than or equal to required restituted signal.Because zero intermediate frequency reciver directly acts on down-conversion signal by a local oscillation signal, relative to superheterodyne receiver, zero intermediate frequency reciver decreases optical mixing process.Generally speaking, zero intermediate frequency reciver structure is do well in reduction design cost, minimizing chip area and reduction power consumption.Zero intermediate frequency reciver application in the field of wireless communication more comes also extensive.

China's software radio technilogy fast development in recent years, digital radio frequency receiver technology is also arisen at the historic moment thereupon.Digital radio frequency receiver be a kind of by analog-digital converter, digitlization is carried out to modulation signal after use Digital Signal Processing to the real radio-frequency transmitter carrying out the digital signal processings such as digital frequency conversion, digital filtering, digital demodulation of modulation signal.The various technical indicators of digital receiver can realize relatively digitized expression, digital receiver has a lot of advantage compared to analog receiver, such as his sensitivity accuracy is high, good stability, flexible design and it can realize the irrealizable sophisticated functions of a lot of analog receiver, generally speaking digital receiver it become a kind of version having development potentiality in the various system of receiver most.And patent 433M digital FM receiver of the present invention is exactly the one belonging to digital radio frequency receiver.

Summary of the invention

The object of the present invention is to provide that a kind of sensitivity accuracy is high, the 433M digital FM receiver of good stability.

The object of the present invention is achieved like this:

The present invention includes: input low noise amplifier and 433M filter segment; 392.3M local vibration source signal circuit section; Frequency mixer and intermediate-frequency filter part; Demodulation secondary frequency down circuit part; The micro-processing section of single-chip microcomputer; The Energy control of whole circuit diagram and ground part, is characterized in that: signal is entered by input low noise amplifier and 433M filter segment; 392.3M local vibration source signal circuit section provides local oscillation signal, 392.3MHz to frequency mixer and intermediate-frequency filter part; Signal completes first time frequency reducing after input low noise amplifier and 433M filter section branch away in frequency mixer and intermediate-frequency filter part, reduces to 40.7M by 433M; Enter demodulation secondary frequency down circuit part again to carry out second time frequency reducing and become 10.7M from 40.7M, carry out demodulation subsequently; Single-chip microcomputer micro-processing section control 392.3M local vibration source signal circuit section and demodulation secondary frequency down circuit part; Energy control and the ground part of whole circuit diagram are module 392.3M local vibration source signal circuit section; ; Demodulation secondary frequency down circuit part; The micro-processing section of single-chip microcomputer provides Digital and analog power supply and earth signal;

Input low noise amplifier and 433M filter segment:

Use low noise amplifier MAX2650; Signal is entered by the tuner P1 of module 1, is gone out 1 pin of the RF2418DS chip entering module 3 by the port 5 of 433M SAW (Surface Acoustic Wave) filter chip U4; P1 is tuner, after tuner receives antenna, comprises the ripple of all frequency ranges of 433M carrier wave, enter chip U3 low noise amplifier MAX2650 by P1 and carry out power amplification, export next stage by port 3 after amplification, what port 4 connected is+5V power supply, port 2 ground connection; The supply power voltage of low noise amplifier MAX2650 is the electric capacity C10 of+5V, 0.1uf and has the electric capacity C11 of polarity 10uf and magnetic bead L4 to carry out filtering to power supply, and the blocking capacitance value at the input/output interface place of MAX2650 is:

$C_{BLOCK}=\frac{53000}{F}\left(pF\right)$

Wherein, the unit of frequency F is MHz, and the carrier frequency of receiver is the capacitance of 433MHz, MAX2650 input/output terminal is 122pF; Its two ends must add electric capacity C101 and the electric capacity C102 of 0.1uf, carry out filtering to direct current signal, and U4 is 433MHz SAW (Surface Acoustic Wave) filter, is entered by 2 pins, output to the pin one of the RF2418DS chip of module 3 from 5 pins;

392.3M local vibration source signal circuit section:

4,5 pins of ADF4360-8 chip are connected to 8 pins of the RF2418DS chip of frequency mixer and intermediate-frequency filter part; The minimum system that MSP430F149 singlechip chip is formed controls ADF4360-8 chip, produces the local frequency of 392.3M; Voltage controlled oscillator output frequency inside ADF4360-8 chip is:

f _VCO＝[(P×B)+A]×f _REFIN/R

Wherein f _vCOfor voltage controlled oscillator output frequency, P is pre-divide ratio, f _rEFINfor reference frequency;

F _cco＝B×Frefin/R

F _ccothe frequency that phase-locked loop exports, F _cco=392.3M, B are the binary registers of 13, and its span is 3 ~ 8191, Frefin is ADF4360-8 chip 16 pin REF _inthe frequency of the active crystal oscillator of input, R is the binary register of 14, and Frefin selects 50M, R=500, B=3923; ADF4360-8 chip 16 pin REF _inthat connect is the active crystal oscillator U12 of 50M; The AGND of the CPGND of 1 pin, the AGND of 3 pins, 8 pins, the AGND of 11 pins, 12 pin C _c, the DGND of 15 pins, the AGND of 22 pins meet in analog i.e. GND; Get the supply power voltage of+3.3V as phase-locked loop ADF4360-8 chip, the CE of the Vvco of 2 pin Avdd, 6 pins, the Dvdd of 21 pins, 23 pins connects the power supply of+3.3V, and each power supply needs to connect the filter circuit the same with in module 1; Chip U13 is the voltage stabilizing sheet AMS1117-3.3 of+3.3V, U13 for phase-locked loop ADF4360-8 chip provides the voltage of+3.3.V, 3 pins inputs, and 2 pins export, and input is+5V power supply, and exporting is exactly+3.3V; 9 pin L ₁, 10 pin L ₂meet resistance R32, a R33 and inductance L 29, a L30 all respectively, wherein resistance R32, R33 is 470 Ω; Inductance value:

$F_o=\frac{1}{2\mathrm{\π}\sqrt{9.3pF(0.9nH+Lext)}}$

In formula, F _othat 392.3M, Lext are required inductance value, Lext=16.8nH; 17 pin CLK, 18 pin DATA, 19 pin LE are connected on MSP430F149 singlechip chip, be connected to I/O port 5.3,5.1,5.4, resistance R22, R24, R2 are 0 Ω, and 20 pin MUXOUT are connected with LED D3,24 pin CP connect a low pass filter, 16 pin REF _inconnect the active crystal oscillator of 50M, the power supply connecting active crystal oscillator need connect filter circuit, and the 50 Ω resistors match circuit that active crystal oscillator pin 3 and phase-locked loop ADF4360-8 chip pin 16 extract directly are connected and are made up of electric capacity C73, C75 of 1nF and the resistance R26 of 51 Ω; Resistance R27, R28, the tuner P12 of 0 Ω are external to frequency spectrograph, whether the frequency produced for phase locked loop ADF4360-8 chip is 392.3MHz, the local frequency that phase-locked loop ADF4360-8 chip produces outputs to frequency mixer 8 pin LOIN from 4 pin RfoutA, and the inductance L 18 of electric capacity C44 and 10nH of the 4pF that RF2418DS chip 8 pin in module 3 connects completes the resistors match of 50 Ω between phase-locked loop ADF4360-8 chip and mixing chip RF2418DS;

Frequency mixer and intermediate-frequency filter part:

U5 chip is RF2418 mixer chip, the pin one of RF2418DS chip connects the port 5 of the U4 chip of input low noise amplifier and 433M filter segment, the pin 8 of RF2418DS chip meets the RfoutA of 4,5 pins connections of the ADF4360-8 chip of 392.3M local vibration source signal circuit section, and the RFIn pin of U2 chip MAX2650 connects 1 pin of the U1 chip of demodulation secondary frequency down circuit part, the inductance L 12 of resistance R8 and 10nH of the 5.11K of the pin one connection of RF2418 chip, 3 pin VDD1 connect+5V DC power supply, and 4 pin VDD2 need not connect, and magnetic bead L13,10uF electric capacity C34,47pF electric capacity C32,0.1uF electric capacity C35 forms filter circuit, and right+5V DC power supply carries out filtering, signal after input low noise amplifier and 433M filter section branch away, frequency mixer RF2418 chip is entered by pin one LNAIN, 11 pin RFIN are entered by 14 pin LNAOUT, signal after mixing is input to the intermediate-frequency filter circuit part IN of this module by 6 pin IF2OUT, the local oscillation signal of the 392.3MHz that 392.3M local vibration source signal circuit section phase-locked loop produces is input to U5 frequency mixer RF2418DS chip by 8 pins, the electric capacity C44 of 4pF and 10nH inductance L 18 complete the resistors match of 50 Ω between ADF4360-8 chip and RF2418DS chip, 7 pin place circuit defaults connect, the 0.1uF electric capacity C40 of 6 pins and 1.5K resistance R13 completes the resistors match of 50 Ω between RF2418DS chip and the intermediate-frequency filter of this module, intermediate-frequency filter part is made up of the inductance L 6 of electric capacity C18,220nH of 33pF, the inductance L 7 of electric capacity C19,220nH of 110pF, the electric capacity C20 of 33pF, signal enters from IN mouth, go out from INI mouth, the pin 6IF2OUT of what IN mouth connect is mixing chip RF2418DS, from the IN of 6 pins out, have two paths of signals, a frequency is 40.7M, another is 825.3M, and low pass filter filtering 825.3M signal retains the signal of 40.7M, signal out enters next low noise amplifier U2 afterwards from INI mouth, the pin 3 of U2 connects the pin one of the SA639 chip of demodulation secondary frequency down circuit part, the pin 4 of U2 connects+5V power supply, power supply connects filter circuit, input pin 1 and the output pin 3 of MAX2650 be all connected 0.1uf every straight filter capacitor C103 and C104,

Demodulation secondary frequency down circuit part:

Select U1 chip SA639 to complete secondary frequency reducing, become 10.7M and demodulation from 40.7M; The intermediate-freuqncy signal of 40.7M is entered into 1 pin of the U1 chip of demodulation secondary frequency down circuit part by the RFIn pin of the U2 chip of module 3; The electric capacity C9 of the inductance L 3 of 760nH, electric capacity C6 and 16pF of 3pF completes the resistors match between the MAX2650 low noise amplifier 50 Ω output resistance of frequency mixer and intermediate-frequency filter part and SA639 demodulation chip 800 Ω input resistance; The C1 of C8 and 1nF of 0.1 μ f carries out every straight filtering to 40.7M signal; SA639 demodulation chip 1,4,24 pins form be a frequency mixer, 2 pin ground connection, 3 pins do not connect, and 4 pins meet the active crystal oscillator U6 of 30M, with 1 pin input 40.7M signal together with complete mixing; 10.7M signal after the inner filtering of SA639 demodulation chip is exported by 24 pin MIXEROUT, filtering is carried out through the ceramic filter PLT1 of first 10.7M, 22 pin IFAMPIN are received after first time filtering, signal comes again 20 pin IFAMPOUT through SA639 demodulation chip inside, and then carry out filtering through the ceramic filter PLT2 of a 10.7M, this time receive 18 pin LIMITER after filtering; 23,21,16,17,19 pin ground connection GND; 5 pin VCC connect+5V power supply; 6,7,8 pin acquiescences connect; The signal of the 10.7M after twice filtering by 15 pins out, connect a phase shift 90 degree of networks, 10.7M signal phase shift before making to enter 90 degree, this phase shift 90 degree of networks are made up of the C27 of C28,11pF of R7,15pF of L11,1.3K of 4.7uH, and the 10.7M signal through phase shift 90 degree enters SA639 demodulation chip by 14 pins; The 10.7M signal without phase shift 90 degree entered by 18 pins is multiplied with the multiplier that the 10.7M signal through phase shift 90 degree entered by 14 pins enters SA639 inside, by generation two components after multiplier, low frequency component high fdrequency component, low frequency component is exactly symbol signal; The connection of chip internal 9 pin one 0 pin be all an operational amplifier, the operational amplifier of 9 pins completes to be penetrated with function, the operational amplifier of 10 pins just in time connects and composes the active low pass filter in two rank with 5.6K resistance R4,5.6K resistance R5,22pF electric capacity C24,33pF electric capacity C26 of outside, only retains the low frequency component of chip rate; 12 pins of SA639 demodulation chip connect+2.5V power supply, obtained by the average dividing potential drop of resistance R9, R10 right+5V power supply both for 22K, 510 Ω resistance R6,10nF electric capacity C25 that 13 pins connect also form low pass filter, again carry out filtering to the low frequency component of chip rate; By 13 pins out be positive low frequency component, and by 11 pins out be negative low frequency component, two paths of differential signals is input to LM311 comparator chip U7 together, from LM311 comparator chip 7 pin export is exactly code element square wave information; 7 pins of LM311 comparator chip are connected on the I/O port P5.5 of MSP430f149 chip U11, carry out detection of preamble, frame extracts and oscilloscope display code element square wave information waveform to information; 1, the 4 pin ground connection of comparator chip U7,5,6 pins do not connect, and 7,8 pins connect+5V power supply, and+5V power supply connects filter circuit;

The micro-processing section of single-chip microcomputer:

17 pin CLK of ADF4360-8 chip, 18 pin DATA, 19 pin LE are connected to the I/O port 5.3,5.1,5.4 of single-chip microcomputer micro-processing section MSP430F149 singlechip chip, and 7 pins of the LM311 comparator chip of module 4 are connected to the I/O port P5.5 of MSP430f149 chip U11; P8 is emulator chip, the minimum system of MSP430F149 singlechip chip selects outside 8M crystal oscillator XTCLK3, P5 is row's pin for subsequent use, P10 connects row's pin of 12864 liquid crystal, U10 and J2 forms serial communication system, U11 is MSP430F149 singlechip chip, and LED liquid crystal D4 connects P1.0 pin, interrupts chip REST1 and forms external interrupt circuit; The voltage stabilizing sheet chip of the supply power voltage of MSP430F149 singlechip chip to be+3.3V, U8 be+3.3V, LED liquid crystal D2 connects+3.3V power supply; + 3.3V voltage stabilizing sheet chip the U13 of phase-locked loop ADF4360-8 chip analogue type, + 3.3V voltage stabilizing sheet chip the U8 of MSP430F149 singlechip chip numeric type, voltage stabilizing sheet U8 has three pins, pin one ground connection, pin 3 be enter termination+5V power supply, pin two is output, exports+3.3V power supply;

The Energy control of whole circuit diagram and ground part:

The all digitally DGND connected by MSP430F149 singlechip chip minimum system and remaining all GND in analog of whole circuit link together; For+5V the power circuit of whole circuit supply ,+5V the power supply of electric capacity C38 to whole circuit of electric capacity C36,0.1uF of 10uF carries out every straight filtering, and LED liquid crystal D1 connects outside+5V power supply, J1 and DC-IN-2 is whole circuit supply+5V electric outlet structure.

Beneficial effect of the present invention is:

The 433M digital FM receiver apparatus design that patent of the present invention provides is ingenious, rationally distributed, low in energy consumption, highly sensitive, dynamic range large, adopts the modulation /demodulation pattern of 2FSK, can carry out real time communication well with 433M Digital Frequency Modulation Transmitter.Patent of the present invention all has very high scientific research and is worth in 433M digital FM receiver field and ultra short wave communication field, also have certain engineer applied simultaneously and be worth.

Accompanying drawing explanation

Fig. 1: the complete machine schematic diagram of patent 433M digital FM receiver device of the present invention, clearly can find out the modules of schematic diagram from schematic diagram.

Fig. 2: input low noise amplifier and 433M filter segment circuit diagram, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 3: 392.3M local vibration source signal circuit section, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 4 .1: the circuit of mixing unit, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 4 .2: intermediate-frequency filter partial circuit, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 4 .3: low noise amplifier partial circuit, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 5 .1: demodulator circuit part, from then on can be very clear in figure find out the concrete connection of this partial circuit.

The cut-away view of Fig. 5 .2:SA639 demodulation chip, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 6: singlechip chip minimum system part, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 7: the Energy control of whole circuit diagram and ground circuit part, from then on can be very clear in figure find out the concrete connection of this partial circuit.

Fig. 8: the complete machine module map of patent 433M digital FM receiver device of the present invention, clearly can find out the connection of each module from module map.

Fig. 9: header structure figure, we can find out the formation of header.

Figure 10: the header oscillogram of oscilloscope display, we can see that the content of outgoing packet is exactly the ASCII character of A and B in fact.

Figure 11: the message oscillogram that oscilloscope detects, we may safely draw the conclusion, patent 433M receiver of the present invention, extracts, the waveform of A and B entrained by carrier wave and so-called symbol waveform are presented at exactly on oscilloscope through detection of preamble and frame.

Figure 12: the design 433M digital FM receiver complete machine pictorial diagram.

Figure 13 is the dividing potential drop transmission phase-shift network using electric capacity and single-tunded circuit composition.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described further.

Patent of the present invention provides a kind of 433M digital FM receiver device.It is made up of 6 modules, is input low noise amplifier and 433M filter segment respectively, extracts 433M signal for amplifying; 392.3M local vibration source signal circuit section, for generation of the local oscillation signal of 392.3M; Frequency mixer and intermediate-frequency filter part, for mixing with extract down-conversion 40.7M signal; Demodulator circuit part, for demodulating the information entrained by carrier wave; The micro-processing section of single-chip microcomputer, for controlling phase-locked loop and demodulation circuit part; The Energy control of whole system and ground part, for whole apparatus system provides different VDD-to-VSSs.The 433M digital FM receiver apparatus design that patent of the present invention provides is ingenious, rationally distributed, low in energy consumption, highly sensitive, dynamic range large, adopts the modulation /demodulation pattern of 2FSK, can carry out real time communication well with 433M Digital Frequency Modulation Transmitter.Patent of the present invention all has very high scientific research and is worth in 433M digital FM receiver field and ultra short wave communication field, also have certain engineer applied simultaneously and be worth.

The patent 433M digital FM receiver of the present invention electric circuit diagram design both comprised on Theoretical Design is invented, software code writes debugging invention also has the material object of final molding to invent simultaneously.The 433M digital FM receiver apparatus design that patent of the present invention provides is ingenious, rationally distributed, reliability is high, low in energy consumption, highly sensitive, the error rate is low, dynamic range is large, integrated level is high, antijamming capability is strong.Be different from the receiver of other structures, this receiver complete machine scheme adopts twice unique frequency reducing pattern, mixing, demodulation better effects if, and Signal transmissions is more stable, and information distortion rate is little; Be different from the model configuration that other ultrashort wave frequency band receivers adopt, the information transmission of this receiver adopts the digital demodulation pattern of unique 2FSK Binary Frequency Shift Keying, Digital Transmission information, stable, accurately, anti-noise ability and antidamping ability better.Comprehensive these 2 innovations, phase continuity when making this receiver apparatus ensure that intersymbol frequency change in demodulating information, decrease the out-of-band radiation of radiofrequency signal, relativity of information is many, and transmission rate is fast.Patent of the present invention all has very high scientific research and is worth in 433M digital FM receiver field and ultra short wave communication field, also there is certain engineer applied be worth simultaneously, technical support well can be provided in television signal transmission, radar target acquisition, mobile service etc.

Just explain the summary of the invention of patent of the present invention and the summary of the invention of hardware circuit diagram in detail below.Patent 433M modulating mode of the present invention is that 2FSK receiver one is divided into 6 modules to form the circuitry figure of final 2FSK receiver, they respectively: the Energy control of (1) input low noise amplifier and 433M filter segment (2) 392.3M local vibration source signal circuit section (3) frequency mixer and intermediate-frequency filter part (4) demodulation (secondary frequency reducing) circuit part (5) single-chip microcomputer micro-processing section (6) whole circuit diagram and ground part.Signal is entered by module 1; Module 2 provides local oscillation signal to module 3: 392.3MHz; Signal from module 1 out after complete in module 3 first time frequency reducing, reduce to 40.7M by 433M; And then enter module 4 and carry out second time frequency reducing and become 10.7M from 40.7M, carry out demodulation subsequently; Module 5 control module 2 and module 4; Module 6 provides Digital and analog power supply and earth signal for module 2,4,5.Below just according to the direction that signal advances, point above-mentioned 6 modules ground explains design process and the summary of the invention of the circuitry of the design 433M receiver in detail.

(1) module 1: input low noise amplifier and 433M filter segment:

This module uses low noise amplifier MAX2650.Signal is entered by the tuner P1 of module 1, is gone out 1 pin of the RF2418DS chip entering module 3 by the port 5 of 433M SAW (Surface Acoustic Wave) filter chip U4.P1 is tuner, after tuner receives antenna, comprises the ripple of all frequency ranges of 433M carrier wave, enter chip U3 low noise amplifier MAX2650 by P1 and carry out power amplification, export next stage by port 3 after amplification, what port 4 connected is+5V power supply, port 2 ground connection.The supply power voltage of low noise amplifier MAX2650 is the electric capacity C10 of+5V, 0.1uf and has the electric capacity C11 of polarity 10uf and magnetic bead L4 to carry out filtering to power supply, and they form filter circuit, after can repeatedly use.The blocking capacitance value at the input/output interface place of MAX2650 is determined by following formula:

$C_{BLOCK}=\frac{53000}{F}\left(pF\right)---(4-1)$

Wherein, the unit of frequency F is MHz, and the carrier frequency of this receiver is 433MHz, and substitute into formula, the capacitance of MAX2650 input/output terminal is 122pF.Its two ends must add C101 and C102 of 0.1uf, carry out filtering to direct current signal, otherwise just can not occur waveform.U4 is 433MHz SAW (Surface Acoustic Wave) filter, is entered by 2 pins, outputs to the pin one of the RF2418DS chip of module 3 from 5 pins.Input low noise amplifier and this module of 433M filter segment are as shown in Figure 2.

(2) module 2:392.3M local vibration source signal circuit section:

This module uses ADF4360-8 chip U18.Module 2 provides the local oscillation signal source of 392.3M for module 3, and 4,5 pins of the ADF4360-8 chip of module 2 are connected to 8 pins of the RF2418DS chip of module 3.The minimum system that MSP430F149 singlechip chip is formed controls ADF4360-8 chip, makes it accurately produce the local frequency of 392.3M.Voltage controlled oscillator output frequency computing formula inside ADF4360-8 chip is:

f _VCO＝[(P×B)+A]×f _REFIN/R(4-2)

Wherein f _vCOfor voltage controlled oscillator output frequency, P is pre-divide ratio, f _rEFINfor reference frequency.

F _cco＝B×Frefin/R(4-3)

F _ccothe frequency that phase-locked loop exports, F in the design _cco=392.3M, B are the binary registers of 13, and its span is 3 ~ 8191, Frefin is ADF4360-8 chip 16 pin REF _inthe frequency of the active crystal oscillator of input, R is the binary register of 14, and the design Frefin selects 50M, and R=500, B=3923 be ADF4360-8 chip 16 pin REF therefore _inthat connect is the active crystal oscillator U12 of 50M.The AGND of the CPGND of 1 pin, the AGND of 3 pins, 8 pins, the AGND of 11 pins, 12 pin C _c, the DGND of 15 pins, the AGND of 22 pins meet in analog i.e. GND.Get the supply power voltage of+3.3V as phase-locked loop ADF4360-8 chip, the CE of the Vvco of 2 pin Avdd, 6 pins, the Dvdd of 21 pins, 23 pins connects the power supply of+3.3V, and each power supply needs to connect the filter circuit the same with in module 1.Chip U13 is the voltage stabilizing sheet AMS1117-3.3 of+3.3V, U13 for phase-locked loop ADF4360-8 chip provides the voltage of+3.3.V, and 3 pins inputs, 2 pins export, and input is+5V power supply, and exporting is exactly+3.3V.9 pin L ₁, 10 pin L ₂meet resistance R32, a R33 and inductance L 29, a L30 all respectively, wherein resistance R32, R33 is 470 Ω.Inductance value calculates according to formula below,

$F_o=\frac{1}{2\mathrm{\π}\sqrt{9.3pF(0.9nH+Lext)}}---(4-4)$

In formula, F _othat 392.3M, Lext are required inductance value, Lext=16.8nH.17 pin CLK, 18 pin DATA, 19 pin LE are connected on MSP430F149 singlechip chip, they are connected respectively to I/O port 5.3,5.1,5.4, and resistance R22, R24, R2 are 0 Ω, and 20 pin MUXOUT are connected with LED D3,24 pin CP connect a low pass filter, 16 pin REF _inconnect the active crystal oscillator of 50M, the power supply connecting active crystal oscillator need connect filter circuit, the 50 Ω resistors match circuit that active crystal oscillator pin 3 and phase-locked loop ADF4360-8 chip pin 16 extract directly are connected, and it is made up of electric capacity C73, C75 of 1nF and the resistance R26 of 51 Ω.Resistance R27, R28, the tuner P12 of 0 Ω can be external to frequency spectrograph, whether the frequency produced for phase locked loop ADF4360-8 chip is 392.3MHz, the local frequency that phase-locked loop ADF4360-8 chip produces outputs to frequency mixer 8 pin LOIN from 4 pin RfoutA, and the inductance L 18 of electric capacity C44 and 10nH of the 4pF that RF2418DS chip 8 pin in module 3 connects completes the resistors match of 50 Ω between phase-locked loop ADF4360-8 chip and mixing chip RF2418DS.This module of 392.3M local vibration source signal circuit section as shown in Figure 3.

(3) module 3: frequency mixer and intermediate-frequency filter part:

This module RF2418 completes first time frequency reducing as once descending frequency reducing chip, and reduce to 40.7M by 433M, U5 chip is exactly RF2418 mixer chip.The port 5 of the U4 chip of the pin one connection module 1 of RF2418DS chip, the RfoutA of 4,5 pins connections of the ADF4360-8 chip of pin 8 connection module 2 of RF2418DS chip, 1 pin of the U1 chip of the RFIn pin link block 4 of this module U2 chip MAX2650.The inductance L 12 of resistance R8 and 10nH of the 5.11K of the pin one connection of RF2418 chip.3 pin VDD1 connect+5V DC power supply, and 4 pin VDD2 need not connect, and magnetic bead L13,10uF electric capacity C34,47pF electric capacity C32,0.1uF electric capacity C35 forms filter circuit, and right+5V DC power supply carries out filtering.Signal after module 1 out, frequency mixer RF2418 chip is entered by pin one LNAIN, 11 pin RFIN are entered by 14 pin LNAOUT, signal after mixing is input to the intermediate-frequency filter circuit part IN of this module by 6 pin IF2OUT, the local oscillation signal of the 392.3MHz that module 2 phase-locked loop produces is input to U5 frequency mixer RF2418DS chip by 8 pins, the electric capacity C44 of 4pF and 10nH inductance L 18 complete the resistors match of 50 Ω between ADF4360-8 chip and RF2418DS chip, 7 pin place circuit defaults connect, the 0.1uF electric capacity C40 of 6 pins and 1.5K resistance R13 completes the resistors match of 50 Ω between RF2418DS chip and the intermediate-frequency filter of this module.The intermediate-frequency filter part of this module is made up of the inductance L 6 of electric capacity C18,220nH of 33pF, the inductance L 7 of electric capacity C19,220nH of 110pF, the electric capacity C20 of 33pF, signal enters from IN mouth, go out from INI mouth, the pin 6IF2OUT of what IN mouth connect is mixing chip RF2418DS, from the IN of 6 pins out, has two paths of signals, a frequency is 40.7M, another is 825.3M, and this low pass filter effect is, filtering 825.3M signal retains the signal of 40.7M.Signal out enters next low noise amplifier U2 afterwards from INI mouth, the pin one of the SA639 chip of pin 3 link block 4 of U2, the pin 4 of U2 connects+5V power supply, power supply connects filter circuit, input pin 1 and the output pin 3 of MAX2650 be all connected 0.1uf every straight filter capacitor C103 and C104.The circuit of mixing unit is as shown in accompanying drawing 4.1, and intermediate-frequency filter partial circuit is as shown in accompanying drawing 4.2, and amplifier circuit in low noise is as shown in accompanying drawing 4.3.

(4) module 4: demodulation (secondary frequency reducing) circuit part:

This module selects U1 chip SA639 to complete secondary frequency reducing, becomes 10.7M and demodulation from 40.7M.The intermediate-freuqncy signal of 40.7M is entered into 1 pin of the U1 chip of module 4 by the RFIn pin of the U2 chip of module 3.The electric capacity C9 of the inductance L 3 of 760nH, electric capacity C6 and 16pF of 3pF completes the resistors match between the MAX2650 low noise amplifier 50 Ω output resistance of module 3 and the SA639 demodulation chip 800 Ω input resistance of this module.The C1 of C8 and 1nF of 0.1 μ f carries out every straight filtering 40.7M signal.SA639 demodulation chip 1,4,24 pins form be a frequency mixer, 2 pin ground connection, 3 pins do not connect, and the active crystal oscillator that 4 pins meet 30M carrys out U6, with 1 pin input 40.7M signal together with complete mixing.10.7M signal after the inner filtering of SA639 demodulation chip is exported by 24 pin MIXEROUT, filtering is carried out through the ceramic filter PLT1 of first 10.7M, 22 pin IFAMPIN are received after first time filtering, signal comes again 20 pin IFAMPOUT through SA639 demodulation chip inside, and then carry out filtering through the ceramic filter PLT2 of a 10.7M, this time receive 18 pin LIMITER after filtering.23,21,16,17,19 pin ground connection GND.5 pin VCC connect+5V power supply.6,7,8 pin acquiescences connect.The signal of the 10.7M after twice filtering by 15 pins out, connect a phase shift 90 degree of networks, 10.7M signal phase shift before making to enter 90 degree, this phase shift 90 degree of networks are made up of the C27 of C28,11pF of R7,15pF of L11,1.3K of 4.7uH, and the 10.7M signal through phase shift 90 degree enters SA639 demodulation chip by 14 pins.The 10.7M signal without phase shift 90 degree entered by 18 pins is multiplied with the multiplier that the 10.7M signal through phase shift 90 degree entered by 14 pins enters SA639 inside, by generation two components after multiplier, low frequency component high fdrequency component, low frequency component is exactly symbol signal.The connection of chip internal 9 pin one 0 pin be all an operational amplifier, the operational amplifier of 9 pins completes to be penetrated with function, the operational amplifier of 10 pins just in time connects and composes the active low pass filter in two rank with 5.6K resistance R4,5.6K resistance R5,22pF electric capacity C24,33pF electric capacity C26 of outside, the function of this low pass filter is exactly that high fdrequency component filtering the generation of previous multiplications device, only remains the low frequency component of that chip rate.12 pins of SA639 demodulation chip connect+2.5V power supply, obtained by the average dividing potential drop of resistance R9, R10 right+5V power supply both for 22K, 510 Ω resistance R6,10nF electric capacity C25 that 13 pins connect also form low pass filter, again carry out filtering to the low frequency component of chip rate.By 13 pins out be positive low frequency component, and by 11 pins out be negative low frequency component, two paths of differential signals is input to LM311 comparator chip U7 together, from LM311 comparator chip 7 pin export is exactly code element square wave information.7 pins of LM311 comparator chip are connected on the I/O port P5.5 of MSP430f149 chip U11, carry out detection of preamble, frame extracts and oscilloscope display code element square wave information waveform to information.1, the 4 pin ground connection of comparator chip U7,5,6 pins do not connect, and 7,8 pins connect+5V power supply, and+5V power supply connects filter circuit.Accompanying drawing 5.1 utilizes SA639 demodulation chip to carry out the circuit diagram of demodulation to signal.Accompanying drawing 5.2 is internal structures of SA639 demodulation chip.

(5) module 5: the micro-processing section of single-chip microcomputer:

Module 5 as singlechip microprocessor, control module 2 and module 4.17 pin CLK of the ADF4360-8 chip of module 2,18 pin DATA, 19 pin LE are connected to the I/O port 5.3,5.1,5.4 of this module MSP430F149 singlechip chip, and 7 pins of the LM311 comparator chip of module 4 are connected to the I/O port P5.5 of this module MSP430f149 chip U11.In this module, P8 is emulator chip, the minimum system of this MSP430F149 singlechip chip need not inner crystal oscillator but select outside 8M crystal oscillator XTCLK3, P5 is row's pin for subsequent use, P10 connects row's pin of 12864 liquid crystal, U10 and J2 forms serial communication system, and U11 is MSP430F149 singlechip chip, LED liquid crystal D4 connects P1.0 pin, interrupts chip REST1 and forms external interrupt circuit.The voltage stabilizing sheet chip of the supply power voltage of MSP430F149 singlechip chip to be+3.3V, U8 be+3.3V, LED liquid crystal D2 connects+3.3V power supply.+ 3.3V voltage stabilizing sheet chip the U13 of phase-locked loop ADF4360-8 chip analogue type, + 3.3V voltage stabilizing sheet chip the U8 of MSP430F149 singlechip chip numeric type, voltage stabilizing sheet U8 has three pins, pin one ground connection, pin 3 be enter termination+5V power supply, pin two is output, exports+3.3V power supply.Accompanying drawing 6 is module 5 circuit diagrams.

(6) module 6: the Energy control of whole circuit diagram and ground part:

Module 6 provides numeral, analog power and earth signal for all active chips in module 2,4,5.Accompanying drawing 7 is Energy control and ground circuit part, i.e. module 6 circuit diagram of whole circuit diagram, and all digitally DGND that MSP430F149 singlechip chip minimum system connects by upper figure circuit and remaining all GND in analog of whole circuit link together; Figure below is whole circuit supply+5V power circuit, + 5V the power supply of electric capacity C38 to whole circuit of electric capacity C36,0.1uF of 10uF carries out every straight filtering, LED liquid crystal D1 connects outside+5V power supply, J1 and DC-IN-2 is whole circuit supply+5V electric outlet structure.

Above 6 modules are exactly the summary of the invention of patent of the present invention, have certainly also needed principle design and the experiment simulation of patent of the present invention before this, and this part can be talked about in embodiment again.Be exactly finally design patent 433M modulating mode of the present invention be the complete machine module map of 2FSK receiver as shown in Figure 8.

Comprise three parts, Part I has been the principle design of patent of the present invention, emulation experiment is connected with hardware circuit.Part II tests the sensitivity of patent 433M digital FM receiver of the present invention and whether dynamic range index meets the demands.If meet require that of two indices, proceed Part III.Part III is 2FSK transmitter in conjunction with 433M modulating mode, jointly completes one section of detection of preamble and frame extracts, and it is successful for demonstrating patent 433M digital FM receiver of the present invention.Part III not only plays the effect of checking in fact, can more say second be exactly patent 433M digital FM receiver of the present invention afterwards practical work time embodiment.Of course, Part III also must carry out under Part II meets the prerequisite of technical requirement, and both are inseparable.

First be Part I embodiment.

First be the principle design invention part of patent of the present invention.Comprise complete machine principle diagram design, utilize ADS radio frequency simulation software emulation complete machine conceptual scheme to obtain simulation result.Because patent of the present invention is exactly in fact obtain the FM receiver that a 433M modulating mode is 2FSK, then according to the several important index of FM receiver, defining patent 433M modulating mode of the present invention is the technical indicator that 2FSK receiver needs to reach: receiver frequency range: 433MHz ± 75KHz; Receiver sensitivity: lower than-55dBm; Dynamic range: be greater than 40dB.Because patent of the present invention demodulation mode used is 2FSK demodulation, then make use of respectively the theory of Binary Frequency Shift Keying 2FSK and phase shift, multiplication frequency discriminator, low pass filter method come together to form the theory of final demodulation 2FSK signal; Then be design the complete machine principle diagram design (as shown in Figure 1) that patent 433M modulating mode of the present invention is 2FSK receiver system.Contact between the modules just explaining the complete machine principle diagram design of Fig. 1 below in detail and formation.First illustratively this Receiver Design needs twice mixing, because a mixing effect is bad.First time mixing, frequency becomes 40.7M from 433M, and so primary local frequency is 392.3M.Second time mixing, frequency becomes 10.7M from 40.7M, and so local frequency is 30M.According to technical requirement and the 433M receiver principle of the design, have chosen following chip.First be that MAX2650 selected by low noise amplifier; 433M SAW (Surface Acoustic Wave) filter SAW selected by filter; RF2418DS selected by frequency mixer; Intermediate-frequency filter after mixing is self-designed low pass filter, uses RFSim99 filter-design software, why designs low pass filter, is because its filter effect is better than band pass filter; Due to larger power output will be met, so put a low noise amplifier after intermediate frequency filtering again, be select MAX2650 equally; It is SA639 chip that demodulator is selected, and in demodulator SA639 chip internal structure, has a frequency mixer, has carried out frequency and become 10.7M from 40.7M; What comparator was selected is LM311 chip; That singlechip chip is selected is MSP430F149; Because the local frequency of first time mixing is 392.3M, there is no the crystal filter of so large frequency, so produce the frequency of 392.3M by MSP430F149 Single-chip Controlling phase-locked loop chip ADF4360-8; Equally, the square wave of the output of comparator is also input on MSP430F149 single-chip microcomputer and processs and displays.What this receiver received is 2FSK signal, and demodulation mode used adds multiplication frequency discriminator with hardware phase-shift network to complete 2FSK demodulation, namely completes digital demodulation with the hardware circuit of simulation.Next ADS radio frequency simulation software emulation complete machine conceptual scheme is just utilized to obtain simulation result.Whether checking simulation result meets required technical indicator, and reasonably words continue down to carry out.Through check analysis, the simulation result of patent of the present invention meets set technical requirement.Then be just that 2FSK receiver has carried out the general introduction of integrated circuit to patent 433M modulating mode of the present invention, then the chip used by each module is determined, one is divided into 6 modules to form the circuitry figure of final 2FSK receiver, and these explained in summary of the invention.

The design's demodulation be 2FSK signal, below just explain the hardware demodulation process of 2FSK in detail.The phase-shift network of quadrature demodulator adopts the circuit form of resonant tank, uses the dividing potential drop transmission phase-shift network of electric capacity and single-tunded circuit composition as shown in figure 13.

If input voltage is output voltage is then have

$\begin{array}{c}{\stackrel{\·}{U}}_2={\stackrel{\·}{U}}_1\frac{1/(\frac{1}{R}+{\mathrm{j\ωC}}_2+\frac{1}{j\mathrm{\ω}L})}{\frac{1}{{\mathrm{j\ωC}}_1}+1/(\frac{1}{R}+{\mathrm{j\ωC}}_2+\frac{1}{j\mathrm{\ω}L})}\\ ={\stackrel{\·}{U}}_1\frac{{\mathrm{j\ωC}}_1}{\frac{1}{R}+1\mathrm{\ω}(C_1+C_2)+\frac{1}{j\mathrm{\ω}L}}\end{array}---(7-1)$

Order q _l=R/ (ω ₀l), ξ=2 (ω-ω ₀) Q _l/ ω ₀can obtain:

Amplitude-frequency characteristic: $K\left(\mathrm{\ω}\right)=\frac{{\mathrm{\ωC}}_{1}R}{\sqrt{1+{\mathrm{\ξ}}^2}}---(7-2)$

Phase-frequency characteristic:

When ω change is less, namely time, tan ξ ≈ ξ.

The component parameter in resonant tank can be obtained by above formula.This phase shifter is because functional, and structure is simple, is easy to realize, is often used as phase shift multiplication frequency discriminator together with multiplier.

Then for the software code of patent 433M receiver of the present invention writes realization of debugging design process and last test result process.Comprise welding and debug hardware circuit, write code and measuring technology index three part.Verify whether meet one by one according to each set technical indicator, two technical indicators wanted most are sensitivity index and dynamic range index respectively.Be exactly finally be 2FSK transmitter in conjunction with 433M modulating mode, patent 433M modulating mode of the present invention is coordinated to be 2FSK receiver, jointly complete one section of detection of preamble and frame extraction, and the header detected and message waveform are presented at above oscilloscope, further the reasonability of checking patent of the present invention.

Next be Part II embodiment.

First be the sensitivity index testing patent 433M digital FM receiver of the present invention: lower than-55dBm.Embodiment is: adding intermediate frequency from signal source is 433M, frequency deviation is 75K, amplitude is the FM frequency-modulated wave of-55dBm, whether observe the waveform after demodulation with oscilloscope, being good sine wave, its frequency theory should be 75K, but due to input signal amplitude too small-signal can produce distortion, and the amplifier of every one-level has noise and these noises also can be exaggerated, finally cause the signal demodulated to have a small amount of noise, this does not affect the demodulation result of signal.During actual test, selecting range is the FM frequency-modulated wave of-65dBm, if it is namely sinusoidal wave that oscilloscope can demonstrate better symbol waveform, illustrate that this receiver sensitivity is better than the technical indicator required, because-65dBm is more stricter than the sensitivity requirement of-55dBm.Meet the demands through test, illustrate that this receiver sensitivity and receiver frequency range all meet the demands.

Then be the dynamic range index of testing patent 433M digital FM receiver of the present invention: be greater than 40dB.Embodiment is: having tested intermediate frequency during measurement sensitivity is above 433M, frequency deviation is 75K, amplitude is the FM frequency-modulated wave of-65dBm, changing now intermediate frequency into is 433M, and frequency deviation is 75K, and amplitude is the FM frequency-modulated wave of-25dBm, if it is namely sinusoidal wave that oscilloscope still can show good symbol waveform, just illustrate that dynamic range index meets the demands, and meets the demands through test, illustrates that the dynamic range index of this receiver meets the demands.

It is finally Part III embodiment.

Under the prerequisite all met requiring technical indicator, for patent 433M receiver of the present invention, utilizing 433M transmitter, carrying out the work that a detection of preamble message extracts, further the function of checking patent 433M receiver of the present invention.Embodiment is: first utilize 433M transmitter to launch a frame code element, then this frame code element is received with patent 433M receiver of the present invention, certainly first header must be detected, and then frame extracts, finally the information (arbitrary two ASCII character) of launching is presented on oscilloscope.Transmitter modulating mode is 2FSK, and the frequency corresponding to high level is 433.3M, and the frequency corresponding to low level is 422.7M.Chip rate is 50K, namely launches a code element every 20us.Header structure is: 0-20us is high level, 20us-40us is low level, 40us-60us is high level, 60us-140us is low level, 140us-160us is high level, 160us-180us is low level, 180us-200us is high level, 200us-320us is low level.Header structure as shown in Figure 9.The content of message is the ASCII character of A and B, they are both the binary number representations of employing 8,41 (hexadecimals), 65 (decimal systems), 01000001 (binary system) that what A was corresponding is, what B was corresponding is 42 (hexadecimals), 66 (decimal systems), 01000010 (binary system).When test, the task of 433M transmitter is that to launch symbol waveform be that the 2FSK signal of A and B sends patent 433M receiver of the present invention to by antenna, at this 2FSK signal after demodulation, extract through detection of preamble and frame, the waveform of A and B entrained by it and so-called symbol waveform are presented on oscilloscope.Accompanying drawing 10 is header waveforms of oscilloscope display, accompanying drawing 11 is message waveforms that oscilloscope detects, after completing detection of preamble, oscilloscope just have read message information, its formation is 01000001,01000010, just in time binary ASCII character that A and B is corresponding, illustrate oscilloscope completely errorless read message information.In sum, patent of the present invention completes the function of one section of simple detection of preamble and message extraction, demonstrates the function of patent 433M receiver of the present invention further.Can launch other header and message when practice, they are arbitrary.

Above three parts are exactly the embodiment of patent 433M digital FM receiver device of the present invention.Generally speaking patent of the present invention completes the design of 433M receiver, welding, software code write debugging and the debugging of hardware finished product, last hardware finished product is had and receives 433M carrier wave and the function demodulating entrained 2FSK information.2FSK transmitter in conjunction with 433M modulating mode, one people enters two arbitrary ASCII character at 433M frequency modulated transmitter circuit, through the transmission of antenna, this 433M FM receiver can demodulate this ASCII character and is presented on oscilloscope, and it is successful that final testing result also demonstrates patent 433M digital FM receiver of the present invention.Compare with the FM receiver of other high-power, large internal memory, the 433M digital FM receiver apparatus design that patent of the present invention provides is ingenious, rationally distributed, low in energy consumption, highly sensitive, dynamic range is large, adopt the modulation /demodulation pattern of 2FSK, real time communication can be carried out with 433M Digital Frequency Modulation Transmitter well.

Claims (1)

1. a 433M digital FM receiver, comprising: input low noise amplifier and 433M filter segment; 392.3M local vibration source signal circuit section; Frequency mixer and intermediate-frequency filter part; Demodulation secondary frequency down circuit part; The micro-processing section of single-chip microcomputer; The Energy control of whole circuit diagram and ground part, is characterized in that: signal is entered by input low noise amplifier and 433M filter segment; 392.3M local vibration source signal circuit section provides local oscillation signal, 392.3MHz to frequency mixer and intermediate-frequency filter part; Signal completes first time frequency reducing after input low noise amplifier and 433M filter section branch away in frequency mixer and intermediate-frequency filter part, reduces to 40.7M by 433M; Enter demodulation secondary frequency down circuit part again to carry out second time frequency reducing and become 10.7M from 40.7M, carry out demodulation subsequently; Single-chip microcomputer micro-processing section control 392.3M local vibration source signal circuit section and demodulation secondary frequency down circuit part; Energy control and the ground part of whole circuit diagram are module 392.3M local vibration source signal circuit section; ; Demodulation secondary frequency down circuit part; The micro-processing section of single-chip microcomputer provides Digital and analog power supply and earth signal;

Input low noise amplifier and 433M filter segment:

Use low noise amplifier MAX2650; Signal is entered by the tuner P1 of module 1, is gone out 1 pin of the RF2418DS chip entering module 3 by the port 5 of 433M SAW (Surface Acoustic Wave) filter chip U4; P1 is tuner, after tuner receives antenna, comprises the ripple of all frequency ranges of 433M carrier wave, enter chip U3 low noise amplifier MAX2650 by P1 and carry out power amplification, export next stage by port 3 after amplification, what port 4 connected is+5V power supply, port 2 ground connection; The supply power voltage of low noise amplifier MAX2650 is the electric capacity C10 of+5V, 0.1uf and has the electric capacity C11 of polarity 10uf and magnetic bead L4 to carry out filtering to power supply, and the blocking capacitance value at the input/output interface place of MAX2650 is:

$C_{BLOCK}=\frac{53000}{F}\left(pF\right)$

Wherein, the unit of frequency F is MHz, and the carrier frequency of receiver is the capacitance of 433MHz, MAX2650 input/output terminal is 122pF; Its two ends must add electric capacity C101 and the electric capacity C102 of 0.1uf, carry out filtering to direct current signal, and U4 is 433MHz SAW (Surface Acoustic Wave) filter, is entered by 2 pins, output to the pin one of the RF2418DS chip of module 3 from 5 pins;

392.3M local vibration source signal circuit section:

4,5 pins of ADF4360-8 chip are connected to 8 pins of the RF2418DS chip of frequency mixer and intermediate-frequency filter part; The minimum system that MSP430F149 singlechip chip is formed controls ADF4360-8 chip, produces the local frequency of 392.3M; Voltage controlled oscillator output frequency inside ADF4360-8 chip is:

f _VCO＝[(P×B)+A]×f _REFIN/R

Wherein f _vCOfor voltage controlled oscillator output frequency, P is pre-divide ratio, f _rEFINfor reference frequency;

F _cco＝B×Frefin/R

F _ccothe frequency that phase-locked loop exports, F _cco=392.3M, B are the binary registers of 13, and its span is 3 ~ 8191, Frefin is ADF4360-8 chip 16 pin REF _inthe frequency of the active crystal oscillator of input, R is the binary register of 14, and Frefin selects 50M, R=500, B=3923; ADF4360-8 chip 16 pin REF _inthat connect is the active crystal oscillator U12 of 50M; The AGND of the CPGND of 1 pin, the AGND of 3 pins, 8 pins, the AGND of 11 pins, 12 pin C _c, the DGND of 15 pins, the AGND of 22 pins meet in analog i.e. GND; Get the supply power voltage of+3.3V as phase-locked loop ADF4360-8 chip, the CE of the Vvco of 2 pin Avdd, 6 pins, the Dvdd of 21 pins, 23 pins connects the power supply of+3.3V, and each power supply needs to connect the filter circuit the same with in module 1; Chip U13 is the voltage stabilizing sheet AMS1117-3.3 of+3.3V, U13 for phase-locked loop ADF4360-8 chip provides the voltage of+3.3.V, 3 pins inputs, and 2 pins export, and input is+5V power supply, and exporting is exactly+3.3V; 9 pin L ₁, 10 pin L ₂meet resistance R32, a R33 and inductance L 29, a L30 all respectively, wherein resistance R32, R33 is 470 Ω; Inductance value:

$F_o=\frac{1}{2\mathrm{\π}\sqrt{9.3pF(0.9nH+Lext)}}$

In formula, F _othat 392.3M, Lext are required inductance value, Lext=16.8nH; 17 pin CLK, 18 pin DATA, 19 pin LE are connected on MSP430F149 singlechip chip, be connected to I/O port 5.3,5.1,5.4, resistance R22, R24, R2 are 0 Ω, and 20 pin MUXOUT are connected with LED D3,24 pin CP connect a low pass filter, 16 pin REF _inconnect the active crystal oscillator of 50M, the power supply connecting active crystal oscillator need connect filter circuit, and the 50 Ω resistors match circuit that active crystal oscillator pin 3 and phase-locked loop ADF4360-8 chip pin 16 extract directly are connected and are made up of electric capacity C73, C75 of 1nF and the resistance R26 of 51 Ω; Resistance R27, R28, the tuner P12 of 0 Ω are external to frequency spectrograph, whether the frequency produced for phase locked loop ADF4360-8 chip is 392.3MHz, the local frequency that phase-locked loop ADF4360-8 chip produces outputs to frequency mixer 8 pin LOIN from 4 pin RfoutA, and the inductance L 18 of electric capacity C44 and 10nH of the 4pF that RF2418DS chip 8 pin in module 3 connects completes the resistors match of 50 Ω between phase-locked loop ADF4360-8 chip and mixing chip RF2418DS;

Frequency mixer and intermediate-frequency filter part:

U5 chip is RF2418 mixer chip, the pin one of RF2418DS chip connects the port 5 of the U4 chip of input low noise amplifier and 433M filter segment, the pin 8 of RF2418DS chip meets the RfoutA of 4,5 pins connections of the ADF4360-8 chip of 392.3M local vibration source signal circuit section, and the RFIn pin of U2 chip MAX2650 connects 1 pin of the U1 chip of demodulation secondary frequency down circuit part, the inductance L 12 of resistance R8 and 10nH of the 5.11K of the pin one connection of RF2418 chip, 3 pin VDD1 connect+5V DC power supply, and 4 pin VDD2 need not connect, and magnetic bead L13,10uF electric capacity C34,47pF electric capacity C32,0.1uF electric capacity C35 forms filter circuit, and right+5V DC power supply carries out filtering, signal after input low noise amplifier and 433M filter section branch away, frequency mixer RF2418 chip is entered by pin one LNAIN, 11 pin RFIN are entered by 14 pin LNAOUT, signal after mixing is input to the intermediate-frequency filter circuit part IN of this module by 6 pin IF2OUT, the local oscillation signal of the 392.3MHz that 392.3M local vibration source signal circuit section phase-locked loop produces is input to U5 frequency mixer RF2418DS chip by 8 pins, the electric capacity C44 of 4pF and 10nH inductance L 18 complete the resistors match of 50 Ω between ADF4360-8 chip and RF2418DS chip, 7 pin place circuit defaults connect, the 0.1uF electric capacity C40 of 6 pins and 1.5K resistance R13 completes the resistors match of 50 Ω between RF2418DS chip and the intermediate-frequency filter of this module, intermediate-frequency filter part is made up of the inductance L 6 of electric capacity C18,220nH of 33pF, the inductance L 7 of electric capacity C19,220nH of 110pF, the electric capacity C20 of 33pF, signal enters from IN mouth, go out from INI mouth, the pin 6IF2OUT of what IN mouth connect is mixing chip RF2418DS, from the IN of 6 pins out, have two paths of signals, a frequency is 40.7M, another is 825.3M, and low pass filter filtering 825.3M signal retains the signal of 40.7M, signal out enters next low noise amplifier U2 afterwards from INI mouth, the pin 3 of U2 connects the pin one of the SA639 chip of demodulation secondary frequency down circuit part, the pin 4 of U2 connects+5V power supply, power supply connects filter circuit, input pin 1 and the output pin 3 of MAX2650 be all connected 0.1uf every straight filter capacitor C103 and C104,

Demodulation secondary frequency down circuit part:

Select U1 chip SA639 to complete secondary frequency reducing, become 10.7M and demodulation from 40.7M; The intermediate-freuqncy signal of 40.7M is entered into 1 pin of the U1 chip of demodulation secondary frequency down circuit part by the RFIn pin of the U2 chip of module 3; The electric capacity C9 of the inductance L 3 of 760nH, electric capacity C6 and 16pF of 3pF completes the resistors match between the MAX2650 low noise amplifier 50 Ω output resistance of frequency mixer and intermediate-frequency filter part and SA639 demodulation chip 800 Ω input resistance; The C1 of C8 and 1nF of 0.1 μ f carries out every straight filtering to 40.7M signal; SA639 demodulation chip 1,4,24 pins form be a frequency mixer, 2 pin ground connection, 3 pins do not connect, and 4 pins meet the active crystal oscillator U6 of 30M, with 1 pin input 40.7M signal together with complete mixing; 10.7M signal after the inner filtering of SA639 demodulation chip is exported by 24 pin MIXEROUT, filtering is carried out through the ceramic filter PLT1 of first 10.7M, 22 pin IFAMPIN are received after first time filtering, signal comes again 20 pin IFAMPOUT through SA639 demodulation chip inside, and then carry out filtering through the ceramic filter PLT2 of a 10.7M, this time receive 18 pin LIMITER after filtering; 23,21,16,17,19 pin ground connection GND; 5 pin VCC connect+5V power supply; 6,7,8 pin acquiescences connect; The signal of the 10.7M after twice filtering by 15 pins out, connect a phase shift 90 degree of networks, 10.7M signal phase shift before making to enter 90 degree, this phase shift 90 degree of networks are made up of the C27 of C28,11pF of R7,15pF of L11,1.3K of 4.7uH, and the 10.7M signal through phase shift 90 degree enters SA639 demodulation chip by 14 pins; The 10.7M signal without phase shift 90 degree entered by 18 pins is multiplied with the multiplier that the 10.7M signal through phase shift 90 degree entered by 14 pins enters SA639 inside, by generation two components after multiplier, low frequency component high fdrequency component, low frequency component is exactly symbol signal; The connection of chip internal 9 pin one 0 pin be all an operational amplifier, the operational amplifier of 9 pins completes to be penetrated with function, the operational amplifier of 10 pins just in time connects and composes the active low pass filter in two rank with 5.6K resistance R4,5.6K resistance R5,22pF electric capacity C24,33pF electric capacity C26 of outside, only retains the low frequency component of chip rate; 12 pins of SA639 demodulation chip connect+2.5V power supply, obtained by the average dividing potential drop of resistance R9, R10 right+5V power supply both for 22K, 510 Ω resistance R6,10nF electric capacity C25 that 13 pins connect also form low pass filter, again carry out filtering to the low frequency component of chip rate; By 13 pins out be positive low frequency component, and by 11 pins out be negative low frequency component, two paths of differential signals is input to LM311 comparator chip U7 together, from LM311 comparator chip 7 pin export is exactly code element square wave information; 7 pins of LM311 comparator chip are connected on the I/O port P5.5 of MSP430f149 chip U11, carry out detection of preamble, frame extracts and oscilloscope display code element square wave information waveform to information; 1, the 4 pin ground connection of comparator chip U7,5,6 pins do not connect, and 7,8 pins connect+5V power supply, and+5V power supply connects filter circuit;

The micro-processing section of single-chip microcomputer:

17 pin CLK of ADF4360-8 chip, 18 pin DATA, 19 pin LE are connected to the I/O port 5.3,5.1,5.4 of single-chip microcomputer micro-processing section MSP430F149 singlechip chip, and 7 pins of the LM311 comparator chip of module 4 are connected to the I/O port P5.5 of MSP430f149 chip U11; P8 is emulator chip, the minimum system of MSP430F149 singlechip chip selects outside 8M crystal oscillator XTCLK3, P5 is row's pin for subsequent use, P10 connects row's pin of 12864 liquid crystal, U10 and J2 forms serial communication system, U11 is MSP430F149 singlechip chip, and LED liquid crystal D4 connects P1.0 pin, interrupts chip REST1 and forms external interrupt circuit; The voltage stabilizing sheet chip of the supply power voltage of MSP430F149 singlechip chip to be+3.3V, U8 be+3.3V, LED liquid crystal D2 connects+3.3V power supply; + 3.3V voltage stabilizing sheet chip the U13 of phase-locked loop ADF4360-8 chip analogue type, + 3.3V voltage stabilizing sheet chip the U8 of MSP430F149 singlechip chip numeric type, voltage stabilizing sheet U8 has three pins, pin one ground connection, pin 3 be enter termination+5V power supply, pin two is output, exports+3.3V power supply;

The Energy control of whole circuit diagram and ground part:

The all digitally DGND connected by MSP430F149 singlechip chip minimum system and remaining all GND in analog of whole circuit link together; For+5V the power circuit of whole circuit supply ,+5V the power supply of electric capacity C38 to whole circuit of electric capacity C36,0.1uF of 10uF carries out every straight filtering, and LED liquid crystal D1 connects outside+5V power supply, J1 and DC-IN-2 is whole circuit supply+5V electric outlet structure.