CN107239611B - Vector signal analysis device and method - Google Patents

Abstract

The invention discloses a vector signal analysis device and method, and belongs to the technical field of testing. The vector signal analysis device based on the modular instrument has the characteristics of small volume, light weight, low cost, easiness in system expansion and the like, and the hardware module and the software are mutually independent, so that the reusability of the hardware module and the portability of the software are improved. Meanwhile, the vector signal analysis method can carry out multi-angle comprehensive analysis on the acquired data in a time domain, a frequency domain and a modulation domain, and improves the accuracy of signal analysis.

Description

Vector signal analysis device and method

Technical Field

The invention belongs to the technical field of testing, and particularly relates to a vector signal analysis device and method.

Background

Compared with the traditional analog signal, the digital modulation signal has the advantages of strong anti-interference performance, high bandwidth efficiency, good confidentiality and the like, is a main form of current signal communication, and is widely applied to the fields of radar, satellite communication, electronic countermeasure and the like, so that the vector analysis of the digital modulation signal becomes a key problem. Vector Signal Analysis (VSA) enables fast and accurate measurements of complex modulated signals, and is more suitable for analyzing burst signals and modulated signals than for spectral analysis.

In the field of test and measurement, a vector signal analysis device mostly adopts a structural form of a desk-top instrument and is realized in a mode of a hardware platform and resident machine software, wherein the hardware platform comprises a CPU module, a radio frequency front-end signal conditioning module, an analog signal processing module and the like to realize front-end processing of signals, the resident machine software runs in the desk-top instrument to realize demodulation and analysis of the signals, and the hardware platform and the resident machine software need to be used simultaneously to finish the demodulation and analysis.

The existing vector signal analysis method mainly adopts a fixed sampling rate to collect intermediate frequency signals, orthogonal demodulation, IQ conversion and decimal extraction filtering are carried out on a programmable logic device (FPGA and the like) to obtain IQ data with an integral multiple of symbol rate, then the data are transmitted to an upper computer through a bus, and demodulation analysis and display are carried out by resident software.

When a vector signal analysis device based on a desk type instrument structure is used for field testing in the fields of radars, electronic countermeasures, ship-borne equipment, vehicle-mounted equipment and the like, the requirements of miniaturization, flexibility and the like of test equipment and a test system in various fields cannot be met due to the limitation of the volume, the space size and the like of the system. Meanwhile, the hardware platform and the software are in one-to-one relationship, and the reusability of the hardware and the software is poor.

Meanwhile, the existing vector signal analysis method carries out orthogonal demodulation, IQ conversion and decimal extraction filtering in a programmable logic device, can carry out vector analysis in a modulation domain, but cannot fully utilize the acquired original signal data, and cannot carry out comprehensive and accurate signal analysis.

Disclosure of Invention

Aiming at the technical problems in the prior art, the invention provides a vector signal analysis device and method, which are reasonable in design, overcome the defects of the prior art and have good effects.

In order to achieve the purpose, the invention adopts the following technical scheme:

a vector signal analysis device comprises a radio frequency conversion unit, a local oscillator unit, an intermediate frequency sampling unit and upper computer software; the local oscillator unit, the radio frequency conversion unit and the intermediate frequency sampling unit are sequentially connected through a cable; the intermediate frequency sampling unit is in communication connection with upper computer software;

the radio frequency conversion unit comprises a power protection circuit, a fixed attenuator, a first selection switch, a second selection switch, a third selection switch, a fourth selection switch, a fifth selection switch, a sixth selection switch, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first program-controlled attenuator, a second program-controlled attenuator, a first mixer, a second mixer, a third mixer, a first band-pass filter, a second band-pass filter and a third band-pass filter; the power protection circuit, the fixed attenuator, one end of the first selection switch is connected in sequence through a line, the other end of the first selection switch is connected with one end of the second selection switch and one end of the third selection switch through a line, the other end of the second selection switch is connected with one end of the first program-controlled attenuator through a first amplifier or a through path, the other end of the first program-controlled attenuator, the third amplifier, the first mixer, the first band-pass filter, the second mixer and one end of the second band-pass filter are connected in sequence through a line, the other end of the third selection switch is connected with one end of the second program-controlled attenuator through a second amplifier or a through path, the other end of the second program-controlled attenuator, the fourth amplifier, the third mixer and one end of the third band-pass filter are connected in sequence through a line, the other end of the second band-pass filter and the other end of the third band-pass filter are connected to one end of the sixth selection switch through lines One end;

the local oscillator unit comprises a 10MHz crystal oscillator, a 100MHz crystal oscillator, an analog switch, a phase discriminator, a power divider, a first 10 frequency divider, a second 10 frequency divider, a 10 frequency multiplier, a first amplifier, a second amplifier, a third amplifier, a local oscillator phase-locked loop, a 1GHz filter, a 100MHz filter, a 10MHz filter, a first 6dB attenuator, a second 6dB attenuator and a third 6dB attenuator;

the 10MHz crystal oscillator phase discriminator is connected with the analog switch, the phase discriminator, the 100MHz crystal oscillator, the power divider, the first 6dB attenuator and the first 10 frequency divider form a phase-locked loop circuit, the analog switch is connected with the phase discriminator of the phase-locked loop circuit, one end of the second 6dB attenuator is connected with the power divider of the phase-locked loop circuit, the other end of the second 6dB attenuator is respectively connected with one end of the first amplifier and one end of the second amplifier through lines, the other end of the first amplifier is connected with the local oscillator phase-locked loop through lines, the other end of the second amplifier is sequentially connected with the 10 frequency multiplier and the 1GHz filter through lines, one end of the third amplifier is connected with the first 6dB attenuator of the phase-locked loop circuit, the other end of the third amplifier is connected with one end of the third 6dB attenuator through lines, the other end of the third 6dB attenuator is respectively connected with one end of the 100MHz filter and one end of the, the other end of the second 10-frequency divider is connected with the 10MHz filter through a line;

the intermediate frequency sampling unit comprises a signal conditioning module, a high-speed AD acquisition module, a high-speed data processing and storing module, a clock generating module, an RAM and a PXI interface; the signal conditioning module, the high-speed AD acquisition module and the high-speed data processing and storing module are sequentially connected through a circuit, the clock generating module is connected with the high-speed AD acquisition module through a circuit, the RAM is connected with an RAM storage logic unit in the high-speed data processing and storing module through a circuit, and the PXI interface is connected with a PXI interface control logic unit in the high-speed data processing and storing module through a circuit;

the upper computer software comprises three functional modules of measurement signal demodulation analysis, reference signal generation and error parameter analysis;

a measurement signal demodulation and analysis module configured to perform orthogonal decomposition, digital filtering, sampling rate conversion, matched filtering, timing correction, frequency offset correction, phase offset correction, timing error estimation, frequency error estimation, and phase error estimation on the intermediate frequency signal;

a reference signal generating module configured to perform symbol decision and symbol mapping on the measurement signal and then generate a reference signal through a shaping filter;

and the error parameter analysis module is configured to compare the measurement signal with the reference signal, extract a series of modulation quality error indexes including amplitude vector error, phase error, amplitude error, IQ offset, origin offset and quadrature error, and display the result to a user.

Preferably, the low-frequency band signal is 9 kHz-500 MHz; the high frequency band signal is 500 MHz-3 GHz.

In addition, the present invention also provides a vector signal analysis method using the vector signal analysis apparatus as described above, including the steps of:

step 1: the local oscillation unit firstly selects an internal reference signal and an external reference signal through an analog switch, the internal reference signal is provided by a 10MHz crystal oscillator, and the external reference signal is input by an external 10MHz signal; then, a reference signal selected by the analog switch is provided to the phase discriminator to be used as a reference of the 100MHz crystal oscillator, and the 100MHz signal is divided into five paths after passing through the power divider: after the first path passes through the first 6dB attenuator and the first 10 frequency divider, the output 10MHz signal is used as the phase discrimination input of the phase discriminator and is compared with the input reference signal, and the phase locking of the 100MHz signal is completed; the second path enters a local oscillator phase-locked loop after passing through a second 6dB attenuator and a first amplifier to be used as a reference of the local oscillator phase-locked loop, outputs a local oscillator signal of 25 MHz-3 GHz and provides the local oscillator signal for the step 2 for frequency mixing; the third path passes through a second 6dB attenuator, a second amplifier and 10 frequency doubling, and then outputs a 1GHz signal through a 1GHz filter; after passing through the third 6dB attenuator, the fourth path outputs a 100MHz signal through a 100MHz filter, and the 100MHz signal is provided for the intermediate frequency sampling unit in the step 3; the fifth path outputs a 10MHz signal through a 10MHz filter after passing through a third 6dB attenuator and a second 10 frequency divider;

step 2: a radio frequency signal enters a radio frequency conversion unit through a radio frequency input port, firstly passes through a power protection circuit and a fixed attenuator, is divided into two paths of signals of a high frequency band and a low frequency band through a first selection switch, passes through a second selection switch, then passes through a first amplifier or a through channel, then enters a fourth selection switch, passes through a first program control attenuator and a third amplifier for power adjustment, is mixed with 782.259 MHz-1285.25 MHz signals generated by a local oscillation unit through a first mixer to obtain a 782.25MHz first intermediate frequency signal, passes through a first band-pass filter, is mixed with 719.75MHz fixed frequency signals in the radio frequency conversion unit through a second mixer to obtain a 62.5MHz second intermediate frequency signal, and is filtered through a second band-pass filter; the high-frequency band signal passes through a third selection switch, then passes through a second amplifier or a through path, enters a fifth selection switch, is subjected to power adjustment through a second programmable attenuator and a fourth amplifier, then is mixed with 687.5-2812.5 MHz signals generated by a local oscillator unit through a third mixer, and passes through a third band-pass filter, so that a 187.5MHz third intermediate-frequency signal is obtained; after passing through the band-pass filter, the high-low band intermediate frequency signals are combined into one path of output through a sixth selection switch, and the output path of the output path is sent to the intermediate frequency sampling unit in the step 3 for processing;

and step 3: the intermediate frequency signal processed by the radio frequency conversion unit in the step 2 is firstly subjected to signal conditioning including amplitude control and differential conversion before sampling at a signal conditioning module of an intermediate frequency sampling unit, then a clock generation module generates a 250MHz sampling clock by using the 100MHz clock provided in the step 1, a high-speed AD acquisition module is driven to carry out ADC (analog-to-digital converter) conversion, the converted signal is quantized into a digital signal and then enters a high-speed data processing and storing module for preprocessing, RAM (random access memory) is used for carrying out real-time data storage after the preprocessing, sampled data output by the high-speed AD acquisition module is subjected to speed reduction and caching, then the data are combined and stored in parallel for carrying out the real-time RAM storage, and meanwhile, the acquired data are transmitted to upper computer software;

and 4, step 4: the upper computer software carries out data analysis and processing on the intermediate frequency signals collected in the step 3; the method specifically comprises the following steps:

step 4.1: the measurement signal demodulation and analysis module carries out orthogonal decomposition on the intermediate frequency signal, and the I/Q signal after orthogonal decomposition is processed by algorithms including digital filtering, sampling rate conversion, matched filtering, timing correction, frequency deviation correction, phase deviation correction, timing error estimation, frequency error estimation and phase error estimation to obtain a baseband signal of the measured signal;

step 4.2: the reference signal generation module carries out symbol judgment and code element mapping according to a baseband signal of a detected signal to obtain code stream information of an original signal, and the reference baseband signal generator and a reference signal filter carry out forming filtering to generate an ideal reference signal required by modulation quality analysis;

step 4.3: the error parameter analysis module compares the measurement signal with the reference signal, extracts a series of modulation quality error indexes including an amplitude vector error, a phase error, an amplitude error, an IQ bias, an origin offset and a quadrature error, and displays the result to a user.

The invention has the following beneficial technical effects:

the vector signal analysis device based on the modular instrument has the characteristics of small volume, light weight, low cost, easiness in system expansion and the like, and the hardware module and the software are mutually independent, so that the reusability of the hardware module and the portability of the software are improved. Meanwhile, the vector signal analysis method can carry out multi-angle comprehensive analysis on the acquired data in a time domain, a frequency domain and a modulation domain, and improves the accuracy of signal analysis.

Drawings

Fig. 1 is a schematic block diagram of a vector signal analyzer.

Fig. 2 is a schematic block diagram of the rf frequency conversion unit.

Fig. 3 is a schematic block diagram of a local oscillation unit.

Fig. 4 is a schematic block diagram of an intermediate frequency sampling unit.

Fig. 5 is a signal processing flowchart of the upper computer software.

Detailed Description

The invention is described in further detail below with reference to the following figures and detailed description:

example 1:

as shown in fig. 1, a vector signal analysis apparatus includes a radio frequency conversion unit, a local oscillator unit, and an intermediate frequency sampling unit, and is configured with upper computer software; the local oscillator unit, the radio frequency conversion unit and the intermediate frequency sampling unit are sequentially connected through a cable; the intermediate frequency sampling unit is in communication connection with upper computer software; the radio frequency conversion unit (as shown in fig. 2) includes a power protection circuit, a fixed attenuator, a first selection switch, a second selection switch, a third selection switch, a fourth selection switch, a fifth selection switch, a sixth selection switch, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first programmable attenuator, a second programmable attenuator, a first mixer, a second mixer, a third mixer, a first band-pass filter, a second band-pass filter, and a third band-pass filter; the power protection circuit, the fixed attenuator, one end of the first selection switch is connected in sequence through a line, the other end of the first selection switch is connected with one end of the second selection switch and one end of the third selection switch through a line, the other end of the second selection switch is connected with one end of the first program-controlled attenuator through a first amplifier or a through path, the other end of the first program-controlled attenuator, the third amplifier, the first mixer, the first band-pass filter, the second mixer and one end of the second band-pass filter are connected in sequence through a line, the other end of the third selection switch is connected with one end of the second program-controlled attenuator through a second amplifier or a through path, the other end of the second program-controlled attenuator, the fourth amplifier, the third mixer and one end of the third band-pass filter are connected in sequence through a line, the other end of the second band-pass filter and the other end of the third band-pass filter are connected to one end of the sixth selection switch through lines One end;

the local oscillation unit (as shown in fig. 3) includes a 10MHz crystal oscillator, a 100MHz crystal oscillator, an analog switch, a phase discriminator, a power divider, a first 10 frequency divider, a second 10 frequency divider, a 10 frequency multiplier, a first amplifier, a second amplifier, a third amplifier, a local oscillation phase-locked loop, a 1GHz filter, a 100MHz filter, a 10MHz filter, a first 6dB attenuator, a second 6dB attenuator, and a third 6dB attenuator;

the 10MHz crystal oscillator phase discriminator is connected with the analog switch, the phase discriminator, the 100MHz crystal oscillator, the power divider, the first 6dB attenuator and the first 10 frequency divider form a phase-locked loop circuit, the analog switch is connected with the phase discriminator of the phase-locked loop circuit, one end of the second 6dB attenuator is connected with the power divider of the phase-locked loop circuit, the other end of the second 6dB attenuator is respectively connected with one end of the first amplifier and one end of the second amplifier through lines, the other end of the first amplifier is connected with the local oscillator phase-locked loop through lines, the other end of the second amplifier is sequentially connected with the 10 frequency multiplier and the 1GHz filter through lines, one end of the third amplifier is connected with the first 6dB attenuator of the phase-locked loop circuit, the other end of the third amplifier is connected with one end of the third 6dB attenuator through lines, the other end of the third 6dB attenuator is respectively connected with one end of the 100MHz filter and one end of the, the other end of the second 10-frequency divider is connected with the 10MHz filter through a line;

the intermediate frequency sampling unit (as shown in fig. 4) comprises a signal conditioning module, a high-speed AD acquisition module, a high-speed data processing and storing module, a clock generating module, an RAM, and a PXI interface; the signal conditioning module, the high-speed AD acquisition module and the high-speed data processing and storing module are sequentially connected through a circuit, the clock generating module is connected with the high-speed AD acquisition module through a circuit, the RAM is connected with an RAM storage logic unit in the high-speed data processing and storing module through a circuit, and the PXI interface is connected with a PXI interface control logic unit in the high-speed data processing and storing module through a circuit;

the upper computer software (as shown in fig. 5) comprises three functional modules of measurement signal demodulation analysis, reference signal generation and error parameter analysis;

a measurement signal demodulation and analysis module configured to perform orthogonal decomposition, digital filtering, sampling rate conversion, matched filtering, timing correction, frequency offset correction, phase offset correction, timing error estimation, frequency error estimation, and phase error estimation on the intermediate frequency signal;

a reference signal generating module configured to perform symbol decision and symbol mapping on the measurement signal and then generate a reference signal through a shaping filter;

and the error parameter analysis module is configured to compare the measurement signal with the reference signal, extract a series of modulation quality error indexes including amplitude vector error, phase error, amplitude error, IQ offset, origin offset and quadrature error, and display the result to a user.

The low-frequency band signal is 9 kHz-500 MHz; the high frequency band signal is 500 MHz-3 GHz.

Example 2:

on the basis of the above embodiment, the present invention further provides a vector signal analysis method, including the steps of:

step 1: the local oscillation unit firstly selects an internal reference signal and an external reference signal through an analog switch, the internal reference signal is provided by a 10MHz crystal oscillator, and the external reference signal is input by an external 10MHz signal; then, a reference signal selected by the analog switch is provided to the phase discriminator to be used as a reference of the 100MHz crystal oscillator, and the 100MHz signal is divided into five paths after passing through the power divider: after the first path passes through the first 6dB attenuator and the first 10 frequency divider, the output 10MHz signal is used as the phase discrimination input of the phase discriminator and is compared with the input reference signal, and the phase locking of the 100MHz signal is completed; the second path enters a local oscillator phase-locked loop after passing through a second 6dB attenuator and a first amplifier to be used as a reference of the local oscillator phase-locked loop, outputs a local oscillator signal of 25 MHz-3 GHz and provides the local oscillator signal for the step 2 for frequency mixing; the third path passes through a second 6dB attenuator, a second amplifier and 10 frequency doubling, and then outputs a 1GHz signal through a 1GHz filter; after passing through the third 6dB attenuator, the fourth path outputs a 100MHz signal through a 100MHz filter, and the 100MHz signal is provided for the intermediate frequency sampling unit in the step 3; the fifth path outputs a 10MHz signal through a 10MHz filter after passing through a third 6dB attenuator and a second 10 frequency division;

step 2: a radio frequency signal enters a radio frequency conversion unit through a radio frequency input port, firstly passes through a power protection circuit and a fixed attenuator, is divided into two paths of signals of a high frequency band and a low frequency band through a first selection switch, passes through a second selection switch, then passes through a first amplifier or a through channel, then enters a fourth selection switch, passes through a first program control attenuator and a third amplifier for power adjustment, is mixed with 782.259 MHz-1285.25 MHz signals generated by a local oscillation unit through a first mixer to obtain a 782.25MHz first intermediate frequency signal, passes through a first band-pass filter, is mixed with 719.75MHz fixed frequency signals in the radio frequency conversion unit through a second mixer to obtain a 62.5MHz second intermediate frequency signal, and is filtered through a second band-pass filter; the high-frequency band signal passes through a third selection switch, then passes through a second amplifier or a through path, enters a fifth selection switch, is subjected to power adjustment through a second programmable attenuator and a fourth amplifier, then is mixed with 687.5-2812.5 MHz signals generated by a local oscillator unit through a third mixer, and passes through a third band-pass filter, so that a 187.5MHz third intermediate-frequency signal is obtained; after passing through the band-pass filter, the high-low band intermediate frequency signals are combined into one path of output through a sixth selection switch, and the output path of the output path is sent to the intermediate frequency sampling unit in the step 3 for processing;

and step 3: the intermediate frequency signal processed by the radio frequency conversion unit in the step 2 is firstly subjected to signal conditioning including amplitude control and differential conversion before sampling at a signal conditioning module of an intermediate frequency sampling unit, then a clock generation module generates a 250MHz sampling clock by using the 100MHz clock provided in the step 1, a high-speed AD acquisition module is driven to carry out ADC (analog-to-digital converter) conversion, the converted signal is quantized into a digital signal and then enters a high-speed data processing and storing module for preprocessing, RAM (random access memory) is used for carrying out real-time data storage after the preprocessing, sampled data output by the high-speed AD acquisition module is subjected to speed reduction and caching, then the data are combined and stored in parallel for carrying out the real-time RAM storage, and meanwhile, the acquired data are transmitted to upper computer software;

and 4, step 4: the upper computer software carries out data analysis and processing on the intermediate frequency signals collected in the step 3; the method specifically comprises the following steps:

step 4.1: the measurement signal demodulation and analysis module carries out orthogonal decomposition on the intermediate frequency signal, and the I/Q signal after orthogonal decomposition is processed by algorithms including digital filtering, sampling rate conversion, matched filtering, timing correction, frequency deviation correction, phase deviation correction, timing error estimation, frequency error estimation and phase error estimation to obtain a baseband signal of the measured signal;

step 4.2: the reference signal generation module carries out symbol judgment and code element mapping according to a baseband signal of a detected signal to obtain code stream information of an original signal, and the reference baseband signal generator and a reference signal filter carry out forming filtering to generate an ideal reference signal required by modulation quality analysis;

step 4.3: the error parameter analysis module compares the measurement signal with the reference signal, extracts a series of modulation quality error indexes including an amplitude vector error, a phase error, an amplitude error, an IQ bias, an origin offset and a quadrature error, and displays the result to a user.

It is to be understood that the above description is not intended to limit the present invention, and the present invention is not limited to the above examples, and those skilled in the art may make modifications, alterations, additions or substitutions within the spirit and scope of the present invention.

Claims (3)

1. A vector signal analysis apparatus, characterized in that: the system comprises a radio frequency conversion unit, a local oscillator unit and an intermediate frequency sampling unit, and is configured with upper computer software; the local oscillator unit, the radio frequency conversion unit and the intermediate frequency sampling unit are sequentially connected through a cable; the intermediate frequency sampling unit is in communication connection with upper computer software;

the radio frequency conversion unit comprises a power protection circuit, a fixed attenuator, a first selection switch, a second selection switch, a third selection switch, a fourth selection switch, a fifth selection switch, a sixth selection switch, a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a first program-controlled attenuator, a second program-controlled attenuator, a first mixer, a second mixer, a third mixer, a first band-pass filter, a second band-pass filter and a third band-pass filter; the power protection circuit, the fixed attenuator, one end of the first selection switch is connected in sequence through a line, the other end of the first selection switch is connected with one end of the second selection switch and one end of the third selection switch through a line, the other end of the second selection switch is connected with one end of the first program-controlled attenuator through a first amplifier or a through path, the other end of the first program-controlled attenuator, the third amplifier, the first mixer, the first band-pass filter, the second mixer and one end of the second band-pass filter are connected in sequence through a line, the other end of the third selection switch is connected with one end of the second program-controlled attenuator through a second amplifier or a through path, the other end of the second program-controlled attenuator, the fourth amplifier, the third mixer and one end of the third band-pass filter are connected in sequence through a line, the other end of the second band-pass filter and the other end of the third band-pass filter are connected to one end of the sixth selection switch through lines One end;

the local oscillator unit comprises a 10MHz crystal oscillator, a 100MHz crystal oscillator, an analog switch, a phase discriminator, a power divider, a first 10 frequency divider, a second 10 frequency divider, a 10 frequency multiplier, a first amplifier, a second amplifier, a third amplifier, a local oscillator phase-locked loop, a 1GHz filter, a 100MHz filter, a 10MHz filter, a first 6dB attenuator, a second 6dB attenuator and a third 6dB attenuator;

the 10MHz crystal oscillator phase discriminator is connected with the analog switch, the phase discriminator, the 100MHz crystal oscillator, the power divider, the first 6dB attenuator and the first 10 frequency divider form a phase-locked loop circuit, the analog switch is connected with the phase discriminator of the phase-locked loop circuit, one end of the second 6dB attenuator is connected with the power divider of the phase-locked loop circuit, the other end of the second 6dB attenuator is respectively connected with one end of the first amplifier and one end of the second amplifier through lines, the other end of the first amplifier is connected with the local oscillator phase-locked loop through lines, the other end of the second amplifier is sequentially connected with the 10 frequency multiplier and the 1GHz filter through lines, one end of the third amplifier is connected with the first 6dB attenuator of the phase-locked loop circuit, the other end of the third amplifier is connected with one end of the third 6dB attenuator through lines, the other end of the third 6dB attenuator is respectively connected with one end of the 100MHz filter and one end of the, the other end of the second 10-frequency divider is connected with the 10MHz filter through a line;

the intermediate frequency sampling unit comprises a signal conditioning module, a high-speed AD acquisition module, a high-speed data processing and storing module, a clock generating module, an RAM and a PXI interface; the signal conditioning module, the high-speed AD acquisition module and the high-speed data processing and storing module are sequentially connected through a circuit, the clock generating module is connected with the high-speed AD acquisition module through a circuit, the RAM is connected with an RAM storage logic unit in the high-speed data processing and storing module through a circuit, and the PXI interface is connected with a PXI interface control logic unit in the high-speed data processing and storing module through a circuit;

the upper computer software comprises three functional modules of measurement signal demodulation analysis, reference signal generation and error parameter analysis;

a measurement signal demodulation and analysis module configured to perform orthogonal decomposition, digital filtering, sampling rate conversion, matched filtering, timing correction, frequency offset correction, phase offset correction, timing error estimation, frequency error estimation, and phase error estimation on the intermediate frequency signal;

a reference signal generating module configured to perform symbol decision and symbol mapping on the measurement signal and then generate a reference signal through a shaping filter;

and the error parameter analysis module is configured to compare the measurement signal with the reference signal, extract a series of modulation quality error indexes including amplitude vector error, phase error, amplitude error, IQ offset, origin offset and quadrature error, and display the result to a user.

2. The vector signal analysis device according to claim 1, characterized in that: the low-frequency band signal is 9 kHz-500 MHz; the high frequency band signal is 500 MHz-3 GHz.

3. A vector signal analysis method, characterized by: a vector signal analyzing apparatus according to claim 1, comprising the steps of:

step 1: the local oscillation unit firstly selects an internal reference signal and an external reference signal through an analog switch, the internal reference signal is provided by a 10MHz crystal oscillator, and the external reference signal is input by an external 10MHz signal; then, a reference signal selected by the analog switch is provided to the phase discriminator to be used as a reference of the 100MHz crystal oscillator, and the 100MHz signal is divided into five paths after passing through the power divider: after the first path passes through the first 6dB attenuator and the first 10 frequency divider, the output 10MHz signal is used as the phase discrimination input of the phase discriminator and is compared with the input reference signal, and the phase locking of the 100MHz signal is completed; the second path enters a local oscillator phase-locked loop after passing through a second 6dB attenuator and a first amplifier to be used as a reference of the local oscillator phase-locked loop, outputs a local oscillator signal of 25 MHz-3 GHz and provides the local oscillator signal for the step 2 for frequency mixing; the third path passes through a second 6dB attenuator, a second amplifier and 10 frequency doubling, and then outputs a 1GHz signal through a 1GHz filter; after passing through the third 6dB attenuator, the fourth path outputs a 100MHz signal through a 100MHz filter, and the 100MHz signal is provided for the intermediate frequency sampling unit in the step 3; the fifth path outputs a 10MHz signal through a 10MHz filter after passing through a third 6dB attenuator and a second 10 frequency divider;

step 2: a radio frequency signal enters a radio frequency conversion unit through a radio frequency input port, firstly passes through a power protection circuit and a fixed attenuator, is divided into two paths of signals of a high frequency band and a low frequency band through a first selection switch, passes through a second selection switch, then passes through a first amplifier or a through channel, then enters a fourth selection switch, passes through a first program control attenuator and a third amplifier for power adjustment, is mixed with 782.259 MHz-1285.25 MHz signals generated by a local oscillation unit through a first mixer to obtain a 782.25MHz first intermediate frequency signal, passes through a first band-pass filter, is mixed with 719.75MHz fixed frequency signals in the radio frequency conversion unit through a second mixer to obtain a 62.5MHz second intermediate frequency signal, and is filtered through a second band-pass filter; the high-frequency band signal passes through a third selection switch, then passes through a second amplifier or a through path, enters a fifth selection switch, is subjected to power adjustment through a second programmable attenuator and a fourth amplifier, then is mixed with 687.5-2812.5 MHz signals generated by a local oscillator unit through a third mixer, and passes through a third band-pass filter, so that a 187.5MHz third intermediate-frequency signal is obtained; after passing through the band-pass filter, the high-low band intermediate frequency signals are combined into one path of output through a sixth selection switch, and the output path of the output path is sent to the intermediate frequency sampling unit in the step 3 for processing;

and step 3: the intermediate frequency signal processed by the radio frequency conversion unit in the step 2 is firstly subjected to signal conditioning including amplitude control and differential conversion before sampling at a signal conditioning module of an intermediate frequency sampling unit, then a clock generation module generates a 250MHz sampling clock by using the 100MHz clock provided in the step 1, a high-speed AD acquisition module is driven to carry out ADC (analog-to-digital converter) conversion, the converted signal is quantized into a digital signal and then enters a high-speed data processing and storing module for preprocessing, RAM (random access memory) is used for carrying out real-time data storage after the preprocessing, sampled data output by the high-speed AD acquisition module is subjected to speed reduction and caching, then the data are combined and stored in parallel for carrying out the real-time RAM storage, and meanwhile, the acquired data are transmitted to upper computer software;

and 4, step 4: the upper computer software carries out data analysis and processing on the intermediate frequency signals collected in the step 3; the method specifically comprises the following steps:

step 4.1: the measurement signal demodulation and analysis module carries out orthogonal decomposition on the intermediate frequency signal, and the I/Q signal after orthogonal decomposition is processed by algorithms including digital filtering, sampling rate conversion, matched filtering, timing correction, frequency deviation correction, phase deviation correction, timing error estimation, frequency error estimation and phase error estimation to obtain a baseband signal of the measured signal;

step 4.2: the reference signal generation module carries out symbol judgment and code element mapping according to a baseband signal of a detected signal to obtain code stream information of an original signal, and the reference baseband signal generator and a reference signal filter carry out forming filtering to generate an ideal reference signal required by modulation quality analysis;

step 4.3: the error parameter analysis module compares the measurement signal with the reference signal, extracts a series of modulation quality error indexes including an amplitude vector error, a phase error, an amplitude error, an IQ bias, an origin offset and a quadrature error, and displays the result to a user.

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