CN105375887B - Buffer amplifying circuit - Google Patents
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- CN105375887B CN105375887B CN201510882013.0A CN201510882013A CN105375887B CN 105375887 B CN105375887 B CN 105375887B CN 201510882013 A CN201510882013 A CN 201510882013A CN 105375887 B CN105375887 B CN 105375887B
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Abstract
The application discloses buffering amplifier circuit, amplifier circuit includes: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; the bias amplifying unit comprises a bias resistor, a first transistor and a second transistor; an input signal is transmitted to the grids of the first transistor and the second transistor through a signal input end of the amplifying circuit, and is amplified by the first transistor and the second transistor to be output as a first signal through a signal output end of the bias amplifying unit; the first compensation unit and the second compensation unit are used for providing negative feedback to the bias amplification unit, so that the signal bandwidth of the bias amplification unit is improved, the rising edge and the falling edge of the output signal of the amplification circuit are steep, the modulation of the output signal of the amplification circuit by the 1/f noise of the transistor is reduced, and the improved phase noise performance of the output signal is obtained.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a buffer amplifying circuit.
Background
Buffer amplifiers are widely used in integrated systems on chip and in communication systems. Fig. 1 is a circuit diagram of a buffer amplifier generally used in the prior art, and as shown in fig. 1, the buffer amplifier includes a bias resistor R0, a first transistor M1 and a second transistor M2, wherein one end of the bias resistor R0 is connected to the gates of the first transistor M1 and the second transistor M2 to serve as a signal input terminal Vin of the buffer amplifier, and the other end is connected to the drains of the first transistor M1 and the second transistor M2 to serve as a signal output terminal G; the first transistor M1 is an N-channel enhanced field effect transistor, the substrate and the source electrode of the first transistor M1 are grounded, the second transistor M2 is a P-channel enhanced field effect transistor, and the substrate and the source electrode of the second transistor M2 are connected with a direct current power supply VDD; the bias resistor R0 is used to bias the first transistor M1 and the second transistor M2 in a saturation amplification region, so that the input signal passing through the signal input terminal Vin can be amplified by the first transistor M1 and the second transistor M2 and then output.
Since flicker noise (i.e., 1/f noise) is generated by random fluctuation of current due to defects of a semiconductor material, which is unavoidable at present, in the buffer amplifier, while amplifying an input signal, 1/f noise of a transistor is modulated on an amplified output signal, which is expressed as phase noise of the output signal, and the excessive phase noise makes it difficult for the buffer amplifier to meet the requirements of high-performance communication systems and on-chip integrated systems.
Therefore, a buffer amplifier with less phase noise of the output signal is needed.
Disclosure of Invention
The embodiment of the invention provides a buffer amplifying circuit which has better phase noise performance.
A buffer amplification circuit, comprising: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; wherein,
the bias amplifying unit comprises a bias resistor, a first transistor and a second transistor; the gates of the first transistor and the second transistor are connected with one end of the bias resistor to serve as a signal input end of the amplifying circuit, the drains of the first transistor and the second transistor are connected with the other end of the bias resistor to serve as a signal output end of the bias amplifying unit, the source of the first transistor is connected with the first compensation unit, the source of the second transistor is connected with the second compensation unit, an input signal is transmitted to the gates of the first transistor and the second transistor through the signal input end of the amplifying circuit, and the input signal is amplified by the first transistor and the second transistor and then is output as a first signal through the signal output end of the bias amplifying unit;
one end of the first compensation unit is connected with the source electrode of the first transistor, and the other end of the first compensation unit is grounded and is used for providing negative feedback for the bias amplification unit and improving the signal bandwidth of the bias amplification unit;
one end of the second compensation unit is connected with the source electrode of the second transistor, and the other end of the second compensation unit is connected with a power supply and used for providing negative feedback for the bias amplification unit and improving the signal bandwidth of the bias amplification unit.
Preferably, the first compensation unit includes a first resistor and a first capacitor, the first resistor is connected in parallel with the first capacitor, one end of the first resistor is connected to the source of the first transistor, and the other end of the first resistor is grounded.
Preferably, the second compensation unit includes a second resistor and a second capacitor, the second resistor is connected in parallel with the second capacitor, one end of the second resistor is connected to the source of the second transistor, and the other end of the second resistor is connected to a power supply.
Preferably, the offset amplification unit further includes a compensation amplification unit, and the compensation amplification unit includes: a third transistor and a fourth transistor; wherein,
the grid electrodes of the third transistor and the fourth transistor are connected with the signal input end of the amplifying circuit, the drain electrodes of the third transistor and the fourth transistor are connected with the signal output end of the bias amplifying unit, the third transistor is an N-channel enhanced field effect transistor, the source electrode and the substrate of the third transistor are grounded, the fourth transistor is a P-channel enhanced field effect transistor, and the source electrode and the substrate of the fourth transistor are connected with a power supply;
the input signal is transmitted to the grid electrodes of the third transistor and the fourth transistor through the signal input end of the amplifying circuit, the input signal is amplified through the third transistor and the fourth transistor to be used as a second signal, the second signal and the first signal are superposed to form a second composite signal, and the second composite signal is output by the signal output end of the bias amplifying unit, so that the signal gain of the amplifying circuit is improved.
Preferably, the amplifying circuit further comprises a first inverting amplifying unit, wherein a signal input end of the first inverting amplifying unit is connected to a signal output end of the bias amplifying unit, and is configured to perform inverting amplification on an output signal of the bias amplifying unit and output a third signal through a signal output end of the first inverting amplifying unit.
Preferably, the first inverting amplification unit includes a fifth transistor and a sixth transistor; wherein,
the grid electrodes of the fifth transistor and the sixth transistor are connected with the signal output end of the bias amplification unit and used as the signal input end of the first inverting amplification unit, the drain electrodes of the fifth transistor and the sixth transistor are connected and used as the signal output end of the first inverting amplification unit, the fifth transistor is an N-channel enhanced field effect transistor, the source electrode and the substrate of the fifth transistor are grounded, the sixth transistor is a P-channel enhanced field effect transistor, the source electrode and the substrate of the sixth transistor are connected with a direct-current power supply, the output signal of the bias amplification unit is transmitted to the grid electrodes of the fifth transistor and the sixth transistor through the signal input end of the first inverting amplification unit, and a third signal is output through the signal output end of the first inverting amplification unit after the inverting amplification of the fifth transistor and the sixth transistor.
Preferably, the amplifying circuit further comprises a second inverting amplifying unit, wherein a signal input end of the second inverting amplifying unit is connected to a signal output end of the first inverting amplifying unit, and is configured to perform inverting amplification on the third signal and output a fourth signal through a signal output end of the second inverting amplifying unit.
Preferably, the second inverting amplification unit includes: a seventh transistor and an eighth transistor; wherein,
the gates of the seventh transistor and the eighth transistor are connected to the signal output end of the first inverting amplifying unit and used as the signal input end of the second inverting amplifying unit, the drains of the seventh transistor and the eighth transistor are connected and used as the signal output end of the second inverting amplifying unit, the seventh transistor is an N-channel enhanced field effect transistor, the source electrode and the substrate of the seventh transistor are grounded, the eighth transistor is a P-channel enhanced field effect transistor, the source electrode and the substrate of the eighth transistor are connected to a direct-current power supply, the third signal is transmitted to the gates of the seventh transistor and the eighth transistor through the signal input end of the second inverting amplifying unit, and a fourth signal is output from the signal output end of the second inverting amplifying unit after the third signal is amplified in an inverting manner by the seventh transistor and the eighth transistor.
Preferably, the amplifying circuit further includes: a blocking capacitor;
one end of the blocking capacitor is used as a signal input end of the amplifying circuit, and the other end of the blocking capacitor is connected to the connection nodes of the grid electrodes of the first transistor and the second transistor and the bias resistor and used for blocking the influence of the direct current level of the input signal on the amplifying circuit.
Preferably, the first transistor is an N-channel enhancement type field effect transistor, and the second transistor is a P-channel enhancement type field effect transistor.
Compared with the prior art, the technical scheme has the following advantages:
an embodiment of the present invention provides a buffer amplifier circuit, including: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; the first compensation unit and the second compensation unit provide negative feedback for the bias amplification unit, so that the signal bandwidth of the bias amplification unit is widened, the rising edge and the falling edge of the output signal of the amplification circuit become steep, the modulation of the output signal of the amplification circuit by the 1/f noise of the transistor is reduced, and the improved phase noise performance of the output signal is obtained.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a circuit diagram of a buffer amplifier used in the prior art;
fig. 2 is a circuit diagram of a buffer amplifier circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a variation of gain bandwidth in an amplifying circuit according to an embodiment of the present invention;
fig. 4 is a specific structure of the first compensation unit and the second compensation unit according to an embodiment of the present invention;
fig. 5 is a circuit diagram of a buffer amplifier circuit according to another embodiment of the present invention;
fig. 6 is a circuit diagram of a buffer amplifier circuit with a load according to a preferred embodiment of the present invention;
FIGS. 7-9 are graphs illustrating phase noise comparisons of the amplifier circuit and the buffer amplifier output signal according to another embodiment of the present invention;
fig. 10 is a comparison graph of the current passing through the amplifying circuit and the buffer amplifier in the same period according to another embodiment of the present invention.
Detailed Description
As described in the background, the buffer amplifier adopted in the prior art has too much phase noise of the output signal, and thus it is difficult to meet the requirements of high-performance communication systems and on-chip integrated systems.
In view of this, an embodiment of the present invention provides a buffer amplifier circuit, including: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; wherein,
the bias amplifying unit comprises a bias resistor, a first transistor and a second transistor; the gates of the first transistor and the second transistor are connected with one end of the bias resistor to serve as a signal input end of the amplifying circuit, the drains of the first transistor and the second transistor are connected with the other end of the bias resistor to serve as a signal output end of the bias amplifying unit, the source of the first transistor is connected with the first compensation unit, the source of the second transistor is connected with the second compensation unit, an input signal is transmitted to the gates of the first transistor and the second transistor through the signal input end of the amplifying circuit, and the input signal is amplified by the first transistor and the second transistor and then is output as a first signal through the signal output end of the bias amplifying unit;
one end of the first compensation unit is connected with the source electrode of the first transistor, and the other end of the first compensation unit is grounded and is used for providing negative feedback for the bias amplification unit and improving the signal bandwidth of the bias amplification unit;
one end of the second compensation unit is connected with the source electrode of the second transistor, and the other end of the second compensation unit is connected with a power supply and used for providing negative feedback for the bias amplification unit and improving the signal bandwidth of the bias amplification unit.
An embodiment of the present invention provides a buffer amplifier circuit, including: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; the first compensation unit and the second compensation unit provide negative feedback for the bias amplification unit, so that the signal bandwidth of the bias amplification unit is widened, the rising edge and the falling edge of the output signal of the amplification circuit become steep, the modulation of the output signal of the amplification circuit by the 1/f noise of the transistor is reduced, and the improved phase noise performance of the output signal is obtained.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a buffer amplifier circuit, as shown in fig. 2, including: a bias amplification unit 100, a first compensation unit 200, and a second compensation unit 300; wherein,
the bias amplifying unit 100 comprises a bias resistor R3, a first transistor A1 and a second transistor A2; gates of the first transistor a1 and the second transistor a2 are connected to one end of the bias resistor R3, and serve as a signal input terminal Vin1 of the amplifier circuit, drains of the first transistor a1 and the second transistor a2 are connected to the other end of the bias resistor R3, and serve as a signal output terminal O of the bias amplifier unit 100, a source of the first transistor a1 is connected to the first compensation unit 200, a source of the second transistor a2 is connected to the second compensation unit 300, an input signal is transmitted to gates of the first transistor a1 and the second transistor a2 through the signal input terminal, and is amplified by the first transistor a1 and the second transistor a2 and then output as a first signal through the signal output terminal O of the bias amplifier unit 100;
the first compensation unit 200 has one end connected to the source of the first transistor a1 and the other end connected to ground, and is configured to provide negative feedback to the bias amplification unit 100, so as to increase the signal bandwidth of the bias amplification unit 100;
the second compensation unit 300 has one end connected to the source of the second transistor a2 and the other end connected to a power supply, and is configured to provide negative feedback to the bias amplification unit 100, so as to improve the signal bandwidth of the bias amplification unit 100.
Note that the substrate of the first transistor is grounded, and the substrate of the second transistor is connected to a power supply, and for convenience of illustration, the substrates of the first transistor and the second transistor are not shown in the drawings.
In this embodiment, the purpose of simultaneously setting the first compensation unit 200 and the second compensation unit 300 is to ensure that the signal amplitudes of the positive and negative half shafts of the output signal of the bias amplification unit 100 are consistent.
It should be further noted that, the first compensation unit 200 and the second compensation unit 300 provide negative feedback to the offset amplification unit 100, so as to reduce the signal gain of the offset amplification unit 100; this is because the gain-bandwidth product of an amplifier circuit is generally constant, and the signal bandwidth of the amplifier circuit can be increased by negative feedback, but the gain is decreased accordingly. Negative feedback of the amplifier circuit as shown in FIG. 3The gain bandwidth variation diagram is shown, the horizontal axis is the frequency axis omega, and the vertical axis is the gain AV. As can be seen from FIG. 3, the initial gain of an amplifier circuit is A0Signal bandwidth of omega0the gain bandwidth product is GBW, when negative feedback is introduced, the feedback factor is beta, then the gain of the amplifying circuit is reduced to A0/(1+βA0) the signal bandwidth is (1+ β A)0)ω0But the gain-bandwidth product is still GBW. In the present invention, the first compensation unit 200 and the second compensation unit 300 broaden the signal bandwidth of the amplification circuit by providing negative feedback, so that the rising edge and the falling edge of the output signal of the amplification circuit become steep, and the modulation of the output signal of the amplification circuit by the transistor 1/f noise is reduced, thereby obtaining improved phase noise performance of the output signal.
On the basis of the above embodiments, a preferred embodiment of the present invention provides a specific implementation form of the first compensation unit 200 and the second compensation unit 300, as shown in fig. 4, the first compensation unit 200 includes a first resistor R1 and a first capacitor C1, the first resistor R1 is connected in parallel with the first capacitor C1, one end of the first resistor R1 is connected to the source of the first transistor a1, and the other end is grounded; the second compensation unit 300 includes a second resistor R2 and a second capacitor C2, the second resistor R2 is connected in parallel with the second capacitor C2, one end of the second resistor R2 is connected to the source of the second transistor a2, and the other end is connected to a power supply.
In addition, the implementation form and whether the resistance is controllably changed of the first resistor R1 and the second resistor R2 are not limited in the present invention, as long as the function of the resistors can be realized, which is determined by the actual situation. The implementation form of the first capacitor C1 and the second capacitor C2 and whether the capacitors are controllably changed are not limited in the present invention, as long as the functions of the capacitors can be implemented, which is determined by the actual situation.
It should be further noted that, in other embodiments of the present invention, the first compensation unit 200 may only include the first resistor R1, and the second compensation unit 300 may only include the second resistor R2, and the present invention does not limit the specific implementation forms of the first compensation unit 200 and the second compensation unit 300, as long as the present invention can provide negative feedback for the offset amplification unit 100 on the premise of satisfying a certain gain, so as to improve the signal bandwidth of the offset amplification unit, which is determined by actual circumstances.
On the basis of the above embodiments, in an embodiment of the present invention, the first transistor a1 is an N-channel enhancement mode fet, and the second transistor a2 is a P-channel enhancement mode fet. The specific types of the first transistor a1 and the second transistor a2 are not limited in the present invention, and are determined according to the actual situation.
On the basis of the above embodiments, in a specific embodiment of the present invention, the offset amplifying unit 100 further includes a compensation amplifying unit, as shown in fig. 5, the compensation amplifying unit 400 includes: a third transistor a11 and a fourth transistor a22, wherein,
the gates of the third transistor a11 and the fourth transistor a22 are connected to the signal input terminal Vin1 of the amplifier circuit, the drains of the third transistor a11 and the fourth transistor a22 are connected to the signal output terminal O of the bias amplifier unit 100, the third transistor a11 is an N-channel enhancement type field effect transistor, the source and the substrate of the third transistor are grounded, the fourth transistor a22 is a P-channel enhancement type field effect transistor, and the source and the substrate of the fourth transistor a22 are connected to a power supply;
the input signal is transmitted to the gates of the third transistor a11 and the fourth transistor a22 through the signal input terminal, and is amplified by the third transistor a11 and the fourth transistor a22 to be used as a second signal, and the second signal is superposed with the first signal to form a second composite signal which is output by the signal output terminal O of the bias amplifying unit 100, so that the signal gain of the amplifying circuit is improved.
The bias resistor R3 biases the first transistor a1 and the second transistor a2 in an amplified state, and also biases the third transistor a11 and the fourth transistor a22 in an amplified state.
It should be noted that, since the first compensation unit 200 and the second compensation unit 300 provide negative feedback to the offset amplification unit 100, the signal gain of the offset amplification unit 100 is reduced, and in order to prevent the amplitude of the first signal output by the offset amplification unit 100 from being too small, the compensation amplification circuit 400 is introduced to increase the amplitude of the output signal on the basis of ensuring the amplitude of the first signal output by the offset amplification unit 100.
On the basis of the foregoing embodiment, in a further specific embodiment of the present invention, the amplifying circuit further includes a first inverting amplifying unit, a signal input end of the first inverting amplifying unit is connected to the signal output end O of the bias amplifying unit 100, and is configured to perform inverting amplification on the output signal of the bias amplifying unit 100 and output a third signal through the signal output end of the first inverting amplifying unit.
It should be noted that, when the output signal of the offset amplification unit 100 does not include the second signal, the first inverting amplification unit is configured to perform inverting amplification on the first signal, and output a third signal through the signal output end of the first inverting amplification unit; when the output signal of the offset amplifying unit 100 includes the second signal, the first inverting amplifying unit is configured to perform inverting amplification on the second synthesized signal, and output a third signal through the signal output terminal of the first inverting amplifying unit.
On the basis of the foregoing embodiment, in a further specific embodiment of the present invention, the amplifying circuit further includes a second inverting amplifying unit, and a signal input end of the second inverting amplifying unit is connected to the signal output end of the first inverting amplifying unit, and is configured to perform inverting amplification on the third signal and output a fourth signal through a signal output end of the second inverting amplifying unit.
On the basis of the above embodiments, another specific embodiment of the present invention provides a specific implementation form of the first inverting amplifying unit and the second inverting amplifying unit, as shown in fig. 6, the first inverting amplifying unit 500 includes a fifth transistor A3 and a sixth transistor a 4; wherein,
the gates of the fifth transistor A3 and the sixth transistor a4 are connected to the signal output terminal O of the bias amplifying unit 100, which is used as the signal input terminal of the first inverting amplifying unit 500, the drains of the fifth transistor A3 and the sixth transistor a4 are connected to serve as the signal output terminal of the first inverting amplifying unit 500, the fifth transistor A3 is an N-channel enhancement type field effect transistor, the source electrode and the substrate of the sixth transistor A4 are grounded, the sixth transistor A4 is a P-channel enhancement mode field effect transistor, the source electrode and the substrate are connected with a direct current power supply, the output signal of the bias amplifying unit 100 is transmitted to the gates of the fifth transistor A3 and the sixth transistor a4 through the signal input terminal of the first inverting amplifying unit 500, and a third signal is output from the signal output terminal of the first inverting amplifying unit 500 after being inverted and amplified by the fifth transistor A3 and the sixth transistor a 4.
Similarly, the output signal of the offset amplification unit 100 is the first signal or the second composite signal.
The second inverting amplification unit 600 includes: a seventh transistor a5 and an eighth transistor a 6; wherein,
the gates of the seventh transistor A5 and the eighth transistor A6 are connected to the signal output terminal of the first inverting amplifying unit 500 as the signal input terminal of the second inverting amplifying unit 600, the drains of the seventh transistor a5 and the eighth transistor a6 are connected to serve as the signal output terminal Vout of the second inverting amplifier unit 600, the seventh transistor a5 is an N-channel enhancement mode fet, the source electrode and the substrate of the eighth transistor A6 are grounded, the eighth transistor A6 is a P-channel enhancement mode field effect transistor, the source electrode and the substrate are connected with a direct current power supply, the third signal is transmitted to the gates of the seventh transistor a5 and the eighth transistor a6 through the signal input terminal of the second inverting amplification unit 600, and after being inverted-amplified by the seventh transistor a5 and the eighth transistor a6, the fourth signal is output from the signal output terminal Vout of the second inverting amplifying unit 600.
Wherein Cd represents a blocking capacitor, and CL is a load carried by the amplifying circuit.
When the output signal of the bias amplifying unit 100 is at a low level, the sixth transistor a4 is turned on, the first inverting amplifying unit 500 outputs a high level to the second inverting amplifying unit 600, and at this time, the seventh transistor a5 is turned on, and the second inverting amplifying unit 600 outputs a low level. When the output signal of the bias amplifying unit 100 is at a high level, the fifth transistor A3 is turned on, the first inverting amplifying unit 500 outputs a low level to the second inverting amplifying unit 600, and at this time, the eighth transistor a6 is turned on, and the second inverting amplifying unit 600 outputs a high level, so that the signal inversion is realized.
It should be further noted that the main function of the first inverting amplification unit 500 and the second inverting amplification unit 600 in this embodiment is to increase the load capacity of the amplification circuit. When the P-channel enhancement type fet of the first inverting amplifier unit 500 or the second inverting amplifier unit 600 is turned on, the power supply charges to the subsequent load through the turned-on P-channel enhancement type fet, and obviously, the larger the size of the P-channel enhancement type fet is, the faster the P-channel enhancement type fet charges to the subsequent load, and the stronger the load carrying capacity is. Similarly, the size of the N-channel enhancement mode fet determines the speed of placing the charge on the load to ground, and the larger the size, the faster the charge on the load is placed to ground. Generally, the larger the size of the transistor constituting the first inverting amplifier unit 500 or the second inverting amplifier unit 600 is, the stronger the load carrying capacity of the amplifier circuit is, but the larger the size of the transistor constituting the first inverting amplifier unit 500 or the second inverting amplifier unit 600 is, the larger the load of the previous stage circuit is, so that it is necessary to adopt a multi-stage inverting amplifier unit to enlarge the load carrying capacity of the amplifier circuit step by step.
On the basis of any one of the above embodiments, in a particularly preferred embodiment of the present invention, the amplifying circuit further includes: a blocking capacitor;
one end of the blocking capacitor is used as a signal input end Vin1 of the amplifying circuit, and the other end of the blocking capacitor is connected to a connection node between the gates of the first transistor A1 and the second transistor A2 and the bias resistor R3, and is used for blocking the influence of the direct current level of the input signal on the amplifying circuit.
The embodiment of the invention takes the buffer amplifier circuit provided by the embodiment of the invention as an example, and compares the noise performance of the buffer amplifier adopted by the prior art.
Comparative experiment 1: a sinusoidal signal with a frequency of 40MHz and an amplitude of 100mV is input through the input terminal Vin of the buffer amplifier in the background art and the input terminal Vin1 of the amplifying circuit in the embodiment of the present invention, the dc power supplies used by the buffer amplifier and the amplifying circuit are the same, the parameters of the first transistor M1 of the buffer amplifier are the same as those of the first transistor a1 of the amplifying circuit, the parameters of the second transistor M2 of the buffer amplifier are the same as those of the second transistor a2 of the amplifying circuit, and the parameters of the load capacitors of the buffer amplifier and the amplifying circuit are the same. A pair of phase noise performances of the buffer amplifier and the amplifying circuit obtained by the experiment is shown in fig. 7. The curve 11 in fig. 7 is the phase noise curve of the output signal of the buffer amplifier and the curve 12 is the phase noise curve of the output signal of the amplifying circuit, which can be derived from fig. 7, the phase noise performance of the amplifying circuit is significantly better than the noise performance of the buffer amplifier: at a frequency offset Δ f (═ 1Hz), the noise output by the amplification circuit is about 0.97dB lower than the noise output by the buffer amplifier; at a frequency offset Δ f (═ 100Hz), the phase noise output by the amplification circuit is about 1.50dB lower than the phase noise output by the buffer amplifier; at a frequency offset Δ f (═ 10MHz), the phase noise output by the amplification circuit is about 2.80dB lower than the phase noise output by the buffer amplifier. As can be seen from fig. 7, at a frequency offset Δ f (═ 100Hz), the phase noise values of the buffer amplifier and the amplifying circuit are both lower than-145 dBc/Hz, and with such low phase noise, the phase noise of the amplifying circuit is optimized by 1.50dB again; at a frequency offset Δ f (═ 10MHz), the phase noise values of the buffer amplifier and the amplification circuit are both below-150 dBc/Hz, and with such low phase noise, the phase noise of the amplification circuit is optimized again by 2.80 dB.
Comparative experiment 2: a sinusoidal signal with a frequency of 40MHz and an amplitude of 300mV is input through the input terminal Vin of the buffer amplifier in the background art and the input terminal Vin1 of the amplifying circuit in the embodiment of the present invention, the dc power supplies used by the buffer amplifier and the amplifying circuit are the same, the parameters of the first transistor M1 of the buffer amplifier are the same as those of the first transistor a1 of the amplifying circuit, the parameters of the second transistor M2 of the buffer amplifier are the same as those of the second transistor a2 of the amplifying circuit, and the parameters of the load capacitors of the buffer amplifier and the amplifying circuit are the same. A pair of phase noise performances of the buffer amplifier and the amplifying circuit obtained by the experiment is shown in fig. 8. Curve 13 in fig. 8 is the phase noise curve of the output signal of the buffer amplifier and curve 14 is the phase noise curve of the output signal of the amplifying circuit, which can be derived from fig. 8, the phase noise performance of the amplifying circuit is significantly better than the noise performance of the buffer amplifier. At a frequency offset Δ f (═ 1Hz), the phase noise output by the amplification circuit is about 1.95dB lower than the phase noise output by the buffer amplifier; at a frequency offset Δ f (═ 100Hz), the phase noise output by the amplification circuit is about 2.03dB lower than the phase noise output by the buffer amplifier; at a frequency offset Δ f (═ 10MHz), the phase noise output by the amplification circuit is about 3.40dB lower than the phase noise output by the buffer amplifier. As can be seen from fig. 8, at a frequency offset Δ f (═ 100Hz), the phase noise values of the buffer amplifier and the amplifying circuit are both lower than-145 dBc/Hz, and with such low phase noise, the phase noise of the amplifying circuit is optimized by 2.03dB again; at a frequency offset Δ f (═ 10MHz), the phase noise values of the buffer amplifier and the amplification circuit are both below-155 dBc/Hz, and with such low phase noise, the phase noise of the amplification circuit is optimized by 3.40dB again.
Comparative experiment 3: a sinusoidal signal with a frequency of 40MHz and an amplitude of 500mV is input through the input terminal Vin of the buffer amplifier in the background art and the input terminal Vin1 of the amplifying circuit in the embodiment of the present invention, the dc power supplies used by the buffer amplifier and the amplifying circuit are the same, the parameters of the first transistor M1 of the buffer amplifier are the same as those of the first transistor a1 of the amplifying circuit, the parameters of the second transistor M2 of the buffer amplifier are the same as those of the second transistor a2 of the amplifying circuit, and the parameters of the load capacitors of the buffer amplifier and the amplifying circuit are the same. A pair of phase noise performances of the buffer amplifier and the amplifying circuit obtained by the experiment is shown in fig. 9. Curve 15 in fig. 9 is the phase noise curve of the output signal of the buffer amplifier and curve 16 is the phase noise curve of the output signal of the amplifying circuit, which can be derived from fig. 9, the phase noise performance of the amplifying circuit is significantly better than the noise performance of the buffer amplifier. At a frequency offset Δ f (═ 1Hz), the phase noise output by the amplification circuit is about 1.82dB lower than the phase noise output by the buffer amplifier; at a frequency offset Δ f (═ 100Hz), the phase noise output by the amplification circuit is about 1.87dB lower than the phase noise output by the buffer amplifier; at a frequency offset Δ f (═ 10MHz), the phase noise output by the amplification circuit is about 3.62dB lower than the phase noise output by the buffer amplifier. As can be seen from fig. 9, at a frequency offset Δ f (═ 100Hz), the phase noise values of the buffer amplifier and the amplifying circuit are both lower than-145 dBc/Hz, and at such low phase noise, the phase noise of the amplifying circuit is optimized by 1.87dB again compared to the phase noise of the buffer amplifier; at a frequency offset Δ f (═ 10MHz), the phase noise values of the buffer amplifier and the amplification circuit are both below-160 dBc/Hz, and with such low phase noise, the phase noise of the amplification circuit is optimized by a further 3.62dB compared to the phase noise of the buffer amplifier.
Through the three comparative experiments, the amplifying circuit provided by the embodiment of the invention has better phase noise performance.
The embodiment of the invention also compares the power consumption parameters of the amplifying circuit and the buffer amplifier:
a sinusoidal signal with a frequency of 40MHz and an amplitude of 500mV is input through the input terminal Vin of the buffer amplifier in the background art and the input terminal Vin1 of the amplifying circuit in the embodiment of the present invention, the dc power supplies used by the buffer amplifier and the amplifying circuit are the same, the parameters of the first transistor M1 of the buffer amplifier are the same as those of the first transistor a1 of the amplifying circuit, the parameters of the second transistor M2 of the buffer amplifier are the same as those of the second transistor a2 of the amplifying circuit, and the parameters of the load capacitors of the buffer amplifier and the amplifying circuit are the same. The current curves consumed by the buffer amplifier and the amplifying circuit in the same cycle obtained through the experiment are shown in fig. 10. As can be seen from fig. 10, the current consumed by the amplifying circuit is significantly lower than the current consumed by the buffer amplifier, as shown in fig. 10, curve 17 is the current consumed by the buffer amplifier in the period, and curve 18 is the current consumed by the amplifying circuit in the period. The average value of the currents is calculated, so that the average current consumed by the buffer amplifier is 4.908mA, the average current consumed by the amplifying circuit is 4.116mA, the power consumption of the amplifying circuit provided by the embodiment of the invention is reduced by more than 16% compared with the power consumption of the buffer amplifier, and the experiment can show that the amplifying circuit provided by the embodiment of the invention not only has good phase noise performance, but also has low power consumption.
In summary, an embodiment of the present invention provides a buffer amplifier circuit, including: a bias amplification unit 100, a first compensation unit 200, and a second compensation unit 300; the first compensation unit 200 and the second compensation unit 300 provide negative feedback for the offset amplification unit 100, so that the signal bandwidth of the offset amplification unit 100 is widened, the rising edge and the falling edge of the output signal of the amplification circuit become steep, the modulation of the output signal of the amplification circuit by the transistor 1/f noise is reduced, and the improved phase noise performance of the output signal is obtained. Meanwhile, through experimental comparison, the amplifying circuit provided by the embodiment of the invention is low in power consumption.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A buffer amplifier circuit, comprising: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; wherein,
the bias amplifying unit comprises a bias resistor, a first transistor and a second transistor; the gates of the first transistor and the second transistor are connected with one end of the bias resistor to serve as a signal input end of the amplifying circuit, the drains of the first transistor and the second transistor are connected with the other end of the bias resistor to serve as a signal output end of the bias amplifying unit, the source of the first transistor is connected with the first compensation unit, the source of the second transistor is connected with the second compensation unit, an input signal is transmitted to the gates of the first transistor and the second transistor through the signal input end of the amplifying circuit, and the input signal is amplified by the first transistor and the second transistor and then is output as a first signal through the signal output end of the bias amplifying unit;
one end of the first compensation unit is connected with the source electrode of the first transistor, and the other end of the first compensation unit is grounded and is used for providing negative feedback for the bias amplification unit and improving the signal bandwidth of the bias amplification unit;
one end of the second compensation unit is connected with the source electrode of the second transistor, and the other end of the second compensation unit is connected with a power supply and used for providing negative feedback for the bias amplification unit and improving the signal bandwidth of the bias amplification unit;
the first compensation unit comprises a first resistor and a first capacitor, the first resistor is connected with the first capacitor in parallel, one end of the first resistor is connected with the source electrode of the first transistor, and the other end of the first resistor is grounded;
the second compensation unit comprises a second resistor and a second capacitor, the second resistor is connected with the second capacitor in parallel, one end of the second resistor is connected with the source electrode of the second transistor, and the other end of the second resistor is connected with a power supply.
2. The amplification circuit of claim 1, wherein the bias amplification unit further comprises a compensation amplification unit comprising: a third transistor and a fourth transistor; wherein,
the grid electrodes of the third transistor and the fourth transistor are connected with the signal input end of the amplifying circuit, the drain electrodes of the third transistor and the fourth transistor are connected with the signal output end of the bias amplifying unit, the third transistor is an N-channel enhanced field effect transistor, the source electrode and the substrate of the third transistor are grounded, the fourth transistor is a P-channel enhanced field effect transistor, and the source electrode and the substrate of the fourth transistor are connected with a power supply;
the input signal is transmitted to the grid electrodes of the third transistor and the fourth transistor through the signal input end of the amplifying circuit, the input signal is amplified through the third transistor and the fourth transistor to be used as a second signal, the second signal and the first signal are superposed to form a second composite signal, and the second composite signal is output by the signal output end of the bias amplifying unit, so that the signal gain of the amplifying circuit is improved.
3. The amplifier circuit according to any one of claims 1-2, wherein the amplifier circuit further comprises a first inverting amplifier unit, a signal input terminal of the first inverting amplifier unit is connected to the signal output terminal of the offset amplifier unit, and is configured to perform inverting amplification on the output signal of the offset amplifier unit and output a third signal through the signal output terminal of the first inverting amplifier unit.
4. The amplifying circuit according to claim 3, wherein the first inverting amplifying unit includes a fifth transistor and a sixth transistor; wherein,
the grid electrodes of the fifth transistor and the sixth transistor are connected with the signal output end of the bias amplification unit and used as the signal input end of the first inverting amplification unit, the drain electrodes of the fifth transistor and the sixth transistor are connected and used as the signal output end of the first inverting amplification unit, the fifth transistor is an N-channel enhanced field effect transistor, the source electrode and the substrate of the fifth transistor are grounded, the sixth transistor is a P-channel enhanced field effect transistor, the source electrode and the substrate of the sixth transistor are connected with a direct-current power supply, the output signal of the bias amplification unit is transmitted to the grid electrodes of the fifth transistor and the sixth transistor through the signal input end of the first inverting amplification unit, and a third signal is output through the signal output end of the first inverting amplification unit after the inverting amplification of the fifth transistor and the sixth transistor.
5. The amplifying circuit according to claim 3, further comprising a second inverting amplifying unit, wherein a signal input terminal of the second inverting amplifying unit is connected to the signal output terminal of the first inverting amplifying unit, and is configured to perform inverting amplification on the third signal and output a fourth signal through a signal output terminal of the second inverting amplifying unit.
6. The amplification circuit according to claim 5, wherein the second inverting amplification unit includes: a seventh transistor and an eighth transistor; wherein,
the gates of the seventh transistor and the eighth transistor are connected to the signal output end of the first inverting amplifying unit and used as the signal input end of the second inverting amplifying unit, the drains of the seventh transistor and the eighth transistor are connected and used as the signal output end of the second inverting amplifying unit, the seventh transistor is an N-channel enhanced field effect transistor, the source electrode and the substrate of the seventh transistor are grounded, the eighth transistor is a P-channel enhanced field effect transistor, the source electrode and the substrate of the eighth transistor are connected to a direct-current power supply, the third signal is transmitted to the gates of the seventh transistor and the eighth transistor through the signal input end of the second inverting amplifying unit, and a fourth signal is output from the signal output end of the second inverting amplifying unit after the third signal is amplified in an inverting manner by the seventh transistor and the eighth transistor.
7. The amplification circuit of any one of claims 1-2 or 4-6, further comprising: a blocking capacitor;
one end of the blocking capacitor is used as a signal input end of the amplifying circuit, and the other end of the blocking capacitor is connected to the connection nodes of the grid electrodes of the first transistor and the second transistor and the bias resistor and used for blocking the influence of the direct current level of the input signal on the amplifying circuit.
8. The amplifier circuit of claim 1, wherein the first transistor is an N-channel enhancement mode fet and the second transistor is a P-channel enhancement mode fet.
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