CN105375887A - Buffer amplifying circuit - Google Patents
Buffer amplifying circuit Download PDFInfo
- Publication number
- CN105375887A CN105375887A CN201510882013.0A CN201510882013A CN105375887A CN 105375887 A CN105375887 A CN 105375887A CN 201510882013 A CN201510882013 A CN 201510882013A CN 105375887 A CN105375887 A CN 105375887A
- Authority
- CN
- China
- Prior art keywords
- transistor
- signal
- amplifying unit
- phase
- amplifying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims abstract description 22
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 22
- 230000005669 field effect Effects 0.000 claims description 30
- 239000000758 substrate Substances 0.000 claims description 23
- 239000002131 composite material Substances 0.000 claims description 5
- 238000012935 Averaging Methods 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 abstract description 5
- 230000003139 buffering effect Effects 0.000 abstract 1
- 238000002474 experimental method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
The application discloses buffering amplifier circuit, amplifier circuit includes: the device comprises a bias amplification unit, a first compensation unit and a second compensation unit; the bias amplifying unit comprises a bias resistor, a first transistor and a second transistor; an input signal is transmitted to the grids of the first transistor and the second transistor through a signal input end of the amplifying circuit, and is amplified by the first transistor and the second transistor to be output as a first signal through a signal output end of the bias amplifying unit; the first compensation unit and the second compensation unit are used for providing negative feedback to the bias amplification unit, so that the signal bandwidth of the bias amplification unit is improved, the rising edge and the falling edge of the output signal of the amplification circuit are steep, the modulation of the output signal of the amplification circuit by the 1/f noise of the transistor is reduced, and the improved phase noise performance of the output signal is obtained.
Description
Technical field
The present invention relates to semiconductor applications, more particularly, relate to a kind of buffer amplifier circuit.
Background technology
Buffer amplifier is widely used in on-chip integration system and communication system.Fig. 1 is the circuit diagram of the buffer amplifier usually adopted in prior art, as shown in Figure 1, described buffer amplifier comprises biasing resistor R0, the first transistor M1 and transistor seconds M2, wherein, one end of described biasing resistor R0 is connected with the grid of described the first transistor M1, transistor seconds M2, as the signal input part Vin of described buffer amplifier, the other end is connected with the drain electrode of described the first transistor M1, transistor seconds M2, as signal output part G; Described the first transistor M1 is N channel enhancement field effect transistor, its substrate and source ground, and described transistor seconds M2 is P-channel enhancement type field effect transistor, and its substrate and source electrode are connected with DC power supply VDD; Described biasing resistor R0 is used for described the first transistor M1, transistor seconds M2 to be biased in saturation amplification district, thus makes to be amplified rear output by described the first transistor M1, transistor seconds M2 by the input signal of described signal input part Vin.
Because flicker noise (i.e. 1/f noise) produces because defects from semiconductor materials causes electric current random fluctuation, and the defect of semi-conducting material is inevitable at present, with regard to described buffer amplifier, while amplification input signal, the 1/f noise of transistor will be modulated in the output signal of amplification, show as the phase noise of output signal, excessive phase noise makes described buffer amplifier be difficult to meet the requirement of high performance communication system and on-chip integration system.
Therefore, the buffer amplifier that a kind of phase noise of output signal is less is needed badly.
Summary of the invention
Embodiments provide a kind of buffer amplifier circuit, described amplifying circuit has good phase noise performance.
A kind of buffer amplifier circuit, comprising: biased amplifying unit, the first compensating unit and the second compensating unit; Wherein,
Described biased amplifying unit comprises biasing resistor, the first transistor, transistor seconds, described the first transistor, the grid of transistor seconds is connected with one end of described biasing resistor, as the signal input part of described amplifying circuit, described the first transistor, the drain electrode of transistor seconds is connected with the other end of described biasing resistor, as the signal output part of described biased amplifying unit, the source electrode of described the first transistor is connected with described first compensating unit, the source electrode of described transistor seconds is connected with described second compensating unit, input signal is sent to the grid of described the first transistor and transistor seconds by the signal input part of described amplifying circuit, export as the signal output part of the first signal via described biased amplifying unit after being amplified by described the first transistor and transistor seconds,
Described first compensating unit one end is connected with the source electrode of described the first transistor, other end ground connection, for providing negative feedback to described biased amplifying unit, improves the signal bandwidth of described biased amplifying unit;
Described second compensating unit one end is connected with the source electrode of described transistor seconds, and the other end is connected with power supply, for providing negative feedback to described biased amplifying unit, improves the signal bandwidth of described biased amplifying unit.
Preferably, described first compensating unit comprises the first resistance and the first electric capacity, described first resistance and the first Capacitance parallel connection, and its one end is connected with the source electrode of described the first transistor, other end ground connection.
Preferably, described second compensating unit comprises the second resistance and the second electric capacity, and described second resistance and the second Capacitance parallel connection, its one end is connected with the source electrode of described transistor seconds, and the other end is connected with power supply.
Preferably, described biased amplifying unit also comprises compensation amplifying unit, and described compensation amplifying unit comprises: third transistor and the 4th transistor; Wherein,
The grid of described third transistor, the 4th transistor is connected to the signal input part of described amplifying circuit, the drain electrode of described third transistor, the 4th transistor is connected to the signal output part of described biased amplifying unit, described third transistor is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 4th transistor is P-channel enhancement type field effect transistor, and its source electrode and substrate are connected with power supply;
Input signal is sent to the grid of described third transistor and the 4th transistor by the signal input part of described amplifying circuit, as secondary signal after being amplified by described third transistor and the 4th transistor, described secondary signal and described first Signal averaging form the second composite signal and are exported by the signal output part of described biased amplifying unit, to improve the signal gain of described amplifying circuit.
Preferably, described amplifying circuit also comprises the first anti-phase amplifying unit, the signal input part of described first anti-phase amplifying unit is connected to the signal output part of described biased amplifying unit, for carrying out anti-phase amplification to the output signal of described biased amplifying unit, and export the 3rd signal by the signal output part of described first anti-phase amplifying unit.
Preferably, described first anti-phase amplifying unit comprises the 5th transistor and the 6th transistor; Wherein,
Described 5th transistor, the grid of the 6th transistor is connected to the signal output part of described biased amplifying unit, as the signal input part of described first anti-phase amplifying unit, described 5th transistor, the drain electrode of the 6th transistor connects, as the signal output part of described first anti-phase amplifying unit, described 5th transistor is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 6th transistor is P-channel enhancement type field effect transistor, its source electrode and substrate are connected to DC power supply, the output signal of described biased amplifying unit is sent to the grid of described 5th transistor and the 6th transistor by the signal input part of described first anti-phase amplifying unit, the 3rd signal is exported by the signal output part of described first anti-phase amplifying unit after the anti-phase amplification of described 5th transistor and the 6th transistor.
Preferably, described amplifying circuit also comprises the second anti-phase amplifying unit, the signal input part of described second anti-phase amplifying unit is connected to the signal output part of described first anti-phase amplifying unit, for carrying out anti-phase amplification to described 3rd signal and exporting the 4th signal by the signal output part of described second anti-phase amplifying unit.
Preferably, described second anti-phase amplifying unit comprises: the 7th transistor and the 8th transistor; Wherein,
Described 7th transistor, the grid of the 8th transistor is connected to the signal output part of described first anti-phase amplifying unit, as the signal input part of described second anti-phase amplifying unit, described 7th transistor, the drain electrode of the 8th transistor connects, as the signal output part of described second anti-phase amplifying unit, described 7th transistor is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 8th transistor is P-channel enhancement type field effect transistor, its source electrode and substrate are connected to DC power supply, described 3rd signal is sent to the grid of described 7th transistor and the 8th transistor by the signal input part of described second anti-phase amplifying unit, the 4th signal is exported by the signal output part of described second anti-phase amplifying unit after the anti-phase amplification of described 7th transistor and the 8th transistor.
Preferably, described amplifying circuit also comprises: capacitance;
One end of described capacitance is as the signal input part of described amplifying circuit, the other end is connected to described the first transistor, the grid of transistor seconds and the connected node of described biasing resistor, for the DC level of blocked input signal on the impact of described amplifying circuit.
Preferably, described the first transistor is N channel enhancement field effect transistor, and described transistor seconds is P-channel enhancement type field effect transistor.
Compared with prior art, technique scheme has the following advantages:
Embodiments provide a kind of buffer amplifier circuit, comprising: biased amplifying unit, the first compensating unit and the second compensating unit; Wherein, described first compensating unit and the second compensating unit are by providing negative feedback for described biased amplifying unit, widen the signal bandwidth of described biased amplifying unit, make rising edge and the trailing edge steepening of the output signal of described amplifying circuit, reduce the modulation of transistor 1/f noise to the output signal of described amplifying circuit, thus obtain the phase of output signal noiseproof feature of improvement.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
Fig. 1 is the circuit diagram of the buffer amplifier adopted in prior art;
The circuit diagram of a kind of buffer amplifier circuit that Fig. 2 provides for one embodiment of the present of invention;
The amplifying circuit negative feedback gain bandwidth change schematic diagram that Fig. 3 provides for one embodiment of the present of invention;
The concrete structure of a kind of described first compensating unit that Fig. 4 provides for a specific embodiment of the present invention and the second compensating unit;
The circuit diagram of a kind of buffer amplifier circuit that Fig. 5 provides for another specific embodiment of the present invention;
The circuit diagram of a kind of load-carrying buffer amplifier circuit that Fig. 6 provides for a concrete preferred embodiment of the present invention;
The described amplifying circuit that Fig. 7-9 provides for an alternative embodiment of the invention and the phase noise vs that described buffer amplifier outputs signal scheme;
In the described amplifying circuit that Figure 10 provides for another embodiment of the present invention and described buffer amplifier same period by the comparison diagram of electric current.
Embodiment
As described in background, prior art adopt buffer amplifier due to output signal phase noise excessive, be difficult to the requirement meeting high performance communication system and on-chip integration system.
In view of this, embodiments provide a kind of buffer amplifier circuit, comprising: biased amplifying unit, the first compensating unit and the second compensating unit; Wherein,
Described biased amplifying unit comprises biasing resistor, the first transistor, transistor seconds, described the first transistor, the grid of transistor seconds is connected with one end of described biasing resistor, as the signal input part of described amplifying circuit, described the first transistor, the drain electrode of transistor seconds is connected with the other end of described biasing resistor, as the signal output part of described biased amplifying unit, the source electrode of described the first transistor is connected with described first compensating unit, the source electrode of described transistor seconds is connected with described second compensating unit, input signal is sent to the grid of described the first transistor and transistor seconds by the signal input part of described amplifying circuit, export as the signal output part of the first signal via described biased amplifying unit after being amplified by described the first transistor and transistor seconds,
Described first compensating unit one end is connected with the source electrode of described the first transistor, other end ground connection, for providing negative feedback to described biased amplifying unit, improves the signal bandwidth of described biased amplifying unit;
Described second compensating unit one end is connected with the source electrode of described transistor seconds, and the other end is connected with power supply, for providing negative feedback to described biased amplifying unit, improves the signal bandwidth of described biased amplifying unit.
Embodiments provide a kind of buffer amplifier circuit, comprising: biased amplifying unit, the first compensating unit and the second compensating unit; Wherein, described first compensating unit and the second compensating unit are by providing negative feedback for described biased amplifying unit, widen the signal bandwidth of described biased amplifying unit, make rising edge and the trailing edge steepening of the output signal of described amplifying circuit, reduce the modulation of transistor 1/f noise to the output signal of described amplifying circuit, thus obtain the phase of output signal noiseproof feature of improvement.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments provide a kind of buffer amplifier circuit, as shown in Figure 2, comprising: biased amplifying unit 100, first compensating unit 200 and the second compensating unit 300; Wherein,
Described biased amplifying unit 100 comprises biasing resistor R3, the first transistor A1, transistor seconds A2, described the first transistor A1, the grid of transistor seconds A2 is connected with one end of described biasing resistor R3, as the signal input part Vin1 of described amplifying circuit, described the first transistor A1, the drain electrode of transistor seconds A2 is connected with the other end of described biasing resistor R3, as the signal output part O of described biased amplifying unit 100, the source electrode of described the first transistor A1 is connected with described first compensating unit 200, the source electrode of described transistor seconds A2 is connected with described second compensating unit 300, input signal is sent to the grid of described the first transistor A1 and transistor seconds A2 by described signal input part, export as the signal output part O of the first signal via described biased amplifying unit 100 after being amplified by described the first transistor A1 and transistor seconds A2,
Described first compensating unit 200 one end is connected with the source electrode of described the first transistor A1, and other end ground connection, for providing negative feedback to described biased amplifying unit 100, improves the signal bandwidth of described biased amplifying unit 100;
Described second compensating unit 300 one end is connected with the source electrode of described transistor seconds A2, and the other end is connected with power supply, for providing negative feedback to described biased amplifying unit 100, improves the signal bandwidth of described biased amplifying unit 100.
It should be noted that, the Substrate ground of described the first transistor, the substrate of described transistor seconds is connected with power supply, and in order to represent convenient, the substrate of described the first transistor and transistor seconds is not shown in the drawing.
In the present embodiment, arrange described first compensating unit 200 to be to ensure that the signal amplitude that described biased amplifying unit 100 outputs signal positive and negative semiaxis is consistent with the object of the second compensating unit 300 simultaneously.
Also it should be noted that, described first compensating unit 200 and the second compensating unit 300 provide negative feedback to described biased amplifying unit 100, reduce the signal gain of described biased amplifying unit 100; This is because generally, the gain bandwidth product of an amplifying circuit is certain, can be improved the signal bandwidth of amplifying circuit, but gain then decreases by negative feedback.Be illustrated in figure 3 amplifying circuit negative feedback gain bandwidth change schematic diagram, transverse axis is frequency axis ω, and the longitudinal axis is gain A
v.As can be seen from Figure 3, the initial gain of an amplifying circuit is A
0, signal bandwidth is ω
0, gain bandwidth product is GBW; When introducing negative feedback, feedback factor is β, and so the gain reduction of amplifying circuit is A
0/ (1+ β A
0), signal bandwidth is (1+ β A
0) ω
0, but gain bandwidth product is still GBW.In the present invention, described first compensating unit 200 and the second compensating unit 300 are by the signal bandwidth of the described amplifying circuit that provides negative feedback to widen, make rising edge and the trailing edge steepening of the output signal of described amplifying circuit, reduce the modulation of transistor 1/f noise to the output signal of described amplifying circuit, thus obtain the phase of output signal noiseproof feature of improvement.
On the basis of above-described embodiment, a preferred embodiment of the present invention provides the specific implementation form of a kind of described first compensating unit 200 and the second compensating unit 300, as shown in Figure 4, described first compensating unit 200 comprises the first resistance R1 and the first electric capacity C1, described first resistance R1 is in parallel with the first electric capacity C1, its one end is connected with the source electrode of described the first transistor A1, other end ground connection; Described second compensating unit 300 comprises the second resistance R2 and the second electric capacity C2, and described second resistance R2 is in parallel with the second electric capacity C2, and its one end is connected with the source electrode of described transistor seconds A2, and the other end is connected with power supply.
It should be noted that, to the way of realization of described first resistance R1 and the second resistance R2 and resistance, whether controllable variations does not limit, as long as can realize the function of resistance, specifically depending on actual conditions in the present invention.To the way of realization of described first electric capacity C1 and the second electric capacity C2 and electric capacity, whether controllable variations does not limit, as long as can realize the function of electric capacity, specifically depending on actual conditions in the present invention.
Also it should be noted that, in other embodiments of the invention, described first compensating unit 200 only can comprise the first resistance R1, described second compensating unit 300 only can comprise the second resistance R2, the specific implementation form of the present invention to described first compensating unit 200 and the second compensating unit 300 does not limit, as long as can for described biased amplifying unit 100 provides negative feedback under the prerequisite meeting certain gain, improve the signal bandwidth of described biased amplifying unit, specifically depending on actual conditions.
On the basis of above-described embodiment, in one embodiment of the invention, described the first transistor A1 is N channel enhancement field effect transistor, and described transistor seconds A2 is P-channel enhancement type field effect transistor.The particular type of the present invention to described the first transistor A1 and transistor seconds A2 does not limit, specifically depending on actual conditions.
On the basis of above-described embodiment, in one particular embodiment of the present invention, described biased amplifying unit 100 also comprises compensation amplifying unit, and as shown in Figure 5, described compensation amplifying unit 400 comprises: third transistor A11 and the 4th transistor A22, wherein,
The grid of described third transistor A11, the 4th transistor A22 is connected to the signal input part Vin1 of described amplifying circuit, the drain electrode of described third transistor A11, the 4th transistor A22 is connected to the signal output part O of described biased amplifying unit 100, described third transistor A11 is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 4th transistor A22 is P-channel enhancement type field effect transistor, and its source electrode and substrate are connected with power supply;
Input signal is sent to the grid of described third transistor A11 and the 4th transistor A22 by described signal input part, as secondary signal after being amplified by described third transistor A11 and the 4th transistor A22, described secondary signal and described first Signal averaging form the second composite signal and are exported, to improve the signal gain of described amplifying circuit by the signal output part O of described biased amplifying unit 100.
It should be noted that, described third transistor A11 and the 4th transistor A22, while described the first transistor A1 and transistor seconds A2 is biased in magnifying state, is also biased in magnifying state by described biasing resistor R3.
Also it should be noted that, because the first compensating unit 200 and the second compensating unit 300 provide negative feedback to described biased amplifying unit 100, reduce the signal gain of described biased amplifying unit 100, the amplitude of described first signal exported to prevent described biased amplifying unit 100 is too small, therefore introduce and compensate amplifying circuit 400, the basis ensureing described first signal that described biased amplifying unit 100 exports is improved the amplitude of output signal.
On the basis of above-described embodiment, in another specific embodiment of the present invention, described amplifying circuit also comprises the first anti-phase amplifying unit, the signal input part of described first anti-phase amplifying unit is connected to the signal output part O of described biased amplifying unit 100, for carrying out anti-phase amplification to the output signal of described biased amplifying unit 100, and export the 3rd signal by the signal output part of described first anti-phase amplifying unit.
It should be noted that, when the output signal of described biased amplifying unit 100 does not comprise described secondary signal, described first anti-phase amplifying unit is used for carrying out anti-phase amplification to described first signal, and exports the 3rd signal by the signal output part of described first anti-phase amplifying unit; When the output signal of described biased amplifying unit 100 comprises described secondary signal, described first anti-phase amplifying unit is used for carrying out anti-phase amplification to described second composite signal, and exports the 3rd signal by the signal output part of described first anti-phase amplifying unit.
On the basis of above-described embodiment, in another specific embodiment of the present invention, described amplifying circuit also comprises the second anti-phase amplifying unit, the signal input part of described second anti-phase amplifying unit is connected to the signal output part of described first anti-phase amplifying unit, for carrying out anti-phase amplification to described 3rd signal and exporting the 4th signal by the signal output part of described second anti-phase amplifying unit.
On the basis of above-described embodiment, another specific embodiment of the present invention provides the specific implementation form of a kind of described first anti-phase amplifying unit and the second anti-phase amplifying unit, as shown in Figure 6, described first anti-phase amplifying unit 500 comprises the 5th transistor A3 and the 6th transistor A4; Wherein,
Described 5th transistor A3, the grid of the 6th transistor A4 is connected to the signal output part O of described biased amplifying unit 100, as the signal input part of described first anti-phase amplifying unit 500, described 5th transistor A3, the drain electrode of the 6th transistor A4 connects, as the signal output part of described first anti-phase amplifying unit 500, described 5th transistor A3 is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 6th transistor A4 is P-channel enhancement type field effect transistor, its source electrode and substrate are connected to DC power supply, the output signal of described biased amplifying unit 100 is sent to the grid of described 5th transistor A3 and the 6th transistor A4 by the signal input part of described first anti-phase amplifying unit 500, the 3rd signal is exported by the signal output part of described first anti-phase amplifying unit 500 after the anti-phase amplification of described 5th transistor A3 and the 6th transistor A4.
Same, the output signal of described biased amplifying unit 100 is the first signal or the second composite signal.
Described second anti-phase amplifying unit 600 comprises: the 7th transistor A5 and the 8th transistor A6; Wherein,
Described 7th transistor A5, the grid of the 8th transistor A6 is connected to the signal output part of described first anti-phase amplifying unit 500, as the signal input part of described second anti-phase amplifying unit 600, described 7th transistor A5, the drain electrode of the 8th transistor A6 connects, as the signal output part Vout of described second anti-phase amplifying unit 600, described 7th transistor A5 is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 8th transistor A6 is P-channel enhancement type field effect transistor, its source electrode and substrate are connected to DC power supply, described 3rd signal is sent to the grid of described 7th transistor A5 and the 8th transistor A6 by the signal input part of described second anti-phase amplifying unit 600, after the anti-phase amplification of described 7th transistor A5 and the 8th transistor A6, the 4th signal is exported by the signal output part Vout of described second anti-phase amplifying unit 600.
Wherein Cd represents capacitance, described CL for described amplifying circuit with load.
It should be noted that, when the output signal of described biased amplifying unit 100 is low level, described 6th transistor A4 conducting, described first anti-phase amplifying unit 500 exports high level to described second anti-phase amplifying unit 600, now, described 7th transistor A5 conducting, described second anti-phase amplifying unit 600 output low level.When the output signal of described biased amplifying unit 100 is high level, described 5th transistor A3 conducting, described first anti-phase amplifying unit 500 is to described second anti-phase amplifying unit 600 output low level, now described 8th transistor A6 conducting, described second anti-phase amplifying unit 600 exports high level, realizes the anti-phase of signal.
Also it should be noted that, described first anti-phase amplifying unit 500 and the main in the present embodiment function of the second anti-phase amplifying unit 600 are the carrying load abilities promoting described amplifying circuit.When the P-channel enhancement type field effect transistor conducting of the anti-phase amplifying unit 600 of described first anti-phase amplifying unit 500 or the second, power supply is charged to successive load by the P-channel enhancement type field effect transistor opened, the size of obvious P-channel enhancement type field effect transistor is larger, its speed to successive load charging is faster, and carrying load ability is stronger.In like manner, the size of N channel enhancement field effect transistor determines the speed electric charge in load being put into ground, and size is larger, and the speed electric charge in load being put into ground is faster.In general, the size forming the transistor of the anti-phase amplifying unit of described first anti-phase amplifying unit 500 or the second 600 is larger, the carrying load ability of described amplifying circuit is stronger, but the size forming the transistor of the anti-phase amplifying unit of described first anti-phase amplifying unit 500 or the second 600 is larger, the load of front stage circuits is larger, therefore need to adopt multistage anti-phase amplifying unit, expand the carrying load ability of described amplifying circuit step by step, have employed the anti-phase amplifying unit of two-stage in the present embodiment, for expanding the carrying load ability of described amplifying circuit, but the progression of the present invention to described anti-phase amplifying unit does not limit, specifically depending on actual conditions, same, the concrete composition structure of the present invention to described anti-phase amplifying unit does not limit, specifically depending on actual conditions.
On the basis of above-mentioned any embodiment, in a concrete preferred embodiment of the present invention, described amplifying circuit also comprises: capacitance;
One end of described capacitance is as the signal input part Vin1 of described amplifying circuit, the other end is connected to described the first transistor A1, the grid of transistor seconds A2 and the connected node of described biasing resistor R3, for the DC level of blocked input signal on the impact of described amplifying circuit.
The buffer amplifier circuit that the embodiment of the present invention provides for the embodiment of the present invention, the noiseproof feature of the buffer amplifier adopted with prior art contrasts.
Contrast experiment 1: the input Vin1 incoming frequency respectively by the described amplifying circuit in the input Vin of the described buffer amplifier in background technology and the embodiment of the present invention is 40MHz, amplitude is the sinusoidal signal of 100mV, described buffer amplifier is identical with the DC power supply that described amplifying circuit adopts, the parameter of the first transistor M1 of described buffer amplifier is identical with the parameter of the first transistor A1 of described amplifying circuit, the parameter of the transistor seconds M2 of described buffer amplifier is identical with the parameter of the transistor seconds A2 of described amplifying circuit, described buffer amplifier is identical with the parameter of the load capacitance of described amplifying circuit.The contrast of the described buffer amplifier obtained by experiment and the phase noise performance of described amplifying circuit as shown in Figure 7.Curve 11 in Fig. 7 is the phase noise curve of described buffer amplifier output signal, curve 12 is the phase noise curve of described amplifying circuit output signal, can obtain from Fig. 7, the phase noise performance of described amplifying circuit is obviously better than the noiseproof feature of described buffer amplifier: at frequency deviation Δ f (=1Hz) place, the low about 0.97dB of noise of the output of the more described buffer amplifier of noise that described amplifying circuit exports; At frequency deviation Δ f (=100Hz) place, the low about 1.50dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports; At frequency deviation Δ f (=10MHz) place, the low about 2.80dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports.And as can be known from Fig. 7, at frequency deviation Δ f (=100Hz) place, the phase noise value of described buffer amplifier and described amplifying circuit is all lower than-145dBc/Hz, and under phase-noise case low like this, the phase noise of described amplifying circuit optimizes 1.50dB again; At frequency deviation Δ f (=10MHz) place, the phase noise value of described buffer amplifier and described amplifying circuit is all lower than-150dBc/Hz, and under phase-noise case low like this, the phase noise of described amplifying circuit optimizes 2.80dB again.
Contrast experiment 2: the input Vin1 incoming frequency respectively by the described amplifying circuit in the input Vin of the described buffer amplifier in background technology and the embodiment of the present invention is 40MHz, amplitude is the sinusoidal signal of 300mV, described buffer amplifier is identical with the DC power supply that described amplifying circuit adopts, the parameter of the first transistor M1 of described buffer amplifier is identical with the parameter of the first transistor A1 of described amplifying circuit, the parameter of the transistor seconds M2 of described buffer amplifier is identical with the parameter of the transistor seconds A2 of described amplifying circuit, described buffer amplifier is identical with the parameter of the load capacitance of described amplifying circuit.The contrast of the described buffer amplifier obtained by experiment and the phase noise performance of described amplifying circuit as shown in Figure 8.Curve 13 in Fig. 8 is the phase noise curve of described buffer amplifier output signal, curve 14 is the phase noise curve of described amplifying circuit output signal, can obtain from Fig. 8, the phase noise performance of described amplifying circuit is obviously better than the noiseproof feature of described buffer amplifier.At frequency deviation Δ f (=1Hz) place, the low about 1.95dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports; At frequency deviation Δ f (=100Hz) place, the low about 2.03dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports; At frequency deviation Δ f (=10MHz) place, the low about 3.40dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports.And as can be known from Fig. 8, at frequency deviation Δ f (=100Hz) place, the phase noise value of described buffer amplifier and described amplifying circuit is all lower than-145dBc/Hz, and under phase-noise case low like this, the phase noise of described amplifying circuit optimizes 2.03dB again; At frequency deviation Δ f (=10MHz) place, the phase noise value of described buffer amplifier and described amplifying circuit is all lower than-155dBc/Hz, and under phase-noise case low like this, the phase noise of described amplifying circuit optimizes 3.40dB again.
Contrast experiment 3: the input Vin1 incoming frequency respectively by the described amplifying circuit in the input Vin of the described buffer amplifier in background technology and the embodiment of the present invention is 40MHz, amplitude is the sinusoidal signal of 500mV, described buffer amplifier is identical with the DC power supply that described amplifying circuit adopts, the parameter of the first transistor M1 of described buffer amplifier is identical with the parameter of the first transistor A1 of described amplifying circuit, the parameter of the transistor seconds M2 of described buffer amplifier is identical with the parameter of the transistor seconds A2 of described amplifying circuit, described buffer amplifier is identical with the parameter of the load capacitance of described amplifying circuit.The contrast of the described buffer amplifier obtained by experiment and the phase noise performance of described amplifying circuit as shown in Figure 9.Curve 15 in Fig. 9 is the phase noise curve of described buffer amplifier output signal, curve 16 is the phase noise curve of described amplifying circuit output signal, can obtain from Fig. 9, the phase noise performance of described amplifying circuit is obviously better than the noiseproof feature of described buffer amplifier.At frequency deviation Δ f (=1Hz) place, the low about 1.82dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports; At frequency deviation Δ f (=100Hz) place, the low about 1.87dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports; At frequency deviation Δ f (=10MHz) place, the low about 3.62dB of phase noise of the output of the more described buffer amplifier of phase noise that described amplifying circuit exports.And as can be known from Fig. 9, at frequency deviation Δ f (=100Hz) place, the phase noise value of described buffer amplifier and described amplifying circuit is all lower than-145dBc/Hz, under phase-noise case low like this, the phase noise of described amplifying circuit optimizes 1.87dB again compared to the phase noise of described buffer amplifier; At frequency deviation Δ f (=10MHz) place, the phase noise value of described buffer amplifier and described amplifying circuit is all lower than-160dBc/Hz, under phase-noise case low like this, the phase noise of described amplifying circuit optimizes 3.62dB again compared to the phase noise of described buffer amplifier.
Can be found out by above-mentioned three contrast experiments, the described amplifying circuit that the embodiment of the present invention provides has better phase noise performance.
The embodiment of the present invention also contrasts the power consumption parameter of described amplifying circuit and described buffer amplifier:
Input Vin1 incoming frequency respectively by the described amplifying circuit in the input Vin of the described buffer amplifier in background technology and the embodiment of the present invention is 40MHz, amplitude is the sinusoidal signal of 500mV, described buffer amplifier is identical with the DC power supply that described amplifying circuit adopts, the parameter of the first transistor M1 of described buffer amplifier is identical with the parameter of the first transistor A1 of described amplifying circuit, the parameter of the transistor seconds M2 of described buffer amplifier is identical with the parameter of the transistor seconds A2 of described amplifying circuit, described buffer amplifier is identical with the parameter of the load capacitance of described amplifying circuit.The described buffer amplifier obtained by experiment and described amplifying circuit same cycle internal consumption current curve as shown in Figure 10.Curve 17 in Figure 10 is the current curve of described buffer amplifier at described cycle internal consumption, curve 18 is the current curve of described amplifying circuit at described cycle internal consumption, as can be seen from Figure 10, the electric current that described amplifying circuit consumes is starkly lower than the electric current that described buffer amplifier consumes.Mean value through calculating current is known, the average current that described buffer amplifier consumes is 4.908mA, and the average current that described amplifying circuit consumes is 4.116mA, the lower power consumption of the more described buffer amplifier of power consumption of the described amplifying circuit that the embodiment of the present invention provides is more than 16%, can be drawn by this experiment, the described amplifying circuit that the embodiment of the present invention provides not only has good phase noise performance, and power consumption is lower.
In sum, embodiments provide a kind of buffer amplifier circuit, comprising: biased amplifying unit 100, first compensating unit 200 and the second compensating unit 300; Wherein, described first compensating unit 200 and the second compensating unit 300 are by providing negative feedback for described biased amplifying unit 100, widen the signal bandwidth of described biased amplifying unit 100, make rising edge and the trailing edge steepening of the output signal of described amplifying circuit, reduce the modulation of transistor 1/f noise to the output signal of described amplifying circuit, thus obtain the phase of output signal noiseproof feature of improvement.Meanwhile, contrast discovery by experiment, the power consumption of the described amplifying circuit that the embodiment of the present invention provides is lower.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.
To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (10)
1. a buffer amplifier circuit, is characterized in that, comprising: biased amplifying unit, the first compensating unit and the second compensating unit; Wherein,
Described biased amplifying unit comprises biasing resistor, the first transistor, transistor seconds, described the first transistor, the grid of transistor seconds is connected with one end of described biasing resistor, as the signal input part of described amplifying circuit, described the first transistor, the drain electrode of transistor seconds is connected with the other end of described biasing resistor, as the signal output part of described biased amplifying unit, the source electrode of described the first transistor is connected with described first compensating unit, the source electrode of described transistor seconds is connected with described second compensating unit, input signal is sent to the grid of described the first transistor and transistor seconds by the signal input part of described amplifying circuit, export as the signal output part of the first signal via described biased amplifying unit after being amplified by described the first transistor and transistor seconds,
Described first compensating unit one end is connected with the source electrode of described the first transistor, other end ground connection, for providing negative feedback to described biased amplifying unit, improves the signal bandwidth of described biased amplifying unit;
Described second compensating unit one end is connected with the source electrode of described transistor seconds, and the other end is connected with power supply, for providing negative feedback to described biased amplifying unit, improves the signal bandwidth of described biased amplifying unit.
2. amplifying circuit according to claim 1, is characterized in that, described first compensating unit comprises the first resistance and the first electric capacity, described first resistance and the first Capacitance parallel connection, and its one end is connected with the source electrode of described the first transistor, other end ground connection.
3. amplifying circuit according to claim 1, is characterized in that, described second compensating unit comprises the second resistance and the second electric capacity, and described second resistance and the second Capacitance parallel connection, its one end is connected with the source electrode of described transistor seconds, and the other end is connected with power supply.
4. amplifying circuit according to claim 1, is characterized in that, described biased amplifying unit also comprises compensation amplifying unit, and described compensation amplifying unit comprises: third transistor and the 4th transistor; Wherein,
The grid of described third transistor, the 4th transistor is connected to the signal input part of described amplifying circuit, the drain electrode of described third transistor, the 4th transistor is connected to the signal output part of described biased amplifying unit, described third transistor is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 4th transistor is P-channel enhancement type field effect transistor, and its source electrode and substrate are connected with power supply;
Input signal is sent to the grid of described third transistor and the 4th transistor by the signal input part of described amplifying circuit, as secondary signal after being amplified by described third transistor and the 4th transistor, described secondary signal and described first Signal averaging form the second composite signal and are exported by the signal output part of described biased amplifying unit, to improve the signal gain of described amplifying circuit.
5. the amplifying circuit according to any one of claim 1-4, it is characterized in that, described amplifying circuit also comprises the first anti-phase amplifying unit, the signal input part of described first anti-phase amplifying unit is connected to the signal output part of described biased amplifying unit, for carrying out anti-phase amplification to the output signal of described biased amplifying unit, and export the 3rd signal by the signal output part of described first anti-phase amplifying unit.
6. amplifying circuit according to claim 5, is characterized in that, described first anti-phase amplifying unit comprises the 5th transistor and the 6th transistor; Wherein,
Described 5th transistor, the grid of the 6th transistor is connected to the signal output part of described biased amplifying unit, as the signal input part of described first anti-phase amplifying unit, described 5th transistor, the drain electrode of the 6th transistor connects, as the signal output part of described first anti-phase amplifying unit, described 5th transistor is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 6th transistor is P-channel enhancement type field effect transistor, its source electrode and substrate are connected to DC power supply, the output signal of described biased amplifying unit is sent to the grid of described 5th transistor and the 6th transistor by the signal input part of described first anti-phase amplifying unit, the 3rd signal is exported by the signal output part of described first anti-phase amplifying unit after the anti-phase amplification of described 5th transistor and the 6th transistor.
7. amplifying circuit according to claim 5, it is characterized in that, described amplifying circuit also comprises the second anti-phase amplifying unit, the signal input part of described second anti-phase amplifying unit is connected to the signal output part of described first anti-phase amplifying unit, for carrying out anti-phase amplification to described 3rd signal and exporting the 4th signal by the signal output part of described second anti-phase amplifying unit.
8. amplifying circuit according to claim 7, is characterized in that, described second anti-phase amplifying unit comprises: the 7th transistor and the 8th transistor; Wherein,
Described 7th transistor, the grid of the 8th transistor is connected to the signal output part of described first anti-phase amplifying unit, as the signal input part of described second anti-phase amplifying unit, described 7th transistor, the drain electrode of the 8th transistor connects, as the signal output part of described second anti-phase amplifying unit, described 7th transistor is N channel enhancement field effect transistor, its source electrode and Substrate ground, described 8th transistor is P-channel enhancement type field effect transistor, its source electrode and substrate are connected to DC power supply, described 3rd signal is sent to the grid of described 7th transistor and the 8th transistor by the signal input part of described second anti-phase amplifying unit, the 4th signal is exported by the signal output part of described second anti-phase amplifying unit after the anti-phase amplification of described 7th transistor and the 8th transistor.
9. the amplifying circuit according to claim 1-4 or any one of 6-8, is characterized in that, described amplifying circuit also comprises: capacitance;
One end of described capacitance is as the signal input part of described amplifying circuit, the other end is connected to described the first transistor, the grid of transistor seconds and the connected node of described biasing resistor, for the DC level of blocked input signal on the impact of described amplifying circuit.
10. amplifying circuit according to claim 1, is characterized in that, described the first transistor is N channel enhancement field effect transistor, and described transistor seconds is P-channel enhancement type field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510882013.0A CN105375887B (en) | 2015-12-03 | 2015-12-03 | Buffer amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510882013.0A CN105375887B (en) | 2015-12-03 | 2015-12-03 | Buffer amplifying circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105375887A true CN105375887A (en) | 2016-03-02 |
| CN105375887B CN105375887B (en) | 2018-10-16 |
Family
ID=55377750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510882013.0A Active CN105375887B (en) | 2015-12-03 | 2015-12-03 | Buffer amplifying circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105375887B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106921349A (en) * | 2017-03-02 | 2017-07-04 | 中国电子科技集团公司第二十四研究所 | Amplifier based on inverter structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101093956A (en) * | 2007-07-20 | 2007-12-26 | 开源集成电路(苏州)有限公司 | Under voltage locking circuit with temperature compensation |
| CN101252341A (en) * | 2008-03-11 | 2008-08-27 | 东南大学 | Wideband low noise amplifier |
| US20080258816A1 (en) * | 2006-11-21 | 2008-10-23 | Industrial Technology Research Institute | Low frequency analog circuit and design method thereof |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
-
2015
- 2015-12-03 CN CN201510882013.0A patent/CN105375887B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080258816A1 (en) * | 2006-11-21 | 2008-10-23 | Industrial Technology Research Institute | Low frequency analog circuit and design method thereof |
| CN101093956A (en) * | 2007-07-20 | 2007-12-26 | 开源集成电路(苏州)有限公司 | Under voltage locking circuit with temperature compensation |
| CN101252341A (en) * | 2008-03-11 | 2008-08-27 | 东南大学 | Wideband low noise amplifier |
| CN101419479A (en) * | 2008-12-10 | 2009-04-29 | 武汉大学 | Low-voltage difference linear constant voltage regulator with novel structure |
Non-Patent Citations (1)
| Title |
|---|
| 赵喆 等: "全CMOS温度补偿的参考电压电流源", 《微处理机》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106921349A (en) * | 2017-03-02 | 2017-07-04 | 中国电子科技集团公司第二十四研究所 | Amplifier based on inverter structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105375887B (en) | 2018-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103219961B (en) | Bandwidth-adjustable operational amplifier circuit | |
| CN103023440B (en) | Circuit for improving linearity of power amplifier | |
| CN103117718B (en) | high-fidelity transistor audio power amplifier | |
| JP2006094533A (en) | Differential amplifier circuit in the form of cascode with class ab control terminal | |
| CN103546127A (en) | Disorder-storage low-power-consumption high-speed comparator | |
| CN101917168B (en) | High switching rate transconductance amplifier for active power factor corrector | |
| CN203840288U (en) | Continuous time common mode feedback circuit for two-stage differential amplifier | |
| CN101951236A (en) | Digital variable gain amplifier | |
| CN207166461U (en) | Full differential operational amplifier | |
| CN201846315U (en) | Digital variable gain amplifier | |
| CN104883139A (en) | Double-switch power supply modulator for envelope tracking system | |
| CN107819445A (en) | A kind of big output voltage swing drive circuit of high speed | |
| CN207354224U (en) | Power amplification circuit for speaker of voice box | |
| CN105375887A (en) | Buffer amplifying circuit | |
| CN103107791A (en) | Gain linear variable gain amplifier with constant bandwidth | |
| CN101471634B (en) | Output stage circuit and operational amplifier applying the same | |
| CN103338015A (en) | Amplifier for increasing gain and design method of amplifier | |
| CN110176911A (en) | The high-low pressure differential amplifier circuit of BMS | |
| CN104682946B (en) | Differential signal-to-single-ended signal conversion circuit | |
| CN103616924A (en) | Sensor circuit | |
| CN206698188U (en) | The amplifier of low-voltage high linearity | |
| CN203747786U (en) | Level switching circuit for fully differential signals | |
| CN106059503A (en) | Voltage buffer amplifier | |
| US7986185B2 (en) | Rail-to-rail Miller compensation method without feed forward path | |
| CN203872141U (en) | Large-dynamic range variable gain amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |