CN105374740A - Semiconductor device and manufacturing method thereof, and electronic device - Google Patents
Semiconductor device and manufacturing method thereof, and electronic device Download PDFInfo
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- CN105374740A CN105374740A CN201410438535.7A CN201410438535A CN105374740A CN 105374740 A CN105374740 A CN 105374740A CN 201410438535 A CN201410438535 A CN 201410438535A CN 105374740 A CN105374740 A CN 105374740A
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and an electronic device. The method includes: (a) a semiconductor substrate is provided; (b) a first etching stopping layer and a first interlayer dielectric layer are formed on the semiconductor substrate in sequence, and a first copper metal interconnection structure is formed in the first interlayer dielectric layer; and (c) a second etching stopping layer and a second interlayer dielectric layer are formed in sequence, and a second copper metal interconnection structure electrically connected with the first copper metal interconnection structure and a pseudo copper metal layer used for shielding ultraviolet light from a subsequent process in order to avoid the irradiation of the first interlayer dielectric layer are formed in the second interlayer dielectric layer. According to the semiconductor device and the manufacturing method thereof, the mechanical strength of the multi-layer copper metal interconnection structure formed by employing the method can be effectively improved, and delamination of positions of each layer of interfaces is avoided.
Description
Technical field
The present invention relates to semiconductor fabrication process, in particular to a kind of semiconductor device and manufacture method, electronic installation.
Background technology
For the logical circuit in semiconductor device, the number of plies of copper metal interconnecting layer reaches several layers and even ten several layers.As shown in Fig. 1 (a), the Semiconductor substrate 100 being formed with front-end devices is formed the first stacked from bottom to top etching stopping layer 101 and the first interlayer dielectric layer 102, in the first interlayer dielectric layer 102, is formed with the first bronze medal metal interconnect structure M1 be communicated with described front-end devices; First interlayer dielectric layer 102 is formed the second stacked from bottom to top etching stopping layer 201 and the second interlayer dielectric layer 202, in the second interlayer dielectric layer 202, is formed with the second bronze medal metal interconnect structure M2 be communicated with the first bronze medal metal interconnect structure M1; Second interlayer dielectric layer 202 is formed dielectric layer 302 between the 3rd stacked from bottom to top etching stopping layer 301 and third layer, between third layer, in dielectric layer 302, is formed with the 3rd bronze medal metal interconnect structure M3 be communicated with the second bronze medal metal interconnect structure M2; Dielectric layer 302 is formed with the 4th stacked etching stopping layer 401 and the 4th interlayer dielectric layer 402 between third layer from bottom to top, in the 4th interlayer dielectric layer 402, is formed with the 4th bronze medal metal interconnect structure M4 be communicated with the 3rd bronze medal metal interconnect structure M3; 4th interlayer dielectric layer 402 is formed dielectric layer 502 between the 5th stacked from bottom to top etching stopping layer 501 and layer 5, between layer 5, in dielectric layer 502, is formed with the 5th bronze medal metal interconnect structure M5 be communicated with the 4th bronze medal metal interconnect structure M4.
After often forming one deck interlayer dielectric layer, all need to implement ultraviolet irradiation, to reduce the dielectric constant of interlayer dielectric layer.Upper strata interlayer dielectric layer is being implemented in the process of ultraviolet irradiation, lower floor's interlayer dielectric layer shrinks phenomenon, in addition the stress effect that lower floor's copper metal interconnect structure in lower floor's interlayer dielectric layer is intrinsic is formed at, in the meeting of the interface 103 of upper and lower two-layer interlayer dielectric layer, delamination occurs, and then cause the inefficacy of device.
Therefore, need to propose a kind of method, to solve the problem.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: (a) provides Semiconductor substrate; B () forms the first etching stopping layer and the first interlayer dielectric layer on the semiconductor substrate successively, form the first bronze medal metal interconnect structure in described first interlayer dielectric layer; C () forms the second etching stopping layer and the second interlayer dielectric layer successively, and in described second interlayer dielectric layer, form the second bronze medal metal interconnect structure of being electrically connected with described first bronze medal metal interconnect structure and for blocking ultraviolet light from subsequent handling to avoid the pseudo-copper metal layer of the irradiation to described first interlayer dielectric layer.
In one example, repeat step (b)-(c), until form the multiple layer of copper metal interconnect structure be made up of the multiple stacked and described first bronze medal metal interconnect structure be communicated with and described second bronze medal metal interconnect structure are formed stepped construction from bottom to top.
In one example, after forming described first interlayer dielectric layer, described second interlayer dielectric layer respectively, all adopt the interlayer dielectric layer formed described in ultraviolet irradiation, to reduce dielectric constant further.
In one example, described second bronze medal metal interconnect structure and described pseudo-copper metal layer are isolated from each other.
In one example, described second bronze medal metal interconnect structure is electrically connected with described pseudo-copper metal layer.
In one example, in the operation forming described second bronze medal metal interconnect structure, form described pseudo-copper metal layer simultaneously.
In one embodiment, the present invention also provides a kind of semiconductor device adopting said method to manufacture.
In one embodiment, the present invention also provides a kind of electronic installation, and described electronic installation comprises described semiconductor device.
According to the present invention, effectively can strengthen the mechanical strength of described multiple layer of copper metal interconnect structure, delamination occurs to avoid position, each bed boundary.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the schematic diagram that delamination occurs in multiple layer of copper metal interconnect structure;
Fig. 2 is the schematic cross sectional view of the multiple layer of copper metal interconnect structure of the method formation of according to an exemplary embodiment of the present one.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed step is proposed, to explain semiconductor device and manufacture method, the electronic installation of the present invention's proposition.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
[exemplary embodiment one]
With reference to Fig. 2, the schematic cross sectional view of the multiple layer of copper metal interconnect structure that the method that illustrated therein is according to an exemplary embodiment of the present is formed.
The Semiconductor substrate 1000 being formed with front-end devices is formed the first stacked from bottom to top etching stopping layer 1001 and the first interlayer dielectric layer 1002, the device that described front-end devices is formed before referring to the post phase manufacturing technique (BEOL) implementing semiconductor device, is formed with the first bronze medal metal interconnect structure N1 be communicated with described front-end devices in the first interlayer dielectric layer 1002; First interlayer dielectric layer 1002 is formed the second stacked from bottom to top etching stopping layer 2001 and the second interlayer dielectric layer 2002, in the second interlayer dielectric layer 2002, be formed with the second bronze medal metal interconnect structure (do not give in figure and illustrating) be communicated with the first bronze medal metal interconnect structure N1, be also formed in the second interlayer dielectric layer 2002 to be isolated from each other with described second bronze medal metal interconnect structure or to be electrically connected for blocking ultraviolet light from subsequent handling to avoid the first pseudo-copper metal layer L1 of the irradiation to the first interlayer dielectric layer 1002; Second interlayer dielectric layer 2002 is formed dielectric layer 3002 between the 3rd stacked from bottom to top etching stopping layer 3001 and third layer, between third layer, in dielectric layer 3002, is formed with the 3rd bronze medal metal interconnect structure N3 be communicated with described second bronze medal metal interconnect structure; Dielectric layer 3002 is formed with the 4th stacked etching stopping layer 4001 and the 4th interlayer dielectric layer 4002 between third layer from bottom to top, in the 4th interlayer dielectric layer 4002, be formed with the 4th bronze medal metal interconnect structure (do not give in figure and illustrating) be communicated with the 3rd bronze medal metal interconnect structure N3, be also formed in the 4th interlayer dielectric layer 4002 to be isolated from each other with described 4th bronze medal metal interconnect structure or to be electrically connected for blocking ultraviolet light from subsequent handling with the second pseudo-copper metal layer L2 of the irradiation of dielectric layer 3002 between avoiding third layer; 4th interlayer dielectric layer 4002 is formed dielectric layer 5002 between the 5th stacked from bottom to top etching stopping layer 5001 and layer 5, between layer 5, in dielectric layer 5002, is formed with the 5th bronze medal metal interconnect structure N5 be communicated with described 4th bronze medal metal interconnect structure.By that analogy, the multiple layer of copper metal interconnect structure with said structure feature can be formed in the Semiconductor substrate 1000 being formed with front-end devices.
Copper metal interconnect structure in above-mentioned multiple layer of copper metal interconnect structure and the formation method of pseudo-copper metal layer similar, the copper metal interconnect structure and the pseudo-copper metal layer that are arranged in same interlayer dielectric layer can be formed in same operation.Only be described for the first bronze medal metal interconnect structure N1 be formed in Semiconductor substrate 1000 below.
First, provide Semiconductor substrate 1000, adopt chemical vapor deposition method in Semiconductor substrate 1000, form the first etching stopping layer 1001 and the first interlayer dielectric layer 1002 successively.
Semiconductor substrate 1000 is formed with front-end devices, in order to simplify, does not give in legend and illustrating.The device that described front-end devices is formed before referring to and implementing the post phase manufacturing technique of semiconductor device, does not limit the concrete structure of front-end devices at this.Described front-end devices comprises grid structure, and as an example, grid structure comprises the gate dielectric and gate material layers that stack gradually from bottom to top.Be formed with side wall construction in the both sides of grid structure, in the Semiconductor substrate 1000 of side wall construction both sides, be formed with source/drain region, be channel region between source/drain region; The top and source/drain region of grid structure are formed with self-aligned silicide.
Material preferred SiCN, SiC or SiN of first etching stopping layer 1001, it with while the etching stopping layer forming the first bronze medal metal interconnect structure N1 wherein, can prevent the copper in the first bronze medal metal interconnect structure N1 to be diffused in the interlayer dielectric layer at described front-end devices place as subsequent etch first interlayer dielectric layer 1002.
The constituent material of the first interlayer dielectric layer 1002 can be selected from this area common various low-ks (k value) material, include but not limited to that k value is the silicate compound (HydrogenSilsesquioxane of 2.5-2.9, referred to as HSQ), k value be 2.2 methane-siliconic acid salt compound (MethylSilsesquioxane, be called for short MSQ), k value be the HOSP of 2.8
tM(advanced low-k materials of the mixture based on organic substance and Si oxide that Honeywell company manufactures) and k value are the SiLK of 2.65
tM(a kind of advanced low-k materials that DowChemical company manufactures) etc.Usually, the method such as ultraviolet irradiation or heating is adopted to make the first interlayer dielectric layer 1002 porous of formation, to reduce the dielectric constant of the first interlayer dielectric layer 1002 further.
Next, in the first interlayer dielectric layer 1002, form the first bronze medal metal interconnect structure N1 being communicated with described front-end devices.The step forming the first bronze medal metal interconnect structure N1 comprises: on the first interlayer dielectric layer 1002, form resilient coating and hard mask layer successively, avoids the porous structure of mechanical stress to the first interlayer dielectric layer 1002 to cause damage when the effect of resilient coating is the copper metal interconnecting layer in follow-up grinding formation first bronze medal metal interconnect structure N1; In hard mask layer, form the first opening, to expose the resilient coating of below, described first opening is used as the pattern of the groove in the first bronze medal metal interconnect structure N1; In resilient coating and interlayer dielectric layer, form the second opening, described second opening is used as the pattern of the through hole in the first bronze medal metal interconnect structure N1; Take hard mask layer as mask, synchronous etch buffer layers and the first interlayer dielectric layer 1002, namely synchronously form the groove in the first bronze medal metal interconnect structure N1 and through hole, described in be etched in when exposing the first etching stopping layer 1001 stop; Remove the first etching stopping layer 1001 exposed by the first bronze medal metal interconnect structure N1, be communicated with described front-end devices to make the first bronze medal metal interconnect structure N1, in the present embodiment, dry method etch technology is adopted to implement the removal of the first etching stopping layer 1001 exposed; Perform etching last handling process, to remove the residuals and impurity that aforementioned etching process produces.
The technical process of above-mentioned formation first bronze medal metal interconnect structure N1 is only the one in dual damascene process, what those skilled in the art should know is, adopt other execution mode in dual damascene process can form the first bronze medal metal interconnect structure N1 equally, the throughhole portions such as first forming the first bronze medal metal interconnect structure N1 forms the trench portions of the first bronze medal metal interconnect structure N1 again, does not repeat them here the implementation step that it is detailed.
Next, in the first bronze medal metal interconnect structure N1, copper metal interconnecting layer is formed.Form the various suitable technology that copper metal interconnecting layer can adopt those skilled in the art to have the knack of, such as physical gas-phase deposition or electroplating technology.
Before forming copper metal interconnecting layer, copper metal diffusion barrier layer and copper metal seed layer need be formed successively on the bottom of the first bronze medal metal interconnect structure N1 and sidewall, in order to simplify, not give in figure and illustrating.Copper metal diffusion barrier layer can prevent copper in copper metal interconnecting layer to the diffusion in the first interlayer dielectric layer 1002, and copper metal seed layer can strengthen the tack between copper metal interconnecting layer and copper metal diffusion barrier layer.The various suitable technology that formation copper metal diffusion barrier layer and copper metal seed layer can adopt those skilled in the art to have the knack of, such as, adopt physical gas-phase deposition to form copper metal diffusion barrier layer, adopt sputtering technology or chemical vapor deposition method to form copper metal seed layer.The material of copper metal diffusion barrier layer is metal, metal nitride or its combination, the combination of preferred Ta and TaN or the combination of Ti and TiN.
Then, chemical mechanical milling tech is performed, until expose the first interlayer dielectric layer 1002.In the process, hard mask layer and resilient coating are all removed.
According to the present invention, effectively can strengthen the mechanical strength of above-mentioned multiple layer of copper metal interconnect structure, delamination occurs to avoid position, each bed boundary.
[exemplary embodiment two]
The present invention also provides a kind of semiconductor device, and described semiconductor device comprises multiple layer of copper metal interconnect structure prepared by the method according to exemplary embodiment one.Described semiconductor device, owing to employing described multiple layer of copper metal interconnect structure, thus has better performance.
[exemplary embodiment three]
The present invention also provides a kind of electronic installation, and it comprises the semiconductor device described in exemplary embodiment two.Described electronic installation can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.Described electronic installation, owing to employing described semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (8)
1. a manufacture method for semiconductor device, comprising:
A () provides Semiconductor substrate;
B () forms the first etching stopping layer and the first interlayer dielectric layer on the semiconductor substrate successively, form the first bronze medal metal interconnect structure in described first interlayer dielectric layer;
C () forms the second etching stopping layer and the second interlayer dielectric layer successively, and in described second interlayer dielectric layer, form the second bronze medal metal interconnect structure of being electrically connected with described first bronze medal metal interconnect structure and for blocking ultraviolet light from subsequent handling to avoid the pseudo-copper metal layer of the irradiation to described first interlayer dielectric layer.
2. method according to claim 1, it is characterized in that, repeat step (b)-(c), until form the multiple layer of copper metal interconnect structure be made up of the multiple stacked and described first bronze medal metal interconnect structure be communicated with and described second bronze medal metal interconnect structure are formed stepped construction from bottom to top.
3. method according to claim 1, is characterized in that, after forming described first interlayer dielectric layer, described second interlayer dielectric layer respectively, all adopts the interlayer dielectric layer formed described in ultraviolet irradiation, to reduce dielectric constant further.
4. method according to claim 1, is characterized in that, described second bronze medal metal interconnect structure and described pseudo-copper metal layer are isolated from each other.
5. method according to claim 1, is characterized in that, described second bronze medal metal interconnect structure is electrically connected with described pseudo-copper metal layer.
6. method according to claim 1, is characterized in that, in the operation forming described second bronze medal metal interconnect structure, form described pseudo-copper metal layer simultaneously.
7. the semiconductor device of the method manufacture adopting one of claim 1-6 described.
8. an electronic installation, described electronic installation comprises semiconductor device according to claim 7.
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Cited By (1)
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