CN105355620B - A kind of copper interconnection structure and its manufacturing method - Google Patents
A kind of copper interconnection structure and its manufacturing method Download PDFInfo
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- CN105355620B CN105355620B CN201510953119.5A CN201510953119A CN105355620B CN 105355620 B CN105355620 B CN 105355620B CN 201510953119 A CN201510953119 A CN 201510953119A CN 105355620 B CN105355620 B CN 105355620B
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- 229910052802 copper Inorganic materials 0.000 title claims abstract description 108
- 239000010949 copper Substances 0.000 title claims abstract description 108
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 title claims abstract description 106
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 97
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 47
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims abstract description 37
- 238000005516 engineering process Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000009713 electroplating Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 42
- 239000000463 material Substances 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- 229910052796 boron Inorganic materials 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 239000007788 liquid Substances 0.000 claims description 5
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 4
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-O ammonium group Chemical group [NH4+] QGZKDVFQNNGYKY-UHFFFAOYSA-O 0.000 claims description 3
- 229910052681 coesite Inorganic materials 0.000 claims description 3
- 229910052906 cristobalite Inorganic materials 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 229910052682 stishovite Inorganic materials 0.000 claims description 3
- 238000005979 thermal decomposition reaction Methods 0.000 claims description 3
- 229910052905 tridymite Inorganic materials 0.000 claims description 3
- 229910002651 NO3 Inorganic materials 0.000 claims description 2
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 claims description 2
- 230000033116 oxidation-reduction process Effects 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims 1
- 239000003292 glue Substances 0.000 claims 1
- 238000004062 sedimentation Methods 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 230000000903 blocking effect Effects 0.000 abstract description 4
- 239000007789 gas Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000003701 mechanical milling Methods 0.000 description 4
- 229910017604 nitric acid Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- HZAXFHJVJLSVMW-UHFFFAOYSA-N 2-Aminoethan-1-ol Chemical compound NCCO HZAXFHJVJLSVMW-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- CQKBIUZEUFGQMZ-UHFFFAOYSA-N [Ru].[Au] Chemical compound [Ru].[Au] CQKBIUZEUFGQMZ-UHFFFAOYSA-N 0.000 description 2
- 150000001336 alkenes Chemical class 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 150000001721 carbon Chemical group 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000001412 amines Chemical class 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- HSJPMRKMPBAUAU-UHFFFAOYSA-N cerium(3+);trinitrate Chemical compound [Ce+3].[O-][N+]([O-])=O.[O-][N+]([O-])=O.[O-][N+]([O-])=O HSJPMRKMPBAUAU-UHFFFAOYSA-N 0.000 description 1
- 150000001879 copper Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 229940031098 ethanolamine Drugs 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003462 sulfoxides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
Abstract
The invention belongs to semiconductor integrated circuit manufacturing process technology fields, disclose a kind of copper interconnection structure, including Semiconductor substrate, dielectric layer, graphene barrier layer, ruthenium metal barrier and metallic copper.The present invention provides a kind of copper interconnection structure and its manufacturing methods for this, copper seed layer can be saved using ruthenium metal barrier, subsequent selective copper electroplating technology can directly be carried out, since ruthenium metal barrier is relatively thin, blocking capability is limited, but the graphene barrier layer being matched therewith can effectively barrier metal copper be spread to dielectric layer, and its resistivity ratio copper is lower, the resistance of generation, which can be neglected, not to be remembered, and so as to which the overall electrical resistance for making copper-connection varies less, device power consumption reduces；Simultaneously as the thinner thickness on graphene barrier layer, can be very good to keep the profile pattern of through-hole, does not influence the fillibility of subsequent copper electroplating technology, metallic copper is avoided to generate gap, improve the yield and consistency of device.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing process technology fields, are related to a kind of copper interconnection structure and its manufacturer
Method.
Background technology
As CMOS transistor size constantly reduces, in the number of transistors in high efficiency, high density integrated circuit
Several ten million are raised to, the signal of the active component of these substantial amounts, which integrates, needs much ten layers or more of high desnity metal to connect
Line, however the resistance that brings of these metal interconnecting wires and parasitic capacitance have become this efficient integrated circuit of limitation it is main because
Element, therefore, semi-conductor industry gradually develop into metal copper-connection from original aluminium interconnection process.
Fig. 1 is the existing process flow chart for preparing copper interconnection structure, and this method includes the following steps：
Step S01 refers to Fig. 1 a, provides semi-conductive substrate 101, and low dielectric is deposited in Semiconductor substrate 101
Constant dielectric layer 102 forms through-hole 103 using lithography and etching technique on low dielectric coefficient medium layer 102；
Step S02 refers to Fig. 1 b, the upper table in the bottom of through-hole 103, side wall and low dielectric coefficient medium layer 102
Face forms barrier layer 104 and copper seed layer 105.
Step S03 refers to Fig. 1 c, the filling copper interconnection layer 106 in through-hole 103, and copper interconnection layer 106 covers copper seed crystal
The upper surface of layer 105；
Step S04 refers to Fig. 1 d, removes copper interconnection layer 106, copper seed layer 105 and barrier layer 104 outside through-hole,
Form copper interconnection structure 107.
In the preparation process of current copper interconnection structure, there is following defect：
First, existing copper wiring technique is for 28nm technologies and hereinafter, the thickness on barrier layer 104 accounts for entire copper-connection leads to
The ratio of hole characteristic size is higher and higher, and the resistance of entire copper conducting wire structure is caused to rise, and device power consumption rises (with barrier layer
For TaN, the resistivity of barrier layer TaN is that the resistivity of 200 μ Ω cm, Cu conducting wires is 1.69 μ Ω cm).
Secondly, Fig. 2 a are referred to, when depositing barrier layer 104 and copper seed layer 105, generally use physical vapour deposition (PVD)
(PVD) mode will appear 201 phenomenons of overhanging in via top, change via profiles pattern, and via openings size is caused to become
It is small, the defects of causing difficulty to the filling of subsequent copper plating, easily generate cavity 202 in through-holes, influence copper interconnection structure
Reliability.
In addition, Fig. 2 b are referred to, the copper interconnection layer 106, copper seed layer 105 and barrier layer 104 outside removal through-hole
In the process, it as a result of the weaker low dielectric coefficient medium layer 102 of mechanical performance, can be led because of pressure and cross shear
Low dielectric coefficient medium layer 102 is caused to occur being broken or be layered 203 (delamination), makes the reduction of copper interconnection structure yield；Together
When, refer to Fig. 2 c, due between barrier layer 104 (Ta/TaN) and copper interconnection layer 106 there are potential difference, during CMP
Galvanic corrosion (galvanic corrosion) can be generated and the part copper in through-hole is made to lack 204, cause copper interconnection structure can
It is reduced by property.Therefore, it is urgent to provide a kind of copper interconnection structure and its manufacturing methods by those skilled in the art, improve existing copper-connection
The pattern of structure ensures the fillibility of follow-up copper interconnection layer, improves the yield and consistency of device.
Invention content
The technical problems to be solved by the invention are to provide a kind of copper interconnection structure and its manufacturing method, and it is mutual to improve existing copper
Link the pattern of structure, ensure the fillibility of follow-up copper interconnection layer, improve the yield and yield of device.
In order to solve the above technical problem, the present invention provides a kind of copper interconnection structure, the copper interconnection structure includes：
Semiconductor substrate；
Dielectric layer, the dielectric layer is covered in the upper surface of the substrate, and has a through-hole on the dielectric layer；
Graphene barrier layer is formed in bottom and the side wall of the through-hole；
Ruthenium metal barrier is covered in bottom and the side wall on the graphene barrier layer；
Metallic copper is filled in the through-hole, and the upper surface of the metallic copper is concordant with the upper surface of the dielectric layer.
Preferably, the material of the dielectric layer is SiO2, SiN, advanced low-k materials, ultra-low dielectric constant material or six
It is one or more in square boron nitride layer.
Preferably, the dielectric layer includes black diamond material layer and hexagonal boron successively from the bottom up.
The present invention also provides a kind of methods for manufacturing copper interconnection structure, include the following steps：
Step S01, providing one has the substrate of dielectric layer, and a through-hole is formed on the dielectric layer；
Step S02 grows graphene barrier layer and ruthenium metal barrier successively in the through-hole；
Step S03 is formed the first photoresist in the through-hole, and is removed on the graphene barrier layer using it as mask
The ruthenium metal barrier on surface；
Step S04 removes first photoresist, and cleans substrate surface；
Step S05 fills metallic copper, and the upper table of the metallic copper using selective copper electroplating technology in the through-hole
Face is concordant with the upper surface of the dielectric layer；
Step S06 forms second photoresist equal with its width in the upper surface of the metallic copper, and with described second
Photoresist removes the graphene barrier layer of the dielectric layer upper surface for mask；
Step S07 removes second photoresist, forms copper interconnection structure.
Preferably, in step S02, using low temperature chemical vapor deposition method, atomic vapor deposition method, SiC thermal decomposition methods or
Oxidation-reduction method forms the graphene barrier layer, and the thickness on the graphene barrier layer is 0.34-3.4nm.
Preferably, in step S02, the ruthenium metal barrier, the ruthenium metal resistance are formed using atomic vapor deposition method
The thickness of barrier is 1-3nm.
Preferably, in step S03, the graphene is removed using wet-etching technology or reactive ion etching process and is stopped
The ruthenium metal barrier of layer upper surface.
Preferably, wet-etching technology is used to remove the etching liquid of the ruthenium metal barrier as ammonium ceric nitrate and nitric acid
Mixed liquor, HNO3And NH4Mixed liquor, the H of F2SO4And H2O2Mixed liquor, dilute HF it is one or more.
Preferably, use reactive ion etching process remove the etching gas of the ruthenium metal barrier for containing F, Cl or
It is one or more in XeF gases.
Preferably, in step S06, dry etch process is used to remove the etching gas on the graphene barrier layer as H2、O2
Or CxFyGas it is one or more.
The present invention provides a kind of copper interconnection structure and its manufacturing method, graphene barrier layer and ruthenium metal barrier replace
For existing barrier layer, copper seed layer can be saved using ruthenium metal barrier, can directly carry out subsequent selective copper electricity
Depositing process, since ruthenium metal barrier is relatively thin, blocking capability is limited, but the graphene barrier layer being matched therewith is by its institute
The equal saturation bonding of carbon atom of some sp2 hydridization, atomic arrangement in honeycomb structure it is sufficiently stable, can effectively barrier metal copper to
Dielectric layer is spread, and its resistivity ratio copper is lower, and the resistance of generation, which can be neglected, not to be remembered, so as to become the overall electrical resistance of copper-connection
Change very little, device power consumption reduces；Simultaneously as the thinner thickness on graphene barrier layer, can be very good to keep the profile of through-hole
Pattern does not influence the fillibility of subsequent copper electroplating technology, and metallic copper is avoided to generate gap；In addition, graphene barrier layer due to
Its electric conductivity can realize subsequent selective copper electroplating technology, i.e., on the ruthenium metal barrier of metallic copper only in through-holes
Electrodeposition, and avoid carrying out copper electroplating technology on graphene barrier layer.The present invention using selective copper electroplating technology and
Photoetching, etching technics form copper interconnection structure, avoid the chemical mechanical milling tech in conventional preparation techniques, avoid and changing
The various defects generated during mechanical milling tech are learned, improve the yield and yield of device.
Description of the drawings
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to needed in the embodiment
Attached drawing is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for ability
For the those of ordinary skill of domain, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 a- Fig. 1 d are the structure diagram of existing copper interconnection structure；
Fig. 2 a- Fig. 2 c are the defects of existing copper interconnection structure schematic diagram；
Fig. 3 is the flow diagram of the manufacturing method of copper interconnection structure proposed by the present invention；
Fig. 4 a- Fig. 4 g are the schematic diagram of the processing step proposed by the present invention for forming copper interconnection structure.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with implementation of the attached drawing to the present invention
Mode is described in further detail.Those skilled in the art can understand the present invention easily as the content disclosed by this specification
Other advantages and effect.The present invention can also be embodied or applied by other different embodiments, this explanation
Every details in book can also be based on different viewpoints and application, without departing from the spirit of the present invention carry out various modifications or
Change.
Above and other technical characteristic and advantageous effect, will in conjunction with the embodiments and attached drawing is to copper-connection knot proposed by the present invention
Structure and its manufacturing method are described in detail.Fig. 3 is the flow diagram of the manufacturing method of copper interconnection structure proposed by the present invention；
Fig. 4 a- Fig. 4 g are the schematic diagram of the processing step proposed by the present invention for forming copper interconnection structure.
The present invention provides a kind of copper interconnection structure, including Semiconductor substrate 401, dielectric layer 402, graphene barrier layer
404th, ruthenium metal barrier 405 and metallic copper 407；Wherein, dielectric layer 402 is covered in the upper surface of substrate 401, and dielectric layer
There is a through-hole 403, graphene barrier layer 404 is formed in bottom and the side wall of through-hole 403, ruthenium metal barrier 405 on 401
Bottom and the side wall on graphene barrier layer 404 are covered in, metallic copper 407 is filled in through-hole 403, and metallic copper 407 is upper
Surface is concordant with the upper surface of dielectric layer 402.
Copper interconnection structure disclosed in this invention can be made by many methods, and as described below, which is that this law is bright, is proposed
Manufacture one embodiment as shown in Figure 3 technological process.As shown in figure 3, the embodiment of the present invention provides a kind of manufacture copper-connection
The method of structure, includes the following steps：
Step S01 please refers to Fig. 4 a, and providing one has the substrate 401 of dielectric layer 402, and a through-hole is formed on dielectric layer 402
403。
In this step, the material of substrate 401 is preferably Si, and the material of dielectric layer 402 is preferably SiO2, SiN, low dielectric it is normal
It is one or more in number material, ultra-low dielectric constant material or hexagonal boron, wherein, advanced low-k materials refer to dielectric
Constant is less than 3 material, and ultra-low dielectric constant material refers to the material that dielectric constant is less than 2.5.Dielectric layer 402 in the present embodiment
Include black diamond material layer (Black Diamond, BD) 402a and hexagonal boron 402b, six side's nitrogen successively from the bottom up
The thickness for changing boron layer 402b is 15nm；The depth of the size of through-hole 403 in the present embodiment is preferably 250nm, 403 feature of through-hole
It is preferably dimensioned to be 65nm.It can ensure the growth on follow-up graphene barrier layer 404 in the present embodiment using hexagonal boron 402b
Quality.
Step S02 please refers to Fig. 4 b, grows graphene barrier layer 404 and ruthenium metal barrier successively in through-hole 403
405。
In this step, using low temperature chemical vapor deposition method, atomic vapor deposition method, SiC thermal decomposition methods or redox
Method forms graphene barrier layer 404, and the thickness on graphene barrier layer 404 is preferably 0.34-3.4nm, the graphite in the present embodiment
The thickness on alkene barrier layer 404 is 1.7nm；Meanwhile ruthenium metal barrier 405, the resistance of ruthenium metal are formed using atomic vapor deposition method
The thickness of barrier 405 is preferably 1-3nm, and the thickness of the ruthenium metal barrier 405 in embodiment is 2nm.
Step S03 please refers to Fig. 4 c, the first photoresist 406 is formed in through-hole 403, and remove graphite using it as mask
The ruthenium metal barrier 405 of 404 upper surface of alkene barrier layer.
In this step, using 404 upper surface of wet-etching technology or reactive ion etching process removal graphene barrier layer
Ruthenium metal barrier 405, wherein, use the etching liquid of wet-etching technology removal ruthenium metal barrier 405 as cerous nitrate
The mixed liquor of ammonium and nitric acid, HNO3And NH4Mixed liquor, the H of F2SO4And H2O2Mixed liquor, dilute HF it is one or more, using anti-
The etching gas for answering ion etch process removal ruthenium metal barrier 405 is containing one or more in F, Cl or XeF gas.This
In embodiment, using HF and NH4The mixed liquor and HNO of F3And NH4The mixed liquor removal ruthenium metal barrier 405 of F.Due to this
404 chemical property of graphene barrier layer in embodiment is stablized, and acid and alkali-resistance, therefore, the wet-etching technology in the present embodiment stop
Only in 404 upper surface of graphene barrier layer.
Step S04 please refers to Fig. 4 d, removes the first photoresist 406, and clean substrate surface.
In this step, wet-etching technology can be used and remove the first photoresist 406, wherein, etching liquid is preferably diformazan
The mixed solution of sulfoxide, ammonium fluoride and hydrofluoric acid.
Step S05 please refers to Fig. 4 e, and metallic copper 407, and gold are filled in through-hole 403 using selective copper electroplating technology
The upper surface for belonging to copper 407 is concordant with the upper surface of dielectric layer 402.
Since wafer surface is covered by graphene barrier layer 404 in the present embodiment, since graphene has good conduction
Performance, therefore copper electroplating technology can be carried out.Further, due to only having there is ruthenium metal barrier 405 in through-hole 403, because
This copper electroplating technology has selectivity, i.e., is only deposited in through-hole 403, and is not deposited on the graphene barrier layer 404 on surface.
Step S06 please refers to Fig. 4 f, and second photoresist equal with its width is formed in the upper surface of metallic copper 407
408, and the graphene barrier layer 404 with the second photoresist 408 for 402 upper surface of mask removal dielectric layer.
In this step, it is preferred to use the etching gas on dry etch process removal graphene barrier layer 404 is H2、O2Or
CxFyGas it is one or more.In the present embodiment, the use of graphene barrier layer 404 for removing surface is containing O2Gas is done
Method lithographic method.
Step S07 please refers to Fig. 4 g, removes the second photoresist 408, forms copper interconnection structure.
In this step, wet-etching technology can be used and remove the second photoresist 408, etching liquid is preferably ethanol amine, uncle
The mixed liquor of amine, hydrogen fluoride and ammonium hydroxide；After removing the second photoresist 408, chip can further be cleaned, form copper
Interconnection structure.
In conclusion the present invention provides a kind of copper interconnection structure and its manufacturing method, graphene barrier layer and ruthenium gold
Belong to barrier layer instead of existing barrier layer, copper seed layer can be saved using ruthenium metal barrier, can directly be carried out subsequent
Selective copper electroplating technology, since ruthenium metal barrier is relatively thin, blocking capability is limited, but the graphene blocking being matched therewith
For layer due to the equal saturation bonding of the carbon atom of its all sp2 hydridization, atomic arrangement is sufficiently stable in honeycomb structure, can effectively hinder
It keeps off metallic copper to spread to dielectric layer, and its resistivity ratio copper is lower, the resistance of generation, which can be neglected, not to be remembered, so as to make copper-connection
Overall electrical resistance varies less, and device power consumption reduces；Simultaneously as the thinner thickness on graphene barrier layer, can be very good to keep
The profile pattern of through-hole does not influence the fillibility of subsequent copper electroplating technology, and metallic copper is avoided to generate gap；In addition, graphene
Barrier layer can realize subsequent selective copper electroplating technology, i.e. the ruthenium gold of metallic copper only in through-holes due to its electric conductivity
Belong to electrodeposition on barrier layer, and avoid carrying out copper electroplating technology on graphene barrier layer.The present invention is using selective copper electricity
Depositing process and photoetching, etching technics form copper interconnection structure, avoid the chemical mechanical milling tech in conventional preparation techniques,
The various defects generated during chemical mechanical milling tech are avoided, improve the yield and yield of device.
Several preferred embodiments of the present invention have shown and described in above description, but as previously described, it should be understood that the present invention
Be not limited to form disclosed herein, be not to be taken as the exclusion to other embodiment, and available for various other combinations,
Modification and environment, and the above teachings or related fields of technology or knowledge can be passed through in the scope of the invention is set forth herein
It is modified.And changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, then it all should be in this hair
In the protection domain of bright appended claims.
Claims (9)
1. a kind of copper interconnection structure, which is characterized in that the copper interconnection structure includes：
Semiconductor substrate；
Dielectric layer, the dielectric layer is covered in the upper surface of the substrate, and has a through-hole, the medium on the dielectric layer
Layer includes black diamond material layer and hexagonal boron successively from the bottom up；
Graphene barrier layer is formed in bottom and the side wall of the through-hole；
Ruthenium metal barrier is covered in bottom and the side wall on the graphene barrier layer；
Metallic copper is filled in the through-hole, and the upper surface of the metallic copper is concordant with the upper surface of the dielectric layer.
2. copper interconnection structure according to claim 1, which is characterized in that the material of the dielectric layer is SiO2, SiN, low Jie
It is one or more in permittivity material, ultra-low dielectric constant material or hexagonal boron.
A kind of 3. method for manufacturing the copper interconnection structure as described in claim 1~2 is any, which is characterized in that including following step
Suddenly：
Step S01, providing one has the substrate of dielectric layer, and a through-hole is formed on the dielectric layer；
Step S02 grows graphene barrier layer and ruthenium metal barrier successively in the through-hole；
Step S03 forms the first photoresist in the through-hole, and removes graphene barrier layer upper surface using it as mask
Ruthenium metal barrier；
Step S04 removes first photoresist, and cleans substrate surface；
Step S05 fills metallic copper using selective copper electroplating technology in the through-hole, and the upper surface of the metallic copper with
The upper surface of the dielectric layer is concordant；
Step S06 forms second photoresist equal with its width in the upper surface of the metallic copper, and with second photoetching
Glue removes the graphene barrier layer of the dielectric layer upper surface for mask；
Step S07 removes second photoresist, forms copper interconnection structure.
4. the manufacturing method of copper interconnection structure according to claim 3, which is characterized in that in step S02, using low temperature
It learns vapour deposition process, atomic vapor deposition method, SiC thermal decomposition methods or oxidation-reduction method and forms the graphene barrier layer, it is described
The thickness on graphene barrier layer is 0.34-3.4nm.
5. the manufacturing method of copper interconnection structure according to claim 3, which is characterized in that in step S02, using atom gas
Phase sedimentation forms the ruthenium metal barrier, and the thickness of the ruthenium metal barrier is 1-3nm.
6. the manufacturing method of copper interconnection structure according to claim 3, which is characterized in that in step S03, carved using wet method
Etching technique or the ruthenium metal barrier of reactive ion etching process removal graphene barrier layer upper surface.
7. the manufacturing method of copper interconnection structure according to claim 6, which is characterized in that removed using wet-etching technology
The etching liquid of the ruthenium metal barrier is ammonium ceric nitrate and mixed liquor, the HNO of nitric acid3And NH4Mixed liquor, the H of F2SO4With
H2O2Mixed liquor, dilute HF it is one or more.
8. the manufacturing method of copper interconnection structure according to claim 6, which is characterized in that using reactive ion etching process
The etching gas for removing the ruthenium metal barrier is containing one or more in F, Cl or XeF gas.
9. according to the manufacturing method of any copper interconnection structure of claim 3~8, which is characterized in that in step S06, adopt
The etching gas that the graphene barrier layer is removed with dry etch process is H2、O2Or CxFyGas it is one or more.
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| US10847463B2 (en) * | 2017-08-22 | 2020-11-24 | Applied Materials, Inc. | Seed layers for copper interconnects |
| CN107993928B (en) * | 2017-11-20 | 2020-05-12 | 长江存储科技有限责任公司 | Method for inhibiting copper electromigration in wafer hybrid bonding |
| JP2021534572A (en) * | 2018-08-11 | 2021-12-09 | アプライド マテリアルズ インコーポレイテッドApplied Materials, Incorporated | Graphene diffusion barrier |
| CN110759334B (en) * | 2019-12-06 | 2023-07-28 | 上海集成电路研发中心有限公司 | Graphene channel structure and manufacturing method thereof |
| CN116153861B (en) * | 2023-04-19 | 2023-07-11 | 武汉楚兴技术有限公司 | Semiconductor structure and preparation method |
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| CN103378064A (en) * | 2012-04-28 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection structure and manufacturing method thereof |
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| US6967155B2 (en) * | 2003-07-11 | 2005-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adhesion of copper and etch stop layer for copper alloy |
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| US6348731B1 (en) * | 1997-05-30 | 2002-02-19 | International Business Machines Corporation | Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same |
| CN102593097A (en) * | 2012-02-27 | 2012-07-18 | 北京大学 | Integrated circuit metal interconnecting structure and manufacture method thereof |
| CN103378064A (en) * | 2012-04-28 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Metal interconnection structure and manufacturing method thereof |
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