CN105336797B - Thin film semiconductor's photoelectric device with veining front surface and/or back surface - Google Patents
Thin film semiconductor's photoelectric device with veining front surface and/or back surface Download PDFInfo
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- CN105336797B CN105336797B CN201510475349.5A CN201510475349A CN105336797B CN 105336797 B CN105336797 B CN 105336797B CN 201510475349 A CN201510475349 A CN 201510475349A CN 105336797 B CN105336797 B CN 105336797B
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- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 9
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/52—PV systems with concentrators
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The present invention relates to thin film semiconductor's photoelectric device with veining front surface and/or back surface.A kind of method for being used to provide veining layer in the opto-electronic device is disclosed.Method is included template layer deposition on the first layer.Template layer has obvious inhomogeneities on thickness or in composition or on both, including forms one or more islands to provide the possibility of at least one texturizing surfaces of island nitride layer.Method is further included is exposed to etch process to produce or change at least one texturizing surfaces by template layer and first layer.At least one texturizing surfaces changed cause light scattering in operation.
Description
Cross reference to related applications
The application is in " TEXTURING A LAYER IN AN submitting, entitled on January 19th, 2012
The United States Patent (USP) Shen of OPTOELECTRONIC DEVICE FOR IMPROVED ANGLE RANDOMIZATION OF LIGHT "
Part continuation application that please be the 13/354th, No. 175, the U.S. Patent application are hereby incorporated by reference in its entirety by quoting.
Technical field
Embodiment of the present invention is usually directed to optoelectronic semiconductor component (such as photovoltaic device including solar cell),
And the method for manufacturing such devices.
Background technology
The purposes of photoelectric device such as photovoltaic device and light emitting diode (LED) becomes wide, because energy efficiency
Importance increase.In photovoltaic device such as solar cell, the knot of solar cell absorbs photon to produce electron hole pair,
The internal electric field that the electron hole pair is tied is separated to produce voltage, so as to convert light energy into electric energy.Preferable photovoltaic (PV)
The absorber layers of device will absorb the positive all photons impinged upon towards the PV devices of light source, because open-circuit voltage (Voc)
Or short circuit current flow (Isc) proportional to luminous intensity.However, some loss mechanisms often interfere with the absorber layers of PV devices, the suction
Acceptor layer is absorbed to positive all light up to device.For example, some photons can be any without producing to pass through absorber layers
Electron hole pair and therefore from not contributeing to produce electricl energy by device.In other cases, the semiconductor layer of PV devices can
To be smooth and therefore can reflect the major part hit in photon, these photons are prevented in order to avoid reaching absorber layers.
Accordingly, there exist to the photoelectric device with increased efficiency and for subtracting compared with conventional photoelectric device manufacture
Few cost and larger flexibility manufacture the demand of the method for such photoelectric device.
The content of the invention
The method of the open veining layer being used to provide in photoelectric device.Method includes template layer being deposited on first layer
On.Template layer is obvious non-uniform on thickness or in composition, including forms one or more islands to provide island
The possibility of at least one texturizing surfaces of nitride layer.Method is further included is exposed to etch process to produce by template layer and first layer
Life changes at least one texturizing surfaces.At least one texturizing surfaces cause light scattering in operation.
The open method for being used to provide photoelectric device.Method includes deposit absorbent body layer and deposition emitter layer.Method is also
Including the first layer of the first material is deposited in emitter layer and absorber layers.In addition, method is included the mould of the second material
Flaggy deposits on the first layer.Method is further included is exposed to etch process to produce or change at least one by template layer and first layer
A texturizing surfaces.At least one texturizing surfaces cause light scattering in operation.Finally, method includes existing dielectric layer deposition
In island nitride layer and by deposition of metal on the dielectric layer.
The open method for being used to provide photoelectric device.Method includes deposition emitter layer and deposit absorbent body layer.Method is also
Including the first layer of the first material is deposited in emitter layer and absorber layers.In addition, method is included the mould of the second material
Flaggy deposits on the first layer.Method is further included is exposed to etch process to produce or change at least one by template layer and first layer
A texturizing surfaces.At least one texturizing surfaces cause light scattering in operation.Finally, method includes depositing anti-reflecting layer
In island nitride layer.
Brief description of the drawings
Therefore attached drawing only some embodiments of illustration and is not to be construed as limiting scope.
Figure 1A -1C show the top-down view of the template island nitride layer on first layer；
Fig. 2 describes the viewgraph of cross-section of the photovoltaic device according to some embodiments described herein；
Fig. 3 A, 3B, 3C, 3D, 3E, 3F, 3G and 3H depiction 1 photovoltaic device viewgraph of cross-section, wherein island nitride layer
It is deposited on the base layer；
The viewgraph of cross-section of the photovoltaic device of Fig. 4 depictions 3, wherein semiconductor contact layer and dielectric layer have been deposited over
In island nitride layer；
The viewgraph of cross-section of the photovoltaic device of Fig. 5 depictions 4, wherein forming hole in the dielectric layer；
Fig. 6 A and 6B describe the top view of the different embodiments of mask, and the mask can be used to form in Figure 5
Hole in the dielectric layer shown；
The viewgraph of cross-section of the photovoltaic device of Fig. 7 depictions 5, wherein metal layer are deposited on the dielectric layer；
Fig. 8 is depicted in the horizontal stroke of an embodiment of the photovoltaic cell produced after stripping technology by the photovoltaic device of Fig. 7
Section view；
Fig. 9 describes the viewgraph of cross-section of another embodiment of the photovoltaic cell produced by the photovoltaic device of Fig. 3 A；
Figure 10 describes the viewgraph of cross-section of the photovoltaic cell of the veining layer scattering light on the back side that illustration passes through device；
Figure 11 describes photovoltaic device according to some embodiments described herein, providing front lighting capture veining layer
Viewgraph of cross-section；
The viewgraph of cross-section of the photovoltaic device of Figure 12 depictions 11, wherein island nitride layer are deposited on the base layer；
And
The viewgraph of cross-section of the photovoltaic device of Figure 13 depictions 12, its middle level have been deposited in island nitride layer.
Embodiment
Embodiment of the present invention is usually directed to photoelectric device and technique, and relates more particularly to include one or more
Texture the optoelectronic semiconductor component of layer and the manufacturing process for forming such photoelectric device.
Herein, layer can be described as being deposited on other one or more layers.This term marker can be by
The top of other layers is deposited directly to, or can indicate that one or more other layers can be deposited in certain embodiments
Between layer and other layers.In addition, other layers can be arranged in any order.
Term template layer herein is defined as instruction to be had significantly on thickness or in composition or on both
The layer of inhomogeneities.This is so large that template layer is the possibility of multiple separated islands including thickness offset.
When template layer and the layer under template layer are exposed to etchant or etch process, texturizing surfaces are generated or change.
Texturizing surfaces can cause light scattering, this can improve the light capture in photoelectric device.
Term island refers to material layer discontinuous in the plane, this allows etchant potentially to reach in lower section
Layer.Island nitride layer can form multiple obvious unconnected regions (Figure 1A), or can fully be connected but (schemed with gap
1B), or can be both combinations (Fig. 1 C).Each template island nitride layer shown on first layer 112 in these figures
152 top-down view.These layers are described in more detail herein.
Embodiment disclosed herein is related to be captured for larger device efficiency using the light of veining layer.
Fig. 2 illustrations are suitable for an embodiment party of the photovoltaic device 100 being used together with the embodiments described herein
The viewgraph of cross-section of case.Although the embodiments herein is related to photovoltaic device, the feature of description may be applied to other photoelectricity
Semiconductor devices such as LED, such as produced with scattering the light in device so as to provide increased or more efficiently light.
Device 100 includes what is coupled by being arranged in ELO releasing layers therebetween or sacrifice layer 104 with growing wafer 101
Battery 120.Multiple epitaxial materials containing different constituents are deposited in photovoltaic device 100.Multiple epitaxial materials
It can be grown or otherwise be formed by the appropriate method for semiconductor growing.Battery 120 can for example be had
There is the battery based on GaAs of the layer made of group iii-v material.Group iii-v material is the film of epitaxially grown layer.
In certain embodiments, epitaxially grown layer can pass through the growth regulation III- during such as Seedling height speed gas-phase deposition
V races materials is formed.Seedling height speed depositing operation allows the growth rate more than 5 μm/hr, than such as from about 10 μm/hr or bigger,
Or up to about 100 μm/hr or bigger.Seedling height speed technique, which is included in system of processing, heats wafer to about 550 DEG C or bigger
Depositing temperature, wafer is exposed to the deposition gases comprising precursor, for example gallium precursor gases and deposited for GaAs
The arsenic hydride of technique and the layer comprising GaAs is deposited on wafer.Deposition gases can include group V precursor, such as
Arsenic hydride, hydrogen phosphide or ammonia.
As described herein, can be polytype heavy for depositing or being formed the depositing operation of group iii-v material
Product carries out in room.For example, can be used to growing, deposit or otherwise be formed group iii-v material it is a kind of continuously into
Expect settling chamber in the commonly assigned U.S. Patent Application No. all submitted on May 29th, 2,009 12/475,131 and the 12/th
Described in 475, No. 169, they are hereby incorporated by reference in its entirety by quoting.
Available layer and some examples of the method for forming such layer are on November 3rd, 2010 in device 100
Disclosed in the Co-pending U.S. Patent Application the 12/939th, 077 of submission, and it is integrally incorporated this by quoting with it
Text.
In certain embodiments, one or more cushions 102 can be formed on growth wafer 101 to start shape
Into photovoltaic device 100.Growth wafer 101 can include such as N-shaped or semi insulating material, and can include and one or more
The same or similar material of cushion then deposited.It can include p-type material in other embodiments.
Sacrifice layer (ELO releasing layers) 104 can be deposited in growth 102 (if present) of wafer 101 or cushion.It is sacrificial
Domestic animal layer 104 can include appropriate material, such as aluminium arsenide (AlAs) or aluminium arsenide alloy, and be used to form in electricity
The lattice structure of the layer included in pond 120, and be then etched and be removed during ELO techniques.
The layer of photovoltaic cell 120 can be deposited on sacrifice layer 104, it connects before can including in certain embodiments
Absorber layers 108 that contact layer 105, front window 106, neighbouring front window 106 are formed, emitter layer 110 and for veining
Basalis 112.Preceding semiconductor contact layer 105 or boundary layer can be deposited on sacrifice layer 104.Preceding contact layer 105 is some
It can be the layer of n doping in embodiment, include group iii-v material, such as GaAs.
Front window 106, also referred to as passivation layer, can form on sacrifice layer 104 on the substrate 101, or if it does,
Formed on optional contact layer 105.Front window 106 can be transparent to allow incident photon to pass through in battery 120 just
Front window 106 on face is to the layer below other.In certain embodiments, front window 106 can include group iii-v material.
Absorber layers 108 can be formed in Window layer 106.Absorber layers 108 can include any appropriate Section III-V
Compound semiconductor, such as GaAs (GaAs).In certain embodiments, absorber layers 108 can be monocrystalline and can
To be that n is adulterated.Different embodiments can provide different doping concentrations, for example scope is from about 1 × 1016cm-3To about 1
×1019cm-3。
In certain embodiments, emitter layer 110 can be formed in absorber layers 108.In certain embodiments,
Emitter layer 110 can be that p adulterates (such as p+Doping).Emitter layer 110 can include any appropriate group iii-v
Compound semiconductor and can be monocrystalline.For example, the doping concentration of the emitter layer 110 of severe p doping can from about 1 ×
1017cm-3To about 1 × 1020cm-3In the range of.In certain embodiments, emitter layer 110 can be with 108 shape of absorber layers
Into hetero-junctions.
In certain embodiments, the contact with p-type emitter layer 110 of n-type absorber layer 108, which produces, is used to absorb photon
P-n junction.Other embodiments can be included among the one or more between absorber layers 108 and emitter layer 110
Layer.Other embodiments can use substrate/absorber layers of p doping and the back of the body/emitter layer, and/or others of n doping
The layer of p/n doping, to replace the layer that the n/p in description herein is adulterated.
Basalis 112 for veining can optionally be deposited over emitter layer 110.Basalis 112 can carry
For first layer, and can be by contributing to island to be formed with the constituent component different from template layer, template layer is sunk
Product is used to texture purpose on the first layer.In certain embodiments, basalis 112 can be that monocrystalline and p are adulterated
And with about 5 × 1017cm-3To about 2 × 1019cm-3Scope in doping concentration.Basalis 112 and template layer are below
In be described in more detail.In certain other embodiments, basalis 112 is not included in device 100.For example, template
Layer (described below) can be deposited in emitter layer 110 or in absorber layers 108 (on emitter layer).
Fig. 3 A are the cross sections according to the photovoltaic device 100 of an embodiment of the texturizing surfaces for being used as back reflector
Figure, the photovoltaic device 100 are included in deposition template layer 140 on basalis 112.Template layer 140 has inconsistent thickness, it can
To cause light reflection and the light scattering in device, so as to increase light capture.
Used template layer in various embodiments can be different.In one embodiment, template layer has aobvious
The thickness inconsistency of work, includes the possibility of multiple and different islands of mould material.In another embodiment, template
Layer has the inconsistency of composition, but can have or can not have significant thickness inconsistency.
When the template layer in device and other layers are exposed to etchant or etching process, template layer can not be by significantly
Etching, or (but the speed to be etched than the first layer that template layer is deposited thereon slow speed) can be etched, or can
With with the speed being etched with the first layer that template layer is deposited thereon is suitable or is deposited thereon more than template layer first layer
The speed for the speed being etched is etched.Thus, template layer can (but need not) forming or changing the mistake of texturizing surfaces
It is now completely etched away in journey.Selectively, template layer still can be partially or entirely presented after etching process, but can be with
Partially or entirely removed in the subsequent processing steps before the manufacture of photoelectric device is completed.
Template layer can have inconsistent composition.The different piece of template layer with different materials composition can be sudden and violent
Etched when being exposed to etchant or etching process with different speed.By this way, template layer can be during the process of etching
Produce thickness inconsistency or increase its thickness inconsistency, even if thickness is consistent before etching.
The template layer with inconsistent thickness can be commonly known as island nitride layer before etching.Island growth can be down to
Partially produced due to the strain between different materials, which is caused by the lattice mismatch between material.Selectively,
Island growth can be very thin due to island nitride layer and not form continuous layer and produce.Selectively, island growth can
To be produced due to dynamic etch during deposition process itself.
For example, in some embodiments, such as the example embodiment shown in figure 3 a, Stranski-
Krastanov techniques can be used for forming template layer 140.The technique is related to deposition certain material, which is initially formed template
The wet layer 142 (it can include one or more single layers) of layer material, then forms the island of identical material in wet layer 142
Shape thing 144.In other embodiments, other kinds of island growth technique can be used.For example, Fig. 3 B show use
The formation of the island of Volmer-Weber techniques, it can not provide the wet of the template layer material of island growth on it
Layer, as described below.
Template layer 140 can include semi-conducting material, and can be the basalis being deposited thereon with template layer 140
The different material of 112 material.In some embodiments, template layer 140 can be the material bigger with than basalis 112
Band gap material.In some instances, template layer 140 can include phosphorus, gallium, aluminium, indium, arsenic, antimony, nitrogen, its derivative and/or
It is combined.For example, in some embodiments, basalis 112 can include GaAs (GaAs) or aluminum gallium arsenide (AlGaAs), and
And template layer 140 can include indium gallium arsenic (InGaAs) or gallium arsenic antimony (GaAsSb).In other embodiments, basalis 112
It can include aluminum gallium arsenide (AlGaAs), and template layer 140 can include gallium phosphide (GaP).In other embodiments, substrate
Layer 112 can include indium arsenide (InAs), and template layer 140 can include indium arsenic antimony (InAsSb).In yet other reality
Apply in scheme, basalis 112 can include gallium indium phosphorus (GaInP), and template layer 140 can include gallium phosphide (GaP) or phosphorus
Change aluminium (AlP).In yet other embodiments, basalis 112 can include indium phosphide (InP), and template layer 140 can
With including indium phosphorus antimony (InPSb).In some embodiments, template layer can include gallium indium nitrogen arsenic (GaInNAs), gallium nitrogen arsenic
(GaNAs), gallium arsenic phosphide (GaAsP), aluminum gallium arsenide phosphorus (AlGaAsP) or gallium aluminium phosphorus (AlGaP).Any in these embodiments
It is a, derivative and/or the combination of these materials can be used.The material being doped can be used for template layer by some embodiments
140；Adulterate, and can have in about 1x1017cm for example, material can be p-3To about 2x1019cm-3Scope in (ratio
Such as from about 1x1018cm-3) doping concentration.
In some embodiments, template layer 140 includes the folding with increase or the ability for maximizing scattering or reflected light
Penetrate the material of rate (n) and absorbability (k).For example, template layer 140 can include the transparent material for allowing light to pass through template layer.Such as
Term as used herein " transparent " refers to the negligible uptake in the wave-length coverage of photoelectric device operation.For example,
In some embodiments, template layer 140 can have the refractive index in the scope of about 1 to about 3.5.In addition, in some realities
Apply in scheme, the material of template layer 140 can have about 0 to about 1x10-2Scope in, than such as from about 1x10-3Or about 1x10-4
Absorbability (k).In some embodiments, template layer 140 can include multiple transparent layers.
In some embodiments, with used deposition parameter phase during previous the layer such as deposition of basalis 112
Than the various parameters of depositing operation can be varied or adjusted, for the deposition of template layer 140.For example, the temperature of depositing operation
Degree, pressure, deposition gases and/or growth rate can be changed, as described in more detail below.
In figure 3 a, wet layer 142 and island 144 are deposited over substrate using Stranski-Krastanov techniques
On layer 112.Wet layer includes the complete film for the absorbate being accumulated in substrate, and wherein substrate is the base in described example
Bottom 112.Wet layer 142 can be grown using the material of deposition, further thereafter to deposit untill realizing specific thicknesses
One or more islands 144 are caused to grow.Therefore, island 144 includes the material identical with wet layer 142.Once wet layer 142
Critical thickness is had been carried out in Stranski-Krastanov techniques (such as by wet layer 144 and the chemical property of basalis 112
Determined with physical property), then continued growth of the absorbate on basalis 112 is tired in wet layer 142 by island 144
Product occurs, which is attributed to strain or stretching in wet layer material.
Island 144 provides the texturizing surfaces of island nitride layer 140.The growth of island 144 is controlled to increase or maximum
Change the angle random for the light for being radiated on template layer 140 or being propagated through template layer 140.This angle randomization of light can be with
By adjusting or the different parameters (and thus cause growth to be adjusted or customize) of growth conditions of customization island 144 cause
Island obtains particular characteristics and increases or maximize.Some in different parameters include deposition for the material of template layer
Amount, depositing temperature, deposition pressure, the growth rate of template layer material, the V group element that is flowed in deposition gases and influence base
The composition of the mould material of lattice mismatch between bottom and template layer material.The amount of the template layer material deposited can influence
Island is grown.For example, the larger quantities of the material deposited is tended to encourage the growth of Stranski-Krastanov islands
(will be described in further detail below) is grown more than Volmer-Weber islands.
Another parameter that can be selected to the growth of control island 144 is included in the depositing operation of island nitride layer 140
The temperature that period provides.For example, temperature higher can be made to produce the island 144 with large-size.For depositing template
Some examples of the temperature range of layer 140 include about 600 DEG C to about 900 DEG C.
Another parameter of growth for controlling island 144 is the pressure that is provided during the deposition of template layer 140.Example
Such as, pressure bigger can be made to produce island 144 with a smaller size.It can be used for the pressure model for depositing template layer 140
Some examples enclosed include about 50 supports to about 600 supports.
Another parameter is the growth rate of template layer 140, it can be controlled to the characteristic for influencing veining layer.For example,
In some embodiments using Stranski-Krastanov techniques, the growth rate of template layer 140 can be controlled as
Than in the growth rate using the standard before Stranski-Krastanov techniques faster.In one example, can basis
Such as growth is controlled above with respect to the Seedling height speed of described other layers for being used to deposit photoelectric device 100 of epitaxially grown layer
Speed.In other embodiments, island 144 can grow slower, if for example, in some embodiments, to island
The more preferable control of the special characteristic of shape thing is desired, such as facet.In some embodiments, about 5 μ can be will be greater than
Growth rate scope when m/ is small is used for template layer 140.
It can be the V group element flowed in the deposition gases provided during deposition with controlled another parameter.For example, with
Can have the Group V precursor and Group III precursor of certain ratio in the deposition gases for forming template layer 140.In some embodiments
In, V group element is hydrogen phosphide.The flow rate ratio can be controlled so that template growth is adjusted to desired characteristic.In general, for example,
The ratio of phosphatization hydrogen flowrate can be reduced relative to the flow rate ratio for previous sedimentary (for example, basalis 112)
(that is, the ratio provided is low), to promote island to be formed.In some embodiments, deposition gases can have about 50:
1 to about 300:Hydrogen phosphide/Group III precursor in 1 scope.
Another parameter that can be selected to the growth of control island 144 is the institute in basalis 112 and template layer 140
The composition (type) of the material used.For example, can be based on the material of contact layer 112 lattice parameter and template layer 140 material
The lattice parameter of material selects material.In general, the growth part of island 144 depend on basalis 112 and template layer 140 it
Between lattice mismatch.For example, in Stanski-Krastanov techniques, the larger mismatch between lattice parameter causes wet layer 142
Less critical thickness, at critical thickness, island growth takes place.It can select the crystalline substance of the material of basalis 112
The lattice parameter of the material of lattice parameter and template layer 140, to provide the desired growth pattern of island 144 or feature, such as
The form of island, island start point of growth etc. after wet layer deposition.In some example embodiments, basalis
The lattice mismatch in the scope of about 3% to about 20% can be used between 112 material and the material of template layer 140.One
In a little embodiments, template layer 140 can be the material of the band gap of the material bigger with than basalis 112.
Island 144 can be controlled to have specific or common physical characteristic, such as regular or irregular shape
Shape, size and/or interval.For example, can be by controlling the growth rate of wet layer and/or island, controlling critical thickness, use
Textured or figuratum basalis 112 etc. controls the geometry of island and size.
In addition, some or all of physical characteristic (for example, size, shape and/or interval) of island 144 can have
There are change or the scrambling of specific degrees, with the island at interval that provide different, non-uniform shape and non-uniform
144.Compared with uniform texture, the texture usually enhancing of this change and randomization dissipates the light received by template layer at random
The ability being mapped in absorbed layer 108.
Because the texturizing surfaces including template layer 140 are formed as the scattering layer of non-interactive, and utilize and use island
The shape of deposition process shaping is grown, the scattering layer of the non-interactive has features not provided in absorbed layer or emission layer；And
And because largely change, scrambling or randomness are preferable in the formation of island 144, in some implementations
In scheme, the semiconductor of high-quality is not required as the material of template layer 140.With island growth technique such as
The previously used of Stranski-Krastanov techniques is compared, this can allow some reductions of the cost of material and/or processing,
In Stranski-Krastanov techniques, the absorption of the island that is arranged accurately size and is accurately spaced in device
Growth (for example, for adjusting the transmitting of the wavelength in semiconductor laser) in layer.In addition, in some embodiments, quality compared with
The use of secondary semiconductor can allow the higher growth rate of template layer 140.
Fig. 3 B are the cross-sectional views of photovoltaic device 100', and photovoltaic device 100' includes being suitable for some implementations disclosed herein
The deposit of the template layer 150 of scheme, wherein island are formed using different island growth techniques.In figure 3b,
Volmer-Weber growth techniques have replaced the Stranski-Krastanov techniques in the example for Fig. 3 A to be used for island
Thing is grown.
Template layer 150 includes island 152, it by template layer material by being deposited on (or the as above institute of basalis 112
Other layers in the embodiment without basalis 112 for stating) on formed.It is different from the template layer 140 of Fig. 3 A, example
Template layer 150 is not included in the wet layer deposited before island is formed.Island 152 is due on the surface of basalis 112
The atom of atom and island material have than its with the atom on the surface of basalis stronger interaction and formed.This causes
The cluster of material or island 152 is formed as island material deposits.Therefore, some or all islands 152 can be direct
Formed on the surface of basalis 112, and/or some or all islands 152 can have in 112 surface of basalis and island
The layer of the island material formed between thing 152.Compared with Stranski-Krastanov described above is grown, Volmer-
The growth of Weber islands usually occurs at lattice mismatch higher between template layer and basalis and in the relatively low of template layer
On thickness.For example, in some embodiments, the growth of Volmer-Weber islands can occur about 5 angstroms in template layer with
Under thickness at.
Template layer 150 includes semi-conducting material, and is the material for the basalis 112 being deposited thereon with template layer 150
Different materials.For example, in some embodiments, template layer 150 can include phosphorus, gallium, aluminium, indium, arsenic, antimony, nitrogen, its derivative
Thing and/or its combination.In some embodiments, basalis 112 and template layer 150 can described above be used for template layer
The combination of the material of 140 material or derivative.Some embodiments can use the material being doped to be used for template layer 150.
Similarly, as explained above with respect to the embodiment of Fig. 3 A, the growth of island 152 can be by adjusting heavy
The one or more different parameters of product process control, including parameters described above.
In another embodiment, template layer has the inconsistency of composition, but can have or can not have notable
Thickness inconsistency.Fig. 3 C are the cross-sectional views for the exemplary photovoltaic device 100 " for showing this embodiment.Template layer 155
Formed including two or more material, the first material is shown as unshadowed area 156 and 157, and second of material
Material is shown as shadow region 158.Fig. 3 C are intended to only show an example, and are not intended to be limited to the scope of the present invention.Especially,
It is more than two kinds of chemical compositions it is possible that existing, 156 and 157 there is identical or different material to form, and 156 be connection
Layer rather than the island disconnected as depicted.
So, the embodiment with Fig. 3 C of the inconsistency of composition is easily affected by etching, which can be with not
Same speed etching layer 156 and 158.In one embodiment, when layer is exposed to etchant or etching process, layer 158 compares
Layer 156 is etched more quickly so that after the etching, the structure of reservation is similar to the structure of Fig. 3 B.Then, from Fig. 3 C's
Layer 156 becomes the island nitride layer 152 for being equal to Fig. 3 B.
In some example embodiments, template layer 155 can include two kinds of one or more semiconductors or more than two
The different composition of kind, such as aluminum gallium arsenide (AlGaAs) (for example, there is different amounts of Al and Ga contents) or AlGaInP
(AlGaInP) (for example, there is different amounts of Al, Ga and/or In content) or other materials.
In order to further change island 152 and provide more coarse texture, etching can be after island growth
Fig. 3 D optional embodiment 100 " ' as shown in carried out.Island, which grows and etches both parameters, to be controlled
The form and size of texture, so as to maximize benefit of the texture to device performance.The change of island 152 can include changing line
The physical size on physics and chemistry surface, wherein the physical size changed includes the change of one or more of texturizing surfaces island
Shape or texturizing surfaces in multiple islands between change distance.In various embodiments, etching can be
One or more in chemical etching, laser-induced thermal etching, plasma etching or ion(ic) etching or similar etching.
In another embodiment, after layer 158 is removed, layer 156 provides island template and is used to further etch.
In another embodiment, layer 140 is partially etched, to produce island template (Fig. 3 E).After the etching,
The remainder of layer 140 is marked as 146.Further it is etched in layer 112 and produces texture (Fig. 3 F).Fig. 3 F are shown in which pair
The etchant that layer 112 is etched has layer 146 a kind of embodiment of insignificant influence.In yet another embodiment,
The etchant being etched to layer 112 simultaneously effective etching layer 146 (Fig. 3 G).It is also possible that layer 112 etching it
Layer 146 no longer exists afterwards.
In another embodiment (Fig. 3 H), etching is not limited to layer 112 and those layers above layer 112, but also expands
Open up layer 110.No matter layer 146 or layer 152 or layer 156 are island nitride layer, this can be applicable in.
In Fig. 4, the photoelectric device 100 of Fig. 3 B by optional semiconductor contact layer 160 further by being deposited on template
On layer 140,150 or 155, dielectric layer 162 is next deposited on contact layer (if present) or is deposited on template layer
140th, formed on 150 or 155 (if if contact layer 160 is not present).Template is shown in the exemplifying drawings being described below
Layer 140, wherein template layer 150 or 155 can be used instead of template layer 140 as required.Those of ordinary skill in the art hold
Change places, it is realized that the photoelectric device 100 ' of Fig. 3 B can further be formed in the same fashion and it is by the present invention's
In spirit and scope.In addition, the description below device 100 is equally applicable to the device 100 " -100 of Fig. 3 A-3H " " " '.Half
Conductor contact layer 160 can be deposited in some embodiments with for example on template layer provide calotte (cap) and with
Other layers are allowed to be more easily deposited on template layer, and/or to be provided preferably for the electric charge carrier movement in device 100
Ohmic contact.In some example embodiments, contact layer 160 can include semiconductor (such as GaAs (GaAs) (for example,
There is less thickness since it can be less opaque), aluminum gallium arsenide (AlGaAs) (for example, because it can be more
It is transparent and there is larger thickness)) or other materials, and can be p-doping in some embodiments, it has
Thickness in the range of about 5nm to about 500nm.
Dielectric layer 162 can be deposited over contact layer 160 and/or template layer 140,150 or 155 in some embodiments
On, and can promote to hit or travel across the reflection or scattering of the light of template layer 140,150 or 155.In some instances,
Dielectric layer 162 can include insulating materials (such as the titanium dioxide for example with the dielectric constant between template semi-conducting material and 1
Silicon (SiO2)).In some embodiments, dielectric layer 162 can be with the light for being intended to scatter by texturing layer four/
The thickness of one wavelength (or multiple quarter-waves), and allow than the reflection using only metal layer (described below) bigger
Ability.In some embodiments, dielectric layer can have the refractive index n lower than template layer 140,150 or 155.
Therefore, island 144 or 152 can form recess in the layer being deposited on template layer so that be reflected at back
In device embodiment, the light advanced of material through template layer 140,150 or 155 hits the surface of recess and from the table of recess
Face is reflect off (for example, the surface scattering for passing through recess).Some examples are illustrated in greater detail on Figure 10.
In some other embodiments, different materials can substitute dielectric layer 162 be deposited on semiconductor layer 160 or
On template layer 140,150 or 155 (if contact layer 160 is not present).For example, in some embodiments, electrically conducting transparent
Oxide (TCO) layer can be deposited to provide the albedo of the raising similar to dielectric layer, and also for template layer and is set
The electric charge carrier put between the conductive metal layer on tco layer provides conductive path.In these embodiments, as figure
162 described hole of dielectric layer in 5 may not necessarily be formed in tco layer.In some embodiments, high resistivity is saturating
Bright (HRT) layer can also be arranged on tco layer and semiconductor layer (such as template layer 140/150/155, emission layer 110 or absorbed layer
108) between.HRT layers can reduce shunting of the electric charge carrier through the pin hole (pin hole) in semi-conducting material.
Fig. 5 is shown had been formed in hole in dielectric layer 162 after to allow the device of the conductive contact through dielectric layer 162
Part 100.In the embodiment with semiconductor contact layer 160, such as the example embodiment shown in Fig. 5, from dielectric layer
162 surface forms hole 164 to semiconductor contact layer 160 through dielectric layer 162.In its without semiconductor contact layer 160
In his embodiment, hole 164 can be formed from the surface of dielectric layer to template layer 140,150 or 155.
In some embodiments, it is etched by using etch process to form hole 164.Etch process can use
Any available suitable technology carries out.
In some example embodiments, the certain patterns in the hole 164 in dielectric layer 162 can pass through mask (such as light
Photoresist/etching mask) provide.Fig. 6 A show the top view of the mask pattern 165 of the providing holes 164 in dielectric layer 162
One example, its mesoporous are the circular holes 166 (being approximate circle in the top view of Fig. 6 A) for having near circular cross section.Figure
6B shows another example of the top view of the mask pattern 167 of the providing holes 164 in dielectric layer 162, its mesoporous is line style
Groove.As shown, one or more grooves 168 can intersect with other one or more grooves 169.As shown,
Groove can be positioned to it is approx parallel to each other and/or vertical, or in other embodiments can with various other angles into
Row placement.Non-linearity or irregular groove can be used in other embodiments.
In the figure 7, photoelectric device 100 has been further advanced by is deposited on dielectric layer 162 by reflectivity back-metal layer 170
An example upper, that set veining layer 180 is formed.Metal layer 170 includes the metal of effective reflected light.For example, at some
In embodiment, metal layer 170 can include gold, silver, copper or other reflective metals, they derivative, and/or they
Combination.The deposition of metal layer 170 provides the approximate flat surface opposite with template layer 140,150 or 155.In some embodiment party
In formula, layer 140,150 or 155 is etched before follow-up procedure of processing.In some embodiments, metal layer
170 can have the average thickness in the range of about 70nm to about 10 μm.The material of metal layer 170 is also deposited in hole 164,
So that conductive contact is formed between metal layer 170 and semiconductor contact layer 160 or is formed in metal layer 170 and template layer
140th, between 150 or 155 (if contact layer 160 is not present).In some other embodiments, metal layer 170 can be sunk
Product is on template layer 140,150 or 155, without making dielectric layer 162 and/or semiconductor contact layer 160 be deposited on metal layer and mould
Between flaggy.
In fig. 8, after some layers shown in the preceding step during stripping technology has eliminated Fig. 2-7, photovoltaic electric
Pond 120 is shown as being reversed direction.When epitaxial layer has been formed as being used for PV devices 100 as shown in Figure 7, photovoltaic device
Some layers (such as front contact layer 105, Window layer 106, absorbed layer 108, emission layer 110 and veining layer 180) in part 100
It can be separated during ELO techniques with substrate 101 and any cushion 102.
In one example, photovoltaic device 100 can be exposed to etching solution to etch sacrifice layer 104 and in extension
Battery 120 is set to be separated with growth wafer 101 during peeling off (ELO) technique.Fig. 8 shows the battery in its obtained orientation
120, the front portion of wherein battery 120 is oriented at the top of battery, and at the top of battery, light hits and enters battery.Therefore, line
Physics and chemistry layer 180 is anterior more anti-far from back is served as than the p-n junction formed by absorbed layer and emission layer away from battery 120
Emitter.Once being separated, then battery 120 can be processed further to form a variety of photovoltaic devices (including photovoltaic cell
And module).For example, hard contact 190 can be deposited on front contact layer 105.
Fig. 9 shows the cross-sectional view of the selectable embodiment 120 ' of photovoltaic cell 120, its mesoporous is not formed at Jie
In electric layer 162, and conductive contact is deposited over below dielectric layer 162.In this example, during layer deposits, some are conductive
Contact 194 can be deposited on semiconductor contact layer 160 ', or (if there is no connecing on template layer 140 '/150 '/155 '
If contact layer 160 ').In some embodiments, layer 140 ', 150 ' or 155 ' carries out before follow-up procedure of processing
Etching.Dielectric layer 162 ' is deposited on contact 194 and semiconductor contact layer 160 '.Metal contact layer 170 ' is deposited over dielectric
On layer 162 '.Then, device is flipped to the direction shown in Fig. 9 after ELO or process similarity.
Conductive contact 194 is illustrated with cross section, and can be extended in the plane of Fig. 9 or be extended from the plane of Fig. 9
Out to one or more position (not shown) for reaching metal contact layer 170 ' through dielectric layer 162 ' by route.For example,
In some embodiments, contact 194 can be configured to and 168 and 169 phase of the groove of the mask pattern 167 shown in Fig. 6 B
Seemingly, wherein contact 194 extends on the region of battery 120 ' and is connected to one or more connecting nodes (for example, phase
It is similar to the node 196 shown in Fig. 6 B), one or more connecting node is extended by the covering part of dielectric layer 162 '
To metal contact layer 170 ', or extend to the exterior position of battery 120 '.There is provided each embodiment of hard contact 194 can keep away
Exempt to etch the hole in dielectric layer, procedure of processing is saved in battery 120 ' is formed.
Figure 10 shows the figure of the part 200 of the photovoltaic cell 120 of pictorial image 8, and wherein light is anti-by serving as back
The veining layer 180 of layer is penetrated to receive.Active layer or area 202 are arranged on texture reflecting layer 180.For example, active layer 202 can
To be solar cell active region, such as emission layer 110 and/or absorbed layer 108.Other one or more layers 204 are at some
It can also be placed in embodiment between active layer 202 and veining layer 180.
Light 206 has been marched in photovoltaic cell 120 and absorbed by upper strata.The light 206 occur from active layer 202 and
Hit the front surface 210 of veining layer 180.Light 206 passes through the transparent material of template layer 140,150 or 155.In some embodiment party
In formula, layer 140,150 or 155 is etched before follow-up procedure of processing.Some of photon 206 can hit dielectric
Layer 162 surface and reflected from the layer.Other photons 206 to pass through dielectric layer 162 and can hit back-metal
Layer 170 surface and reflected from the layer.Photon through reflection orient as indicated by arrow 212 pass back through template layer 140,
150 or 155 and subsequently into active layer 202, wherein they " can bounce around " and can pass through absorbed layer 108
Captured with emission layer 110, and further produce electric current in the battery.
The island 144 (or island 156 of the island 152 of template layer 150 or template layer 155) of template layer 140 exists
Recess 172 is created in dielectric layer 162 and back-metal layer 170.This create the random of dielectric layer 162 and back-metal layer 170
Changing, roughening and angular front surface.Veining layer 180 diffuses or is scattered through the unabsorbed light of active layer 202
Son.The texture of veining layer 180 can provide new angle for incident photon, some of these incident photons can redirect
Pass back through template layer 140,150 or 155 and towards the inside of photovoltaic cell.Although some light can be absorbed by template layer,
But because photon is scattered and redirected in inside, many light are re-directed to active layer 202.Therefore, texture
Therefore changing the different angles on the surface of layer 180 and its recess 172 effectively causes photon 206 to be reflected back work with random angles
To allow larger amount of photon by active layer recapture and be converted into electric energy in property layer 202, so as to enhance battery 120
Light acquisition performance and increase efficiency.
Figure 11 is suitable for providing another implementation of the photovoltaic device 300 of veining layer in the front side of photoelectric device 300
The cross-sectional view of mode.Captured instead of above-mentioned back side light or in addition, veining layer can be arranged for photovoltaic cell
Light capture at front side.The light that this allows to hit the front side of photovoltaic device is by the grain surface created by veining layer in device
It is middle to be scattered, increase the light capture in device.
Photovoltaic device 300 is coupled including the ELO releasing layers by being disposed therein or sacrifice layer 304 with growth wafer 301
Battery 320.In some embodiments, one or more cushions 302 can be formed on growth wafer 301 to open
Beginning forms photovoltaic device 300.The layer of photovoltaic cell 320 can be deposited on sacrifice layer 304, and the sacrifice layer 304 is in some realities
Back semiconductor contact layer 312, the emission layer 310 on back contact layer 312 can be included, on emission layer 310 by applying in mode
Absorbed layer 308 (or emission layer 310 on absorbed layer 308), the front window layer on absorbed layer 308 or passivation layer 306 and it is used for
Basalis 305 texturing, being arranged in Window layer 306.
In some embodiments, back contact layer 312 can include nonmetallic group iii-v compound semiconductor,
Such as GaAs.
Basalis 305 for veining is similar in appearance to the basalis 112 described above with reference to Fig. 1.For example, basalis 305
Provide thereon in order to texture the first layer of purpose deposition template layer, and for example by with the composition different from template layer
(for example, different lattice parameters), can aid in island and is formed.
In other embodiments, device 300 is not grown on sacrificial layer structure as shown or ELO release Rotating fields.
For example, in other embodiments, device 300 is not peeled off program including ELO and is grown in no sacrifice layer 104 or cushion
On 302 substrate.
Figure 12 is the cross-sectional view of photovoltaic device 300, and photovoltaic device 300 is included according to the texture for being used as front side light trapping layer
Change the deposit of the template layer 340 on the basalis 305 of the embodiment of layer.Template layer 340 can use island growth work
Skill is created and provided for making the island 344 of one or more surface texturizings of template layer to cause in the devices
Light reflection and scattering, add light capture.Some embodiments can include wetting layer 342, it is similar in appearance to above-mentioned wetting layer.
In other embodiments, there is no island in layer 340 to grow, and on the contrary, the template layer has component inhomogeneities
And subsequent etch process removes some materials than removing other materials faster.This is also similar to above for Fig. 3 C descriptions
Situation.In some embodiments, layer 340 is etched before follow-up procedure of processing.
In fig. 13, photoelectric device 300, which has been further advanced by, is deposited on layer on template layer 340 to be formed.At some
In embodiment, in example as shown in Figure 13, optional semiconductor contact layer 360 is deposited on template layer 340.
Anti-reflective coating (ARC) 362 can be deposited on semiconductor contact layer (if present) or in template layer
On 340 (if there is no if contact layer 360).ARC layer 362 includes dielectric material, and the dielectric material allows light to pass through, at the same time
Prevent light from being reflected from the surface of ARC layer 362.In some embodiments, ARC layer 362 can include multiple layers.
In ELO embodiments, ELO techniques can be used battery 320 (including layer 340,360 and 362) from ELO layers
301st, 302 and 304 remove.After the removing, battery 320 keeps its direction shown in Figure 11-13 and on above-mentioned
Do not overturn on the direction of dorsal part reflector embodiment.In other embodiments, it is used for battery 320 without ELO techniques.
Layer 340,360 and 362 provides front side light capture veining layer 380.The forward position of veining layer 380 allows it
Receive the light of shock device 300 and at different angles by the lower floor of light scattering to device 300, this is attributed to template layer
Veining, randomization the surface of island in 340.This improves light capture, because photon bounces in lower floor, it is allowed to
More photons are absorbed to produce electric current.
In the other embodiment of device 100 and 300, other layer arrangements, doping arrangement, layer thickness etc. can be used.
For example, emission layer can be deposited on absorbed layer in some embodiments.
Each embodiment of photoelectric device and the method for providing such devices specifically described herein can provide texture
Change layer, veining layer includes being created for making veining layer allow the island for increasing light capture.Disclosed each embodiment
The advantages of can also providing better than previous light trapping layer formation technology, including larger pliability, the cost of attenuating and increase
Layer growth rate, save manufacture device in time and expense.
Although according to shown each embodiment, the invention has been described, those of ordinary skill in the art will be easy
, it is realized that each embodiment there may be change and these changes will within the spirit and scope of the present invention.Therefore, ability
Domain those of ordinary skill can make many modifications, without departing from spirit and scope of the appended claims.
Claims (32)
1. a kind of method for the veining layer being used to provide in photoelectric device, the described method includes：
In the template layer of planar semiconductor layer Epitaxial growth island, wherein the template layer has significantly not on thickness
Uniformity；And
By the template layer and the planar semiconductor layer exposed to etch process to use the template layer to be used as etching mask
At least one texturizing surfaces are produced in the planar semiconductor layer, wherein at least one texturizing surfaces are the light
The part of electrical part.
2. the method as described in claim 1, wherein at least one texturizing surfaces cause light scattering in operation.
3. the method as described in claim 1, wherein the template layer passes through physical vapour deposition (PVD), chemical vapor deposition, liquid phase
Deposition, lithography or liquid coat to be formed.
4. the method as described in claim 1, wherein the etch process by the chemical etchant based on liquid or solution into
OK.
5. the method as described in claim 1, wherein etch process are carried out by the technology from the group consisted of：Gas
Etching, laser-induced thermal etching, plasma etching or ion(ic) etching.
6. the method as described in claim 1, wherein the template layer is not etched in itself.
7. the method as described in claim 1, wherein the template layer is etched in itself.
8. the method as described in claim 1, wherein the etch process is selective more fast with template layer more described than etching
The planar semiconductor layer is etched fastly.
9. the method as described in claim 1, wherein the etch process is selective with than etching in the template layer
Some other materials constituents more quickly etch some material composis included in the template layer.
10. the method as described in claim 1, wherein the template layer due to the template layer and the planar semiconductor layer it
Between lattice mismatch and formed, the template layer is epitaxially grown on the planar semiconductor layer.
11. the method as described in claim 1, wherein the template layer is sufficiently thin incompletely to cover the plane half
Conductor layer, the template layer are epitaxially grown on the planar semiconductor layer.
12. the method as described in claim 1, wherein the template layer includes multiple islands.
13. method as claimed in claim 12, wherein the multiple island has variable size each other.
14. the method as described in claim 1, wherein the angle that at least one texturizing surfaces cause photon to be randomized
Scattering.
15. the method as described in claim 1, wherein the template layer is in semiconductor and the group including consisting of
It is at least one：Gallium, aluminium, indium, phosphorus, nitrogen and arsenic.
16. the method as described in claim 1, wherein the template layer has the band gap of bigger than the planar semiconductor layer.
17. the method as described in claim 1, wherein the template layer is transparent.
18. the method as described in claim 1, wherein the template layer is formed using Stranski-Krastanov techniques.
19. the method as described in claim 1, wherein the template layer is formed using Volmer-Weber techniques.
20. the method as described in claim 1, further includes dielectric layer deposition on the template layer.
21. the method as described in claim 1, further includes and transparent conductive oxide (TCO) layer is deposited on the template layer.
22. the method as described in claim 1, further includes anti-reflection coating being deposited at least one texturizing surfaces
On.
23. the method as described in claim 1, further includes and metallic reflector is deposited on the template layer.
24. method as claimed in claim 23, wherein, Jie between the metallic reflector and the planar semiconductor layer
Electric layer is provided with hole, with allow between the metallic reflector and the planar semiconductor layer or in the metallic reflector and
Between the template layer, or the conduction of the metallic reflector and the planar semiconductor layer with the template layer between the two connects
Touch.
25. the method as described in claim 1, wherein at least one texturizing surfaces are back reflector layers, the back of the body is anti-
Emitter layer is oriented to p-n junction than the photoelectric device further from the front portion of the photoelectric device.
26. the method as described in claim 1, wherein at least one texturizing surfaces are front window layers, the front window
Layer is oriented to p-n junction than the photoelectric device closer to the front portion of the photoelectric device.
27. the method as described in claim 1, further includes：
Semiconductor contact layer is deposited on the template layer；And
By dielectric layer deposition on the semiconductor contact layer.
28. a kind of texturizing surfaces in photovoltaic device, the method system described in the texturizing surfaces usage right requirement 1
Make, which includes at least one texturizing surfaces.
29. a kind of method for providing photoelectric device, the described method includes：
Deposit emitter layer and absorber layers；
The plane layer of first material is deposited in the emitter layer and the absorber layers；
By the template layer epitaxially grown of the second material on the plane layer, wherein the template layer has significantly on thickness
Inhomogeneities；
By the template layer and the plane layer exposed to etch process to use the template layer as etching mask described
At least one texturizing surfaces are produced in plane layer, wherein at least one texturizing surfaces cause light scattering in operation,
And wherein described at least one texturizing surfaces are the parts of the photoelectric device；
By dielectric layer deposition on the template layer；And
By deposition of metal on the dielectric layer.
30. a kind of method for providing photoelectric device, the described method includes：
Deposit emitter layer and absorber layers；
The plane layer of first material is deposited in the emitter layer and the absorber layers；
By the template layer epitaxially grown of the second material on the plane layer, the template layer has one of second material
Or multiple islands, wherein one or more of islands have irregular physical features；
The template layer and the plane layer are exposed to etch process to produce at least one veining in the plane layer
Surface, wherein at least one texturizing surfaces cause light scattering in operation, wherein at least one texturizing surfaces are institutes
State the part of photoelectric device；And
Anti-reflecting layer is deposited on the template layer.
31. a kind of method for manufacturing photoelectric device, the described method includes：
In the template layer of planar semiconductor layer Epitaxial growth island, wherein the template layer has significantly not on thickness
Uniformity；And
By the template layer and the planar semiconductor layer exposed to etch process to use the template layer to be used as etching mask
At least one texturizing surfaces are produced in the planar semiconductor layer, wherein the template layer is for manufacturing the phototube
Retained at least in part in whole the method for part, and wherein described at least one texturizing surfaces are the phototubes
The part of part.
32. method as claimed in claim 30, wherein the irregular physical features are including one or more of following：
The irregular size of one or more of islands,
The irregular shape of one or more of islands, or
Irregular interval between one or more of islands.
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| CN102473743A (en) * | 2010-01-27 | 2012-05-23 | 因特潘开发咨询有限责任公司 | Method for producing a coated item by means of texture etching |
| CN103952768A (en) * | 2014-05-09 | 2014-07-30 | 中国科学院宁波材料技术与工程研究所 | Monocrystal silicon inverted pyramid array structure suede, and preparation method and application thereof |
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| CN102473743A (en) * | 2010-01-27 | 2012-05-23 | 因特潘开发咨询有限责任公司 | Method for producing a coated item by means of texture etching |
| CN103952768A (en) * | 2014-05-09 | 2014-07-30 | 中国科学院宁波材料技术与工程研究所 | Monocrystal silicon inverted pyramid array structure suede, and preparation method and application thereof |
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