CN105336718A - 源极向下半导体器件及其制造方法 - Google Patents

源极向下半导体器件及其制造方法 Download PDF

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Publication number
CN105336718A
CN105336718A CN201510468210.8A CN201510468210A CN105336718A CN 105336718 A CN105336718 A CN 105336718A CN 201510468210 A CN201510468210 A CN 201510468210A CN 105336718 A CN105336718 A CN 105336718A
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Prior art keywords
semiconductor substrate
methods according
carrier
layer
paste
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CN201510468210.8A
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CN105336718B (zh
Inventor
M·施内甘斯
A·梅瑟
M·米希兹
M·勒斯纳
M·皮恩克佐利兹
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Infineon Technologies AG
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Infineon Technologies AG
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Priority claimed from US14/451,043 external-priority patent/US9640419B2/en
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Abstract

一种用于形成半导体器件的方法，其包括：在半导体衬底中形成器件区域，半导体衬底包括第一侧和第二侧。器件区域与第一侧邻近地形成。该方法还包括：在半导体衬底的第一侧之上形成种子层；在种子层之上形成经图案化的抗蚀剂层。在经图案化的抗蚀剂层内在种子层之上形成接触焊盘。该方法还包括：在形成接触焊盘之后，去除经图案化的抗蚀剂层，以露出种子层的在经图案化的抗蚀剂层之下的部分；以及在种子层的露出的部分之上形成保护层。

Description

源极向下半导体器件及其制造方法
相关申请的交叉引用
本申请是2014年8月4日提交的美国非临时申请No.14/451,043的部分接续案申请，在此通过参考将该申请并入本文。
技术领域
本发明总地涉及半导体器件，并且在具体实施例中涉及源极向下半导体器件及其制造方法。
背景技术
半导体器件用在许多电子应用和其它应用中。半导体器件可以包括形成在半导体晶片上的集成电路。备选地，半导体器件可以被形成为单片器件，例如分立器件。通过在半导体晶片之上沉积许多类型的材料薄膜、对材料薄膜进行图案化、对半导体晶片的选择区域进行掺杂等，半导体器件被形成在半导体晶片上。
在常规半导体制造工艺中，在单个晶片中制造大量的半导体器件。每个晶片以批量模式被处理，或者单独地被处理，这是因为一些工艺有时对一个晶片的效果最佳。需要机械力的工艺，诸如抛光、单片化、研磨和其它工艺，不仅单独地被处理，而且也可以被安装在载体上用于在处理期间提供附加的支撑和稳定性。
发明内容
根据本发明的一个实施例，一种用于形成半导体器件的方法包括：在半导体衬底中形成器件区域，该半导体衬底包括第一侧和第二侧。器件区域与第一侧邻近地形成。该方法进一步包括：在半导体衬底的第一侧之上形成种子层；以及在种子层之上形成经图案化的抗蚀剂层。在经图案化的抗蚀剂层内的种子层之上形成接触焊盘。该方法进一步包括：在形成接触焊盘之后，去除经图案化的抗蚀剂层，以露出覆种子层的在经图案化的抗蚀剂层之下的部分；以及在种子层的露出部分之上形成保护层。
根据本发明的另一实施例，一种用于形成半导体器件的方法包括：在半导体衬底的第一侧之上形成种子层。半导体衬底在第一侧处包括器件区域。该方法包括：在种子层之上形成接触焊盘，同时露出种子层的与接触焊盘相邻的部分；以及在种子层的露出部分之上形成保护层。将膏剂涂覆在半导体衬底之上。膏剂覆盖保护层。该方法进一步包括：通过固化膏剂来形成陶瓷载体；以及通过使用陶瓷载体作为载体，来处理半导体衬底。
根据本发明的另一实施例，一种半导体器件包括芯片，该芯片包括经划片的半导体衬底、以及种子层，该种子层布置在经划片的半导体衬底的整个主表面之上、并且与经划片的半导体衬底的整个主表面重叠。经图案化的接触焊盘布置在种子层的部分之上，并且覆盖种子层的该部分。经划片的载体材料布置在经划片的半导体衬底之上，并且布置在经图案化的接触焊盘的侧壁处。
根据本发明的又一实施例，一种用于形成半导体器件的方法，该方法包括：在半导体衬底中形成器件区域，半导体衬底包括第一侧和第二侧，其中器件区域与第一侧邻近地形成；将半导体衬底的第一侧安装到载体上；以及对半导体衬底和载体进行单片化，以形成多个半导体裸片。
根据本发明的又一实施例，一种用于形成半导体器件的方法，该方法包括：在半导体衬底之上涂覆膏剂；通过固化膏剂，来形成陶瓷载体；以及通过将陶瓷载体用作载体，而减薄半导体衬底。
根据本发明的又一实施例，一种半导体芯片，包括：经划片的半导体衬底；以及经划片的载体，布置在半导体衬底之上。
附图说明
为了更全面地理解本发明及其优势，现在参考以下结合附图作出的描述，其中：
图1A图示了根据本发明的一个实施例的在完成前端工艺之后的制造过程中的半导体器件的横截面图；
图1B图示了根据本发明的一个实施例的在形成阻挡层和种子层之后的制造过程中的半导体器件的横截面图；
图1C图示了根据本发明的一个实施例的在形成经结构化的抗蚀剂层之后的制造过程中的半导体器件的横截面图；
图1D图示了根据本发明的一个实施例的在沉积用于形成接触焊盘的导电材料之后的制造过程中的半导体器件的横截面图；
图1E图示了根据本发明的一个实施例的在通过去除抗蚀剂层形成接触焊盘之后的制造过程中的半导体器件的横截面图；
图1F图示了根据本发明的一个实施例的在安装在载体上之后的制造过程中的半导体器件的横截面图；
图1G图示了根据本发明的一个实施例的在背侧金属化层的形成之后的半导体衬底；
图1H图示了根据本发明的一个实施例的在对背侧金属化层进行图案化之后的半导体衬底；
图1I图示了根据本发明的一个实施例的在单片化之后的半导体衬底；
图2A图示了根据本发明的一个实施例的在形成前端工艺以及涂覆载体材料之后的半导体衬底；
图2B图示了根据本发明的一个实施例的在用于对陶瓷载体进行抛光的抛光工艺期间的制造过程中的半导体器件的横截面图；
图2C图示了根据本发明的一个实施例的在形成经平坦化的陶瓷载体之后的制造过程中的半导体器件的横截面图；
图2D图示了根据本发明的一个实施例的使用载体***的半导体衬底的处理；
图2E图示了根据本发明的一个实施例的在使用经平坦化的陶瓷载体使衬底减薄之后的制造过程中的半导体器件的横截面图；
图2F图示了根据本发明的一个实施例的在形成经图案化的背侧金属化层之后的制造过程中的半导体器件的横截面图；
图2G图示了根据本发明的一个实施例的在减薄载体之后的衬底和载体；
图2H和图2I图示了根据本发明的一个实施例的在单片化的制备中利用划片胶带的放置在框架上的载体和衬底，其中图2I图示了横截面图，图2H图示了顶视图；
图2J图示了根据本发明的一个实施例的在处理半导体芯片时的后续阶段期间的划片工艺；
图2K图示了根据本发明的一个实施例的在划片工艺之后形成的多个裸片；
图3图示了根据本发明的一个备选实施例的在形成经图案化的背侧金属化层之后的制造过程中的半导体器件的横截面图；
图4图示了包括根据本发明的实施例形成的芯片的半导体封装体。
具体实施方式
常规功率MOSFET被安装在封装体中的引线框架或衬底之上，其中源极引线和栅极引线背离引线框架。然而，当由功率器件支持的电压为大时，功率器件产生相当大的热量，该热量需要被快速地耗散掉。通常，热量通过下方的引线框架而耗散。
源极向下配置被日益增加地使用，以改善热量离开功率器件的传导。在这样的配置中，源极引线被直接安装在引线框架上，而漏极引线背离引线框架。由于使得源极引线更靠近散热器，所以可以改善散热。
在下文描述的各种实施例中，修改源极接触区域，以通过使用种子层和扩散阻挡层来基本覆盖衬底的所有表面区域。因此，与常规工艺不同，并不对在形成接触焊盘时所使用的扩散阻挡层和种子层进行图案化和去除。
将通过使用在图1至图3中描述的方法和在图4中描述的半导体封装体来进一步描述本发明的实施例。
图1包括图1A至图1I，图示了根据本发明的一个实施例的在制造过程中的半导体器件的截面图。
图1A图示了根据本发明的一个实施例的在前端工艺的完成之后的制造过程中的半导体器件的横截面图。
参照图1A，图示了在前端工艺的完成之后的半导体衬底10。半导体衬底10具有形成在其中的多个半导体器件，即芯片1。芯片1中的每个芯片可以是任意类型的芯片。例如，芯片1中的每个芯片可以是逻辑芯片、存储器芯片、模拟芯片、高功率开关和其它类型的芯片。芯片1中的每个芯片可以包括形成集成电路的诸如晶体管或二极管之类的多个器件，或可以是诸如单个晶体管或单个二极管之类的分立器件。
在各种实施例中，半导体芯片1可以包括功率半导体器件，其在一个实施例中可以为分立的垂直器件。在一个实施例中，半导体芯片1是诸如PIN二极管或肖特基二极管之类的两端子器件。在一个或多个实施例中，半导体芯片1为诸如功率金属绝缘体半导体场效应晶体管(MISFET或MOSFET)、结型场效应晶体管(JFET)、双极结型晶体管(BJT)、绝缘栅型双极晶体管(IGBT)或晶闸管之类的三端子器件。
在一个实施例中，衬底10可以包括诸如硅晶片之类的半导体晶片。在其它实施例中，衬底10可以是包括其它半导体材料的晶片，该其它半导体材料例如包括合金，诸如SiGe、SiC，或者化合物半导体材料，诸如GaAs、InP、InAs、GaN、蓝宝石、绝缘体上硅。在各种实施例中，衬底10可以包括碳化硅(SiC)的层。在一个实施例中，衬底10可以包括氮化镓(GaN)的层。
因此，在一个实施例中，半导体芯片1可以包括在硅衬底、碳化硅衬底、氮化镓衬底上形成的垂直功率器件。备选地，半导体芯片1可以包括在衬底上形成的横向功率器件，该衬底包括碳化硅层和/或氮化镓层。
作为图示，衬底10可以为300mm硅晶片，该晶片可以具有约750μm至约800μm的厚度，而在另一实施例中，衬底10可以是200mm、300mm或450mm硅晶片，该晶片可以具有约700μm至约750μm的厚度。
参照图1A，器件区域15被布置在衬底10内。在各种实施例中，器件区域15可以包括掺杂区域。此外，器件区域15的一些部分可以被形成在衬底10之上。器件区域15可以包括诸如晶体管的沟道区域之类的有源区域。器件区域15可以使用多个隔离区域16来进行隔离，在一个实施例中该隔离区域16可以是隔离沟槽。作为图示，器件可以包括形成垂直晶体管的多个沟槽栅极17。
衬底10包括顶表面11和相对的底表面12。在各种实施例中，器件区域15被形成为与底表面12相比更靠近衬底10的顶表面11。有源器件可以被形成在衬底10的器件区域15中。器件区域15在一定深度上延伸，该深度取决于器件，约为从顶表面11起5μm至50μm，并且在一个实施例中约为10μm。此外，如随后将描述的那样，芯片1的最终深度将在减薄之后确定。
在各种实施例中，在衬底10之上形成所有必要的互连、连接、焊盘等，用于在器件区域15的器件之间进行耦合和/或与外部电路***进行耦合。相应地，在衬底10之上形成金属化层20。金属化层20可以包括一个或多个金属化层级。每个金属化层级可以包括嵌入在绝缘层内的金属线或过孔。金属化层20可以包括金属线和过孔，用于接触器件区域15并且用于将每个芯片1内的不同器件耦合，诸如互连30，其将多个沟槽栅极17连接到栅极接触区域61。
图1B图示了根据本发明的一个实施例的在形成阻挡层和种子层之后的制造过程中的半导体器件的横截面图。
参照图1B，在金属化层20之上形成阻挡层21和种子层22。阻挡层21是保形的，并且作为示例，可以包括Ta,TaN,WN,WSi,Ti,TiN,Ru,Co的单层及其组合。此外，可以用于阻挡层21的材料的示例包括氮化钽硅、钨、钨化钛等。在一个特定示例中，阻挡层21可以包括钨钛层。
阻挡层21通常可以被用作用于防止金属扩散到下方的半导体材料或金属化层20的阻挡层。阻挡层21可以例如使用化学气相沉积(CVD)、物理气相沉积(PVD)或原子层沉积(ALD)工艺来沉积。
然后类似地使用例如CVD、PVD或ALD工艺，在阻挡层21之上沉积种子层22。种子层22可以是例如包括铜的种子层，用于后续的铜的电镀。
在各种实施例中，使用保形沉积工艺来沉积阻挡层21和种子层22，在金属化层20的顶表面上留下保形的衬层或扩散阻挡层。在一个实施例中，阻挡层21包括通过物理气相沉积(PVD)而沉积的氮化钽。
备选地，阻挡层21可以包括氮化钛、氮化钨、钛钨、难熔金属或其它可以使用例如CVD、PVD工艺或化学镀覆而保形地沉积的阻挡层。在一些实施例中，可以原位沉积阻挡层21和种子层22。
种子层22可以包括金属材料。种子层22可以例如包括纯金属或合金。应理解到，任何纯金属可以包括一定量的微量杂质。合金可以包括至少两种金属元素。合金可以包括金属元素和非金属元素。
种子层22可以包括元素Cu(铜)、Al(铝)、Au(金)、银(Ag)和W(钨)中的一种或多种。材料的示例包括纯铜、铜合金、纯铝、铝合金、纯金、金合金、纯银、银合金、纯钨和钨合金。种子层22可以通过物理气相沉积或溅射工艺来形成。
图1C图示了根据本发明的一个实施例的在形成经结构化的抗蚀剂层之后的制造过程中的半导体器件的横截面图。
参照图1C，形成用于接触焊盘的开口24。在各种实施例中，可以通过沉积抗蚀剂层23、并且使用光刻和刻蚀工工艺的组合对接触焊盘进行图案化，来形成开口24，抗蚀剂层23包括硬掩膜层和光致抗蚀剂层。经结构化的抗蚀剂层23可以包括经显影的光致抗蚀剂层、以及在光致抗蚀剂层之下的一层或多层硬掩膜层。
开口24使用于电镀的下方的种子层22露出，同时挡住种子层22的其上将不形成接触焊盘的部分。
图1D图示了根据本发明的一个实施例的在沉积用于形成接触焊盘的导电材料之后的制造过程中的半导体器件的横截面图。
参照图1D，在种子层22之上沉积导电填充材料25。在各种实施例中，导电填充材料25包括导电材料。导电填充材料25可以包括金属材料。导电填充材料25可以包括纯金属或合金。
在各种实施例中，导电填充材料25可以包括元素Cu(铜)、Al(铝)、Au(金)、银(Ag)和W(钨)中的一种或多种。材料的示例包括纯铜、铜合金、纯铝、铝合金、纯金、金合金、纯银、银合金、纯钨和钨合金。
在一个实施例中，可以通过电镀(或电镀沉积)工艺来形成导电填充材料25。在其它实施例中，可以使用溅射、气相沉积、诸如丝网印刷之类的印制、涂覆等来沉积导电填充材料25。
在一个实施例中，导电填充材料25可以包括钨，但是在其它实施例中也可以使用铜、铝、Al-Cu-Si、其它金属及其组合。如果导电填充材料25包括钨，则优选地使用包括CVD氮化钛和硅掺杂钨的双层种子层作为阻挡层21和种子层22。在其它实施例中，利用铜填充开口24。
图1E图示了根据本发明的一个实施例的在通过去除抗蚀剂层形成接触焊盘之后的制造过程中的半导体器件的横截面图。
如接下来在图1E中所示，去除抗蚀剂层23，从而形成接触焊盘60。此外，在一些实施例中，例如使用化学机械抛光(CMP)工艺，使导电填充材料25平坦化。
然而，在各种实施例中，并未去除在抗蚀剂23的去除时露出的种子层22。因此，种子层22和阻挡层21继续停留在整个衬底10之上。
在形成由经图案化的接触焊盘60的情况下，完成前端处理。可以在导电填充材料25和露出的种子层22之上沉积酰亚胺层50。对酰亚胺层50进行开孔，例如向下刻蚀或备选地进行图案化，以露出经图案化的接触焊盘60。
通常，在进一步的处理之前沉积钝化层。钝化层被设计用于在后续处理期间帮助保护以及器件区域15。然而，在一个或多个实施例中，钝化层可以被省略，这是因为这一功能可以使用载体***被有利地执行。
图1F图示了根据本发明的一个实施例的在安装在支撑上之后的制造过程中的半导体器件的横截面图。
参照图1F，对衬底10的背侧进行减薄，形成经减薄的衬底110并且露出新的背表面13。减薄工艺可以包括机械研磨、等离子体刻蚀、湿法刻蚀和抛光中的一种或多种。减薄工艺使多个隔离区域16露出，由此使栅极接触区域61与器件的漏极区域62隔离。在减薄之前，可以利用胶带将衬底10安装在例如载体的支撑66上，用于在减薄和后续处理期间的稳定性。
图1G图示了根据本发明的一个实施例的在背侧金属化层的形成之后的半导体衬底。
接下来参照图1G，在减薄的衬底110的露出的背表面13下方形成背侧金属化层65。在各种实施例中，背侧金属化层65可以包括多于一个的金属层。作为说明例，图示了第一背侧金属化层120、第二背侧金属化层130、第三背侧金属化层140。
在一个或多个实施例中，可以使用物理气相沉积工艺来沉积背侧金属化层65。在备选实施例中，可以使用包括化学气相沉积、原子层沉积的其它气相沉积工艺、电化学沉积、化学镀覆等来沉积背侧金属化层65。
在各种实施例中，背侧金属化层65包括铝。在一个或多个实施例中，背侧金属化层65包括多层，该多层包括铝、钛、镍钒和银中的一个或多个层。在另一实施例中，背侧金属化层65包括多层，该多层包括使用热物理气相沉积工艺而沉积的铝、钛、金锡中的一个或多个层，其中在对减薄的衬底110进行加热之后执行沉积。
在备选实施例中，背侧金属化层65包括铜。在另一备选实施例中，背侧金属化层65包括焊料兼容材料，例如可以包括银、锡、金、铂、锡、铅、铟、镉、铋中的一种或多种。如上所描述，特定示例包括铝层、钛层、镍钒层、银、金-锡等，以便实现热铝物理气相沉积，用于在减薄的衬底110的背侧处形成低欧姆接触。
在又一实施例中，背侧金属化层65包括金属硅化物。在另一实施例中，背侧金属化层65包括诸如氮化钛、氮化钨、氮化钽之类的金属氮化物。
在各种实施例中，通过沉积钛或钨来形成第一背侧金属化层120，并且通过沉积铝来形成第二背侧金属化层130。
在各种实施例中，沉积100nm至约500nm的第三背侧金属化层140。第三背侧金属化层140可提供用于接触形成的焊料层。第三背侧金属化层140的示例包括Au、Ag、Sn、Au合金、Ag合金、Sn合金及其组合。在其它实施例中，沉积100nm至约10000nm的第三背侧金属化层140。在各种实施例中，第三背侧金属化层140可以包括形成焊料层的多层，并且也可以保护下方的金属免受环境影响。在一些实施例中，可以使用铜作为第三背侧金属化层140。
图1H图示了根据本发明的一个实施例的在对背侧金属化层进行图案化之后的半导体衬底。
在进行图案化之后，如图1H所示，背侧金属化层65包括漏极接触65D和栅极接触65G，在各种实施例中，背侧金属化层65可以包括多个金属层。
图1I图示了根据本发明的一个实施例的在单片化之后的半导体衬底。
参照图1I，从支撑66去除减薄的衬底110。将减薄的衬底110附着到胶带，该胶带可以是包括粘附胶带72的框架状支撑结构71。将减薄的衬底110安装到在外支撑结构71内的粘附胶带72。在一个实施例中，粘附胶带72可以是划片胶带。在一个或多个实施例中，作为环形结构的支撑结构71，沿着外边缘支撑粘附胶带72。在另一实施例中，粘附胶带72可以具有例如聚氯乙烯的衬底，该衬底具有粘附层的涂层，诸如丙烯酸树脂。在一个或多个实施例中，支撑结构71包括诸如金属或塑料(陶瓷)材料之类的支撑材料。在各种实施例中，支撑结构71的内径大于减薄的衬底110的直径。在备选实施例中，支撑结构71可以包括除了圆形之外的适当形状。
如图1I所示，在一个或多个实施例中，将减薄的衬底110牢固地固定在粘附胶带72的中央部分之上。因此，可以在下述的后续单片化工艺期间安全地处理减薄的衬底110。
然后可以对减薄的衬底110进行单片化，形成单独的裸片。例如通过胶带膨胀工艺，可以将经单片化的裸片从具有胶带的载体去除。
图2包括图2A至图2K，图示了根据本发明的一个实施例的在各个制造阶段中的半导体器件。
图1所描述的实施例可以适用于处理薄衬底。现代半导体芯片在减小的厚度下制造，以例如通过减小热效应而改善性能。例如，通过减薄衬底厚度而减小功率器件的导通电阻同时改善热传导。薄芯片日益变得必要，特别是对于高功率应用。然而，非常薄的芯片需要薄晶片处理，该晶片可能薄于60μm。在没有附加的机械支撑的情况下，这样的薄晶片无法被处理。因此，需要复杂的载体***来支撑这样的薄晶片。在没有这样的载体***的情况下，对于非常薄的芯片的处理和组装是受限的。
用以支撑薄晶片的现有技术的***使用胶以将玻璃载体晶片附着在Si晶片的顶部上。在处理之后，去除玻璃载体晶片和胶。然而，这种基于胶的接合的热稳定性是有限的，例如上至240℃低于2分钟。备选地，将例如玻璃栅格的永久载体通过玻璃焊料连接到硅晶片。这些接触的热稳定性在300℃至800℃的范围内。但预先图案化的玻璃栅格是机械受限的，这是因为它们需要玻璃条比150μm更宽。因此，这些可以不是具有小切口(例如30μm-100μm)的使用晶片。
备选地，例如在嵌入的晶片级处理中，使用模制化合物作为载体***。但这样的技术具有受限的热稳定性，例如高达280℃。
在一个或多个实施例中，在晶片之上形成陶瓷膏剂，之后通过烧结工艺来形成永久的、热稳定的且隔离的载体***。在执行载体的功能之后，晶片与载体一起被单片化成单独的芯片，从而载体的部分成为组装好的器件的一部分。
图2A图示了根据本发明的一个实施例的在形成前端处理且涂覆载体材料之后的半导体衬底。
如在现有实施例中所描述的，在形成经图案化的接触焊盘60的情况下，完成前端处理。可以通过使用镀覆工艺来沉积厚铜层，而形成经图案化的接触焊盘60。酰亚胺层50可以被沉积在厚铜层之上，并且被开孔以露出经图案化的铜焊盘60。
通常，在进一步处理之前，沉积钝化层或保护层。保护层被设计为在后续处理期间保护金属化层20以及器件区域15。然而，在一个或多个实施例中，可以省略保护层，这是因为这一功能可以通过使用载体***而被有利地执行。
在各种实施例中，在衬底10的顶表面11之上沉积陶瓷膏剂。在各种实施例中，通过使用印制工艺，将陶瓷膏剂作为液体沉积，之后进行干燥和烧结。
在一个备选实施例中，使用涂覆工艺来沉积陶瓷膏剂。在其它实施例中，可以使用诸如旋涂工艺之类的工艺来沉积陶瓷膏剂，例如在该期间沉积旋涂的电介质。在其它实施例中，可以使用其它沉积工艺来沉积膏剂。
在一个或多个实施例中，除了陶瓷材料之外，可以印制氧化硅、氧化铝、氧化镁、氧化钛或类似材料的膏剂，并进行烧结，以形成如陶瓷膏剂或混凝土(concrete)的稳定氧化物。在各种实施例中，陶瓷膏剂可以是基于水的混合物并且可以类似混凝土而呈现自硬化。
在各种实施例中，陶瓷膏剂具有浆料状粘性，从而避免了它流动离开衬底10。在一些实施例中，可以由被设置用于形成固态材料的两种组分的混合物来形成陶瓷膏剂。在各种实施例中，可以使用自固化材料作为载体材料。
附加地，在一些实施例中，也可以使用基于由有机化合物填充的热稳定聚合物的化合物材料。其它实施例可以使用粉末材料(包括陶瓷和氧化物)，该粉末材料通过使用激光烧结而被固化和/或图案化。
陶瓷膏剂被烧结(加热)以形成固态材料。例如，在一个或多个实施例中，烧结可以在380℃至约450℃下执行。在另一实施例中，烧结可以在350℃至约450℃下执行。在另一实施例中，烧结可以在400℃至约450℃下执行。在其它实施例中，烧结工艺可以在较低温度下执行。
在固化之后，载体材料提供电隔离，否则衬底上的各种部件可能创建电短路。
在各种实施例中，固化的陶瓷膏剂形成具有顶表面81的陶瓷载体80。如图2A所示，陶瓷载体80可以具有弯曲表面，这是由于所沉积的陶瓷膏剂的表面张力和/或在烧结期间出现的后续应力的影响所造成的。固化(烧结)的陶瓷膏剂的曲率在边缘和拐角85处可能进一步恶化。
在各种实施例中，陶瓷载体80具有类似于硅的热膨胀系数的热膨胀系数。
在一个或多个实施例中，陶瓷载体80的厚度为至少150μm，并且在各种实施例中为约150μm至约180μm。在一个或多个实施例中，陶瓷载体80的厚度至少为衬底10的厚度的20％至70％。陶瓷载体80的厚度是陶瓷载体80的机械特性以及衬底10的厚度和直径的函数。衬底10越大，需要陶瓷载体80越厚。
图2B图示了根据本发明的一个实施例的在用于对陶瓷载体进行抛光的抛光工艺期间的制造过程中的半导体器件的横截面图。
参照图2B，使陶瓷载体80的顶表面81经受抛光处理，以去除弯曲的表面82。抛光工艺可以通过将衬底10放置在卡盘上并通过真空保持住以防止损坏衬底10而执行。在一个实施例中可以作为研磨工具的减薄工具91使载体80的厚度减小。在另一实施例中，减薄工具可以使用化学工艺，诸如湿法刻蚀或等离子体刻蚀，以减薄载体80。
图2C图示了根据本发明的一个实施例的在形成陶瓷载体之后的制造过程中的半导体器件的横截面图。
随后，如图2C所示，在抛光工艺之后，陶瓷载体80可以具有平坦表面83。在各种实施例中，陶瓷载体80可以具有约60μm至约120μm的厚度。在一个或多个实施例中，减薄后的陶瓷载体80的厚度为衬底10的厚度的至少5％至15％，并且在一个实施例中为衬底10的约10％。抛光后的载体80的拐角86使得在后续处理期间能够将载体80稳定地放置。
图2D图示了根据本发明的实施例的使用载体***的半导体衬底的处理。
后续处理如在常规处理中那样继续，除了根据本发明的实施例可以不使用附加载体之外。图2D图示了使用上述本发明的实施例形成的载体80，该载体在后续处理期间支撑衬底10。载体80可以被安装在卡盘90上，并且可以在例如处理腔室95内被处理。
图2E图示了根据本发明的一个实施例的在使用陶瓷载体对衬底减薄之后的制造过程中的半导体器件的横截面图。
使用陶瓷载体80作为机械支撑，从背侧，即从先前的底表面12，对衬底10进行减薄。在各种实施例中，减薄可以通过使用机械研磨、化学刻蚀或二者的组合来执行。在衬底10中形成的芯片1最终深度将在减薄后而确定。在一个实施例中可以是研磨工具的减薄工具，使衬底10的厚度减小。在另一实施例中，减薄工具可以使用诸如湿法刻蚀或等离子体刻蚀之类的化学工艺来减薄衬底10。
在一个或多个实施例中，衬底10可以在未安装在胶带上的情况下被减薄。在各种实施例中，减薄可以在整个晶片背侧上是平坦的，或者通过抗蚀剂图案化以及湿法或等离子体刻蚀来进行图案化。例如，可能需要通过研磨对衬底10的局部减薄(例如如上文所描述)以及随后的抗蚀剂图案化和湿法刻蚀或等离子体刻蚀，以在热器件面积区域中实现薄衬底并且在芯片边缘处实现用于机械稳定性的较厚区域。
在一个或多个实施例中，减薄后的衬底10(即减薄的衬底110)可以是5μm至约40μm。器件区域15露出了减薄后的减薄衬底110的新的背表面13。器件区域15被减薄到小于例如10μm。
图2F图示了根据本发明的一个实施例的在形成经图案化的背侧金属化层之后的制造过程中的半导体器件的横截面图。
可以在执行背侧氧化之后进行图案化。在经图案化的背侧钝化层112之间形成背侧金属化层65，该经图案化的背侧钝化层112可以用作刻蚀停止层。经图案化的背侧钝化层112可以包括氧化物和氮化物层。如前面所描述，背侧金属化层65形成在减薄的衬底110的露出的背表面13上，并且被图案化。
图2G图示了根据本发明的一个实施例的在减薄载体之后的衬底和载体。
参照图2G，载体80被减薄到用于封装的合适厚度。在一个实施例中，载体80的减薄去除了下方的经图案化的接触焊盘60的覆盖物，从而使得仅留下在相邻接触焊盘60之间的载体材料80。
在各种实施例中，载体80可以使用研磨工艺来减薄。在一个或多个实施例中，减薄后的载体80的厚度为约40μm至约100μm。然而，减薄后的剩余载体80比剩余的减薄的衬底110更厚。在没有载体80的情况下，经减薄的衬底110的薄层可能翘曲和/或机械地碎裂。因此，剩余载体80的厚度大于经减薄的衬底110的厚度。
图2H和图2I图示了根据本发明的一个实施例的载体和衬底，其被放置在具有准备用于单片化的划片胶带的框架上。图2H图示了顶视图，图2I图示了横截面图。
参照图2H，衬底被附着到包括粘附胶带220的框架210。经减薄的衬底110和载体80被安装到在外框架210内的粘附胶带220。在一个实施例中，粘附胶带220可以是划片胶带。框架210可以包括与上面参照图1I所描述的框架类似的特征。
在备选实施例中，如果载体80具有更高的内在应力，则在无附加的机械支撑的情况下对载体80进行减薄(如图2E中那样)可能使载体80断裂或层离(delaminate)。在这样的实施例中，在对载体80的减薄之前，将具有减薄的衬底110的载体80附着到框架210的粘附胶带220。
如图2G和图2I所示，在一个或多个实施例中，减薄的衬底110和载体80被牢固地固定在粘附胶带220的中央部分之上。因此，减薄的衬底110和载体80在下述的后续单片化工艺期间可以被安全地处理。
图2J图示了根据本发明的一个实施例的在处理半导体芯片时的后续阶段期间的划片工艺。
如接下来在图2J中所示，使用划片工具240来贯穿划片区域230地划片。在一个或多个实施例中，划片区域230可以是窄的，例如30μm至100μm。在一个实施例中，划片工具240可以是切割刀。在一个实施例中，划片可以通过使用两步划片工艺来执行。在第一步骤中，可以使用较宽的划片刀来切割载体材料180，之后由较窄的刀切割减薄的衬底110。在划片期间，划片刀贯穿种子层22和阻挡层21地切割。
图3图示了根据本发明的备选实施例的在形成经图案化的背侧金属化层之后的制造过程中的半导体器件的横截面图。
图3是图2F所示的背侧金属化的备选实施例，并且可以跟随在图2A至图2E之后。在该实施例中，可以使用经图案化的背侧钝化层112作为刻蚀掩膜，来执行附加的衬底刻蚀。后续处理可以如图2G至图2K所描述的那样继续。
图4图示了包括根据本发明的实施例形成的芯片的半导体封装体。
参照图4，半导体封装体300包括引线框架，在引线框架之上布置半导体芯片1。半导体芯片1安装在引线框架的裸片底座330之上，该引线框架可以是铜引线框架。引线框架具有多个引线320，作为示例该多个引线320包括第一引线321、第二引线322。
在半导体芯片1的前侧上的接触(漏极接触65D和栅极接触65G)通过使用导线键合310而耦合到多个引线320。半导体芯片1的背侧接触(接触焊盘60，包括共用源极接触65S)直接电耦合到裸片底座330。裸片底座330直接电耦合到多个引线320之一。
密封体350布置成，围绕半导体芯片1并且在裸片底座330上方。在各种实施例中，半导体芯片1可以使用其它类型的封装工艺来进行封装。
也可以使用实施例来形成共用漏极器件，其中源极接触65S和漏极接触65D位置颠倒，从而使得共用漏极可以被附着至裸片底座330，而源极接触和栅极接触被附着到多个引线320。
如在各种实施例中所描述的，包括金属的材料可以例如为纯金属、金属合金、金属化合物、金属间化合物以及其它类似材料，即包括金属原子的任何材料。例如，铜可以是纯铜或包括铜的任何材料，诸如但不限于铜合金、铜化合物、铜的金属间化合物、包括铜的绝缘体、以及包括铜的半导体。
尽管已经参照示例性实施例描述了本发明，但本描述并不旨在构成限制意义。参考描述，对于本领域技术人员显而易见，示例性实施例的各种修改和组合以及本发明的其它实施例。作为说明，在备选实施例中，图1至图4所描述的实施例可以彼此组合。因而意味着，所附权利要求涵盖任何这样的修改或实施例。

Claims (46)

1.一种用于形成半导体器件的方法，所述方法包括：
在半导体衬底中形成器件区域，所述半导体衬底包括第一侧和第二侧，其中所述器件区域与所述第一侧邻近地形成；
在所述半导体衬底的所述第一侧之上形成种子层；
在所述种子层之上形成经图案化的抗蚀剂层；
在所述经图案化的抗蚀剂层内的所述种子层之上形成接触焊盘；
在形成所述接触焊盘之后，去除所述经图案化的抗蚀剂层，以露出所述种子层的在所述经图案化的抗蚀剂层之下的部分；以及
在所述种子层的露出的所述部分之上形成保护层。
2.根据权利要求1所述的方法，其中所述保护层包括酰亚胺层。
3.根据权利要求1所述的方法，其中所述保护层覆盖露出的所述种子层的顶表面以及所述接触焊盘的侧壁。
4.根据权利要求1所述的方法，还包括：
将所述半导体衬底的所述第一侧安装到载体上；以及
对所述半导体衬底和所述载体进行单片化，以形成多个半导体裸片。
5.根据权利要求1所述的方法，其中所述接触焊盘是垂直器件的共用源极接触。
6.根据权利要求1所述的方法，其中将所述种子层作为地毯式覆盖层而形成在所述半导体衬底的整个主表面之上。
7.一种用于形成半导体器件的方法，所述方法包括：
在半导体衬底的第一侧之上形成种子层，所述半导体衬底在所述第一侧处包括器件区域；
在所述种子层之上形成接触焊盘，同时露出所述种子层的与所述接触焊盘相邻的部分；
在所述种子层的露出的所述部分之上形成保护层；
将膏剂涂覆在半导体衬底之上，所述膏剂覆盖所述保护层；
通过固化所述膏剂，来形成陶瓷载体；以及
通过使用所述陶瓷载体作为载体，来处理所述半导体衬底。
8.根据权利要求7所述的方法，其中所述种子层包括铜层。
9.根据权利要求7所述的方法，还包括：在形成所述种子层之前形成阻挡层。
10.根据权利要求7所述的方法，其中将所述种子层作为地毯式覆盖层而形成在所述半导体衬底的整个主表面之上。
11.根据权利要求7所述的方法，其中所述接触焊盘为垂直器件的共用源极接触。
12.根据权利要求7所述的方法，其中所述膏剂包括基于水的混合物。
13.根据权利要求7所述的方法，还包括：在减薄所述半导体衬底之后，减薄所述陶瓷衬底，以露出布置在所述半导体衬底之上的接触焊盘。
14.根据权利要求7所述的方法，还包括：对所述陶瓷载体和所述半导体衬底进行单片化，以形成半导体芯片。
15.根据权利要求7所述的方法，其中固化所述膏剂包括：对所述膏剂进行烧结。
16.根据权利要求15所述的方法，其中所述烧结在350℃至约450℃下执行。
17.根据权利要求7所述的方法，其中形成所述陶瓷载体包括：在固化所述膏剂之后，平坦化所述膏剂。
18.根据权利要求7所述的方法，其中所述平坦化使得经固化的所述膏剂的厚度减小至少50％。
19.一种半导体器件，包括：
芯片，包括：
经划片的半导体衬底；
种子层，布置在所述经划片的半导体衬底的整个主表面之上，并且与所述经划片的半导体衬底的整个主表面重叠；
经图案化的接触焊盘，布置在所述种子层的部分之上，并且覆盖所述种子层的所述部分；以及
经划片的载体材料，布置在所述经划片的半导体衬底之上，并且布置在所述经图案化的接触焊盘的侧壁处。
20.根据权利要求19所述的器件，其中所述经划片的载体包括经烧结的陶瓷材料。
21.根据权利要求20所述的器件，其中所述经烧结的陶瓷材料包括氧化硅、氧化铝、氧化镁、氧化钛、和填充聚合物的有机化合物材料。
22.根据权利要求20所述的器件，还包括：
裸片底座，其中所述接触焊盘布置在所述裸片底座上，其中所述接触焊盘布置在所述经划片的半导体衬底与所述裸片底座之间；
第一互连，将第一引线与所述经划片的半导体衬底的第一背侧接触相耦合；以及
第二互连，将第二引线与所述经划片的半导体衬底的第二背侧接触相耦合。
23.根据权利要求22所述的器件，其中所述接触焊盘为共用源极接触。
24.一种用于形成半导体器件的方法，所述方法包括：
在半导体衬底中形成器件区域，所述半导体衬底包括第一侧和第二侧，其中所述器件区域与所述第一侧邻近地形成；
将所述半导体衬底的所述第一侧安装到载体上；以及
对所述半导体衬底和所述载体进行单片化，以形成多个半导体裸片。
25.根据权利要求24所述的方法，还包括：
将所述载体安装到处理工具的卡盘上；以及
对所述半导体衬底的所述第二侧执行处理。
26.根据权利要求25所述的方法，其中执行所述处理包括：执行背侧研磨工艺，以减薄所述半导体衬底。
27.根据权利要求24所述的方法，其中将所述半导体衬底安装到所述载体上包括：
在所述第一侧之上涂覆膏剂；
固化所述膏剂，从而形成包括非平坦表面的隔离衬底；以及
平坦化所述隔离衬底，以形成平坦的表面。
28.根据权利要求27所述的方法，还包括：通过将经平坦化的所述隔离衬底用作所述载体，而在所述半导体衬底的所述第二侧之上形成背侧金属化。
29.根据权利要求24所述的方法，还包括：在所述单片化之前，减薄所述载体。
30.一种用于形成半导体器件的方法，所述方法包括：
在半导体衬底之上涂覆膏剂；
通过固化所述膏剂，来形成陶瓷载体；以及
通过将所述陶瓷载体用作载体，而减薄所述半导体衬底。
31.根据权利要求30所述的方法，其中所述膏剂包括基于水的混合物。
32.根据权利要求30所述的方法，还包括：在减薄所述半导体衬底之后，减薄所述陶瓷载体，以露出布置在所述半导体衬底之上的接触焊盘。
33.根据权利要求30所述的方法，还包括：
对所述陶瓷载体和所述半导体衬底进行单片化，以形成半导体芯片。
34.根据权利要求30所述的方法，其中固化所述膏剂包括：烧结所述膏剂。
35.根据权利要求34所述的方法，其中所述烧结在350℃至约450℃下执行。
36.根据权利要求30所述的方法，其中形成所述陶瓷载体包括：在固化所述膏剂之后，平坦化所述膏剂。
37.根据权利要求36所述的方法，其中所述平坦化将经固化的所述膏剂的厚度减小至少50％。
38.根据权利要求36所述的方法，其中在所述平坦化期间，在真空中处理所述衬底。
39.根据权利要求36所述的方法，其中减薄所述半导体衬底包括：在未安装到划片胶带上的情况下，进行减薄。
40.根据权利要求36所述的方法，还包括：
将所述衬底和所述陶瓷载体安装到划片胶带上；以及
对所述衬底和所述陶瓷衬底进行划片。
41.根据权利要求40所述的方法，其中在将所述半导体衬底和所述陶瓷载体安装到所述划片胶带上之前，减薄所述衬底。
42.根据权利要求40所述的方法，其中在将所述半导体衬底和所述陶瓷载体安装到所述划片胶带上之后，减薄所述衬底。
43.一种半导体芯片，包括：
经划片的半导体衬底；以及
经划片的载体，布置在所述半导体衬底之上。
44.根据权利要求43所述的芯片，其中所述经划片的载体的厚度大于所述经划片的半导体衬底的厚度。
45.根据权利要求43所述的芯片，其中所述经划片的载体包括经烧结的陶瓷材料。
46.根据权利要求45所述的芯片，其中所述经烧结的陶瓷材料包括氧化硅、氧化铝、氧化镁、氧化钛、和填充聚合物的有机化合物材料。
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