CN105334085A - Sample preparation method and secondary ion mass spectrometry method - Google Patents
Sample preparation method and secondary ion mass spectrometry method Download PDFInfo
- Publication number
- CN105334085A CN105334085A CN201410395360.6A CN201410395360A CN105334085A CN 105334085 A CN105334085 A CN 105334085A CN 201410395360 A CN201410395360 A CN 201410395360A CN 105334085 A CN105334085 A CN 105334085A
- Authority
- CN
- China
- Prior art keywords
- conductor chip
- semi
- perforate
- geodesic structure
- sample preparation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Sampling And Sample Adjustment (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a sample preparation method, which comprises the following steps: a semiconductor chip is provided and the semiconductor chip contains several regularly-arranged structures to be measured; the front of the semiconductor chip is peeled off, and position distribution of the structures to be measured is judged; cross section of the semiconductor chip undergoes corrosion treatment, and depth of the structures to be measured and width on the cross section of the structures to be measured are judged; the front of the semiconductor chip is provided with at least one hole according to the position distribution, depth and width of the structures to be measured, the holes are positioned in at least two side surfaces of one of the structures to be measured, and depth of the holes is greater than or equal to depth of the structures to be measured; and the back of the semiconductor chip is ground until the holes are exposed, so as to obtain an analytical sample. The invention also provides a secondary ion mass spectrometry method for using the analytical sample. The analytical sample has flat surface and large analysis area, which are beneficial to raise test analysis accuracy.
Description
Technical field
The present invention relates to semiconductor test analysis technical field, particularly relate to a kind of sample preparation methods and SIMS analysis method.
Background technology
Semiconductor manufacturing is the process that a technique is extremely complicated, in whole semiconductor fabrication, needs to carry out various detection to manufactured product, to determine whether manufactured product meets designing requirement, and then ensures the quality of semiconductor product.
Such as, ion implantation is a procedure very important in semiconductor manufacturing.Ion implantation comprises dissimilar ion implantation, typically the injection of N-type ion and the injection of P type ion.In semiconductor fabrication in N-type ion implantation based on phosphorus (P) and arsenic (As), P type ion is based on boron (B) and indium (In).Ion implantation is carried out in the reaction chamber of sealing.Mostly current reaction chamber is arc electricity reaction chamber, when carrying out ion implantation, the wafer of ion gun and pre-note ion being put into reaction chamber, then ionizes ion, screened by electromagnetic field to ion, improve the ion energy of screening simultaneously, be finally injected into wafer.When being screened ionization by electromagnetic field, electromagnetic field is screened the ion in reaction chamber by specific charge.When carrying out this ion screening, easily the Ion Phase ion together of specific charge and prescreen being falsely dropped middle injection wafer, injection ion so just can be made to be subject to the pollution of other ions.
Whether there are other contaminated ions to detect the ion injecting wafer, often utilize the technology of SIMS analysis at present.SIMS analysis (SecondaryIonMassSpectroscopy, be called for short SIMS) be utilize analytical reagent composition to sputter the secondary ion of generation by institute after the incident target of primary ion, thus a kind of analytical approach of acquisition material surface or depth section element information.SIMS can analyze the whole elements comprising hydrogen also can provide isotopic information, analysis of compounds component and molecular structure.The method of SIMS analysis has very high sensitivity, ppm (partpermillion can be reached, namely 1,000,000/) magnitude of even ppb (partperbillion, namely part per billion), is therefore widely used in the analysis field of material.
Due to SIMS analysis, have certain requirement: first to sample, the surface of sample should keep clean and smooth as far as possible; Secondly, sample need reserve enough analyzed area areas; In addition, sample need have good electric conductivity.But, in the prior art, for some specific samples (samples as some all technological processes), the front of sample is too coarse, analyzed area is little or poorly conductive, and the precision of analysis of secondary ion mass spectrum and reference value are reduced greatly.
Summary of the invention
The object of the invention is to, a kind of sample preparation methods and SIMS analysis method are provided, improve the accuracy of test analysis.
For solving the problems of the technologies described above, the invention provides a kind of sample preparation methods, comprising:
There is provided one to be formed with some regularly arranged semi-conductor chips treating geodesic structure, described semi-conductor chip comprise front, with the back side of described vis-a-vis and the xsect perpendicular to described front and back;
The front of described semi-conductor chip is peeled off, treats the last layer rete of geodesic structure place rete described in peeling off extremely, according to the described structure treating the last layer rete of geodesic structure place rete, described in judgement, treat the position distribution of geodesic structure;
Corrosion treatment is carried out to the xsect of described semi-conductor chip, according to the result of described corrosion treatment, treat described in judgement geodesic structure the degree of depth and described in treat the width of geodesic structure at described xsect;
According to described position distribution, the degree of depth and the width for the treatment of geodesic structure, at least one perforate is prepared from the front of described semi-conductor chip, described perforate is positioned at least two sides for the treatment of geodesic structure described in one of them, treats the degree of depth of geodesic structure described in the degree of depth of described perforate is more than or equal to;
The back side of described semi-conductor chip is ground, until expose described perforate, obtains analyzing sample.
Optionally, in described sample preparation methods, prepare between the step of at least one perforate and the step that the back side of described semi-conductor chip is ground in the front of described semi-conductor chip, also comprise:
Filled conductive material in described perforate.
Optionally, in described sample preparation methods, described conductive material is platinum.
Optionally, in described sample preparation methods, carry out, between the step of corrosion treatment, also comprising in the step peeled off the front of described semi-conductor chip with to the xsect of described semi-conductor chip:
Focused ion beam is adopted to carry out pre-service to the xsect of described semi-conductor chip.
Optionally, in described sample preparation methods, prepare between the step of at least one perforate and the step that the back side of described semi-conductor chip is ground in the front of described semi-conductor chip, also comprise:
A substrate is pasted in the front of described semi-conductor chip.
Optionally, in described sample preparation methods, described substrate is electrically-conductive backing plate, and described semi-conductor chip and described electrically-conductive backing plate are pasted by conducting resinl.
Optionally, in described sample preparation methods, the step that the back side of described semi-conductor chip is ground is comprised:
The back side of described semi-conductor chip is roughly ground, until the backside surface of described semi-conductor chip is apart from described perforate 50nm ~ 1000nm;
Fine grinding is carried out to the back side of described semi-conductor chip, exposes described perforate.
Optionally, in described sample preparation methods, described semi-conductor chip comprises some stacked retes, described in treat geodesic structure arrangement in described rete wherein.
Optionally, in described sample preparation methods, the treating fluid of described corrosion treatment comprises the combination of one or more in hydrofluorite, nitric acid and acetic acid, and the processing time of described corrosion treatment is 10s ~ 30s.
Optionally, in described sample preparation methods, prepare a described perforate in the front of described semi-conductor chip, described perforate is annular, and surrounds described one and treat geodesic structure.
Optionally, in described sample preparation methods, prepare four described perforates in the front of described semi-conductor chip, described perforate is bar shaped, and four described perforates are centered around a described surrounding treating geodesic structure.
Optionally, in described sample preparation methods, focused ion beam is adopted to prepare at least one described perforate in the front of described semi-conductor chip.
According to another side of the present invention, a kind of SIMS analysis method is also provided, comprises:
The employing as above described analysis sample prepared of sample preparation methods described in any one is provided;
A described position for the treatment of geodesic structure is determined according to described perforate;
From the one side that described analysis sample was polished, treat that geodesic structure carries out SIMS analysis to described one.
Compared with prior art, sample preparation methods provided by the invention and SIMS analysis method have the following advantages:
In sample preparation methods provided by the invention, the front of described semi-conductor chip is peeled off, and after corrosion treatment is carried out to the xsect of described semi-conductor chip, at least one perforate is prepared in the front of described semi-conductor chip, described perforate is positioned at least two sides for the treatment of geodesic structure described in one of them, treat geodesic structure to locate described in one of them, treat the degree of depth of geodesic structure described in the degree of depth of described perforate is more than or equal to, thus orient the position and the degree of depth of described in one, treating geodesic structure; Then, the back side of described semi-conductor chip is ground, until expose described perforate, obtain analyzing sample, then according to described perforate, a described position for the treatment of geodesic structure can be determined.Through grinding, the smooth surface of described analysis sample; Further, the back side of described semi-conductor chip relatively cleaner, does not have too much interference structure, makes the analyzed area of described analysis sample larger.Thus, SIMS analysis can be carried out from the back side of described semi-conductor chip, thus improve the accuracy of SIMS analysis.
Accompanying drawing explanation
Fig. 1 is the process flow diagram of sample preparation methods in one embodiment of the invention;
Fig. 2-Figure 10 is the schematic diagram of the process chips structure of the sample preparation methods of one embodiment of the invention;
Figure 11 is the scanning electron microscope diagram sheet after the xsect of semi-conductor chip carries out corrosion treatment;
Figure 12 is the schematic diagram that the employing SIMS analysis of one embodiment of the invention treats geodesic structure; .
Figure 13 is the schematic diagram of perforate in another embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, sample preparation methods of the present invention and SIMS analysis method are described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is, provides a kind of sample preparation methods, comprising:
Step S11: provide one to be formed with some regularly arranged semi-conductor chips treating geodesic structure, described semi-conductor chip comprise front, with the back side of described vis-a-vis and the xsect perpendicular to described front and back;
Step S12: peel off the front of described semi-conductor chip, treats the last layer rete of geodesic structure place rete, according to the described structure treating the last layer rete of geodesic structure place rete, treats the position distribution of geodesic structure described in judgement described in peeling off extremely;
Step S13: corrosion treatment is carried out to the xsect of described semi-conductor chip, according to the result of described corrosion treatment, treat described in judgement geodesic structure the degree of depth and described in treat the width of geodesic structure at described xsect;
Step S14: according to described position distribution, the degree of depth and the width for the treatment of geodesic structure, at least one perforate is prepared from the front of described semi-conductor chip, described perforate is at least positioned at two sides for the treatment of geodesic structure described in one of them, treats the degree of depth of geodesic structure described in the degree of depth of described perforate is more than or equal to;
Step S15: grind the back side of described semi-conductor chip, until expose described perforate, obtains analyzing sample.
Through grinding, the smooth surface of described analysis sample; Further, the back side of described semi-conductor chip relatively cleaner, does not have too much interference structure, makes the analyzed area of described analysis sample larger.Thus, SIMS analysis can be carried out from the back side of described semi-conductor chip, thus improve the accuracy of SIMS analysis.
According to core concept of the present invention, a kind of SIMS analysis method is also provided, comprises:
Step S21: the described analysis sample adopting sample preparation methods described above to prepare is provided;
Step S22: determine a described position for the treatment of geodesic structure according to described perforate;
To described one, step S23: the one side be polished from described analysis sample, treats that geodesic structure carries out SIMS analysis.
Below, refer to Fig. 1-Figure 10 and illustrate sample preparation methods of the present invention, in the present embodiment, treat that geodesic structure is described for P trap for described, described analysis sample has carried out for analyzing the pollution whether described P trap is subject to other ions.
First, as shown in Figure 1, carry out step S11, provide semiconductor chip (chip) 1, as shown in Figure 2, Fig. 2 is the schematic diagram of the xsect of described semi-conductor chip 1.Described semi-conductor chip 1 comprises some regularly arranged P traps 111.In the present embodiment, described semi-conductor chip 1 comprises some stacked retes, be respectively: substrate layer (substrate) 100, epitaxial loayer (epitaxiallayer, be called for short EPI) 110, grid layer 120, first interconnection layer 130, second interconnection layer 140, top interconnect layer 150 and spacer layer 160, stacked rete is not limited to above-mentioned rete, and those of ordinary skill in the art can select required rete as required, and therefore not to repeat here.
Wherein, have described P trap 111, the N trap 112 regularly carrying out arranging in described epitaxial loayer 110 and be arranged in a part of described P trap 111, N-type heavily doped region 113 is positioned at described N trap 112, P type heavily doped region 114 and is positioned at P trap 111 described in another part.The queueing discipline of described P trap 111 sets according to the needs of device, and concrete queueing discipline does not limit in the present invention, and this is what it will be appreciated by those skilled in the art that.Described grid layer 120 comprises grid 121 and connection plug 122, and described grid 121 and through hole connection plug 122 are isolated by dielectric layer 123.Groove (trench) and through hole (via) can be comprised in described first interconnection layer 130, second interconnection layer 140, top interconnect layer 150, in described groove and through hole, fill metal, thus realize interconnection.
Described semi-conductor chip 1 comprises front 11, the back side 12 relative with described front 11 and xsect, and described cross-section normal is in described front 11 and the back side 12.The side that described semi-conductor chip 1 has a described substrate layer 100 is the back side 12 of described semi-conductor chip 1, and the side that described semi-conductor chip 1 deviates from described substrate layer 100 is the front 11 of described semi-conductor chip 1.In the present embodiment, described xsect is a side of described semi-conductor chip 1, and in other embodiments of the invention, also can do a section on described semi-conductor chip 1, described section is as described xsect.
Then carry out step S12, as shown in Figure 3, the front 11 of described semi-conductor chip 1 is peeled off, peel off the last layer rete (described grid layer 120) to described P trap 111 place rete (described epitaxial loayer 110).Fig. 3 is the schematic diagram of the xsect after described semi-conductor chip 1 is peeled off.In the present embodiment, because described P trap 111 place rete is positioned at the below of described grid 121, so, according to the position of described grid 121, the Position Approximate of described P trap 111 can be judged.As shown in Figure 4, schematic diagram when Fig. 4 is the described semi-conductor chip 1 of Fig. 3 overlooking under Electronic Speculum.Because described grid 121 and connection plug 122 all conduct electricity, so under Electronic Speculum, described grid 121 and connection plug 122 can be observed.In the diagram, according to the position of described grid 121, can judge the position that described P trap 111 dotted line frame in the diagram fences up, thus obtain the position distribution of described P trap 111 on described semi-conductor chip 1.The xsect of described semi-conductor chip 1 is positioned at a side of described semi-conductor chip 1, such as in the present embodiment, schematic diagram when Fig. 4 is described semi-conductor chip 1 overlooking under Electronic Speculum, then viewed from the direction of arrow, just can obtain the xsect of described semi-conductor chip 1 as shown in Figure 3 from Fig. 4.
Preferably, between step S12 and step S13, adopt the xsect of focused ion beam to described semi-conductor chip 1 to carry out pre-service, make the xsect of described semi-conductor chip 1 more smooth.
Then, carry out step S13, corrosion treatment is carried out to the xsect of described semi-conductor chip 1.After carrying out corrosion treatment to the xsect of described semi-conductor chip 1, device architectures different in described epitaxial loayer 110 can obtain different treatment effects, and under Electronic Speculum, different device architectures can present the different degree of depth.In the present embodiment, described P trap 111 and the degree of depth Butut of described epitaxial loayer 110 under Electronic Speculum not carrying out ion implantation, with reference to Figure 11, Figure 11 is the scanning electron microscope diagram sheet after the xsect of semi-conductor chip carries out corrosion treatment, that obviously can find out the border of described P trap 111 than the described epitaxial loayer 110 carrying out ion implantation from Figure 11 is of light color, thus can according to the result of described corrosion treatment, judge described P trap 111 the degree of depth and described in treat the width of geodesic structure at described xsect.Preferably, in the present embodiment, described corrosion treatment is acid treatment, and described acid-treated treating fluid can comprise the combination of one or more in hydrofluorite, nitric acid and acetic acid, and the processing time of described corrosion treatment is preferably 10s ~ 30s, such as 20s.But the treating fluid of described corrosion treatment and processing time are not limited to above-mentioned scope of disclosure, can treat that geodesic structure is selected according to concrete.
Subsequently, carry out step S14, the position distribution treating geodesic structure according to described, the degree of depth and described in treat the width of geodesic structure at described xsect, at least one perforate is prepared in the front 11 of described semi-conductor chip 1, described perforate is positioned at least two sides for the treatment of geodesic structure described in one of them, treats geodesic structure to locate described in one of them.General, select to treat that geodesic structure 111 positions described in a centre position, as shown in Figure 5, select to treat geodesic structure 111 described in empty wire frame positions, treat described in empty wire frame positions in Fig. 5 that geodesic structure 111 is away from described semi-conductor chip 1, can not be damaged in step S12 and step S13.In the present embodiment, prepare a described perforate 125, as shown in Figure 5, Fig. 5 is the vertical view after described semi-conductor chip 1 prepares described perforate 125, described perforate 125 is annular, and described perforate 125 is surrounded described one and treated geodesic structure 125, thus treats that geodesic structure 125 is positioned the centre of described perforate 125 by described one, as long as see described perforate 125, just can judge that described one is treated that geodesic structure 125 is positioned at the centre of described perforate 125.
As shown in Figure 6, Fig. 6 is the schematic diagram that described semi-conductor chip 1 prepares the xsect after described perforate 125, the degree of depth of described perforate 125 is more than or equal to the degree of depth of described P trap 111, i.e. the bottom surface of described perforate 125 is greater than the distance H2 of bottom surface apart from the back side 12 of described semi-conductor chip 1 of described P trap 111 apart from the distance H1 at the back side 12 of described semi-conductor chip 1.Due to, described perforate 125 is surrounded described one and is treated geodesic structure 125, so the inner ring width W1 of described perforate 125 is greater than the width W 2 of described P trap 111 at described xsect, and the process preparing described perforate 125 can not pollute described P trap 111.Preferably, adopt focused ion beam to prepare described perforate 125 in the front 11 of described semi-conductor chip 1, certainly, described perforate 125 can also be prepared by methods such as etchings.
Preferably, as shown in Figure 7, filled conductive material 126 in described perforate 125, elemental metals or the alloys such as such as platinum, copper, aluminium, described conductive material 126 is conducive to the electric conductivity improving described analysis sample, thus improves the accuracy of test further.
In the present embodiment, as shown in Figure 8, a substrate 2 is pasted in the front 11 of described semi-conductor chip 1, described semi-conductor chip 1 is supported when grinding in step S15 to facilitate, the size of described substrate 2 can need to select, and such as, described substrate 2 can be the square plate of 1cm*1cm.Preferably, described substrate 2 is electrically-conductive backing plate, such as blank wafer etc., can improve the electric conductivity of described analysis sample.Described semi-conductor chip 1 and described electrically-conductive backing plate 2 are pasted by conducting resinl 11.
Then, carry out step S15, the back side 12 of described semi-conductor chip 1 is ground, until expose described perforate 125.Preferably, described step S15 is divided into following two sub-steps:
Sub-step S151, as shown in Figure 9, roughly grind the back side 12 of described semi-conductor chip 1, the abrasive media utilizing roughness larger grinds, until when the surface, the back side 12 of described semi-conductor chip 1 is 50nm ~ 1000nm with the distance H3 of described perforate 125, stop corase grind;
Sub-step S152, as shown in Figure 10, carries out fine grinding to the back side 12 of described semi-conductor chip 1, and the abrasive media (such as masonry cream) utilizing roughness less grinds, and such as, until expose described perforate 125, obtains analyzing sample 3.The degree of depth due to described perforate 125 is more than or equal to the degree of depth of described P trap 111, so when exposing described perforate 125, described P trap 111 just exposes or also do not expose, not P trap 111 described in easy damaged, thus improves the accuracy of test.And adopt the method for first corase grind, rear fine grinding, both can improve grinding efficiency, and can avoid again damaging described P trap 111.
The surface that described analysis sample 3 was polished, as analysis surface during test, because this surface was polished, so the analysis surfacing of described analysis sample 3, is conducive to the accuracy improving test.And, the back side 12 of described semi-conductor chip 1 cleaner, there is no too much interference structure (such as described grid 121, connection plug 122, interconnection structure etc.), the analyzed area 31 of described analysis sample 3 is made (to be positioned on surface that described analysis sample 3 was polished, and be positioned at the centre of described perforate 125) comparatively large, thus improve the accuracy analyzed.
In addition, the present invention also provides a kind of SIMS analysis method, specifically comprises:
First, carry out step S21, described analysis sample 3 is provided;
Then, carry out step S22, determine the position of described P trap 111 according to described perforate 125, in the present embodiment, the one side that described analysis sample 3 was polished finds described perforate 125, be positioned at the centre of described perforate 125 by the described P trap 111 of locating;
Finally, carry out step S23, from the one side that described analysis sample 3 was polished, treat that geodesic structure carries out SIMS analysis to described one.Concrete, by the analyzed area 31 of the incident described analysis sample 3 of primary ion 41, sputtering produces secondary ion 42, detects the information of described secondary ion 42, and analyzes.
Preferred embodiment of the present invention is described above, but the present invention is not limited to above-mentioned open scope, such as:
The number of described perforate is not limited to 1, the shape of described perforate is also not limited to annular, in another embodiment of the invention, the number of described perforate can also be 4, as shown in figure 13, described perforate 225 is bar shaped, and four described perforates 225 are centered around a described surrounding treating geodesic structure 111, thus orients a described position for the treatment of geodesic structure 111.Certainly, the number of described perforate can also be 2,3 or more; In addition, the shape of described perforate can also be circular port, some circular ports are arranged in described at least two sides for the treatment of geodesic structure, such as, some circular ports are arranged in described one and treat two of geodesic structure adjacent sides, or some circular ports are arranged in described one and treat two of geodesic structure relative sides, or, some circular ports are arranged in a described surrounding treating geodesic structure, etc.; As long as described perforate is positioned at described at least two sides for the treatment of geodesic structure, a described position for the treatment of geodesic structure 111 all can be oriented, also within thought range of the present invention;
In addition, describedly treat that geodesic structure is not limited to as P type trap, it can also be the structure of Else Rule arrangement, according to above-mentioned statement of the present invention, said method can be applied to the analysis field of ion diffuse by those of ordinary skill in the art, this is what it will be appreciated by those skilled in the art that, and therefore not to repeat here.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (13)
1. a sample preparation methods, comprising:
There is provided one to be formed with some regularly arranged semi-conductor chips treating geodesic structure, described semi-conductor chip comprise front, with the back side of described vis-a-vis and the xsect perpendicular to described front and back;
The front of described semi-conductor chip is peeled off, treats the last layer rete of geodesic structure place rete described in peeling off extremely, according to the described structure treating the last layer rete of geodesic structure place rete, described in judgement, treat the position distribution of geodesic structure;
Corrosion treatment is carried out to the xsect of described semi-conductor chip, according to the result of described corrosion treatment, treat described in judgement geodesic structure the degree of depth and described in treat the width of geodesic structure at described xsect;
According to described position distribution, the degree of depth and the width for the treatment of geodesic structure, at least one perforate is prepared from the front of described semi-conductor chip, described perforate is positioned at least two sides for the treatment of geodesic structure described in one of them, treats the degree of depth of geodesic structure described in the degree of depth of described perforate is more than or equal to;
The back side of described semi-conductor chip is ground, until expose described perforate, obtains analyzing sample.
2. sample preparation methods as claimed in claim 1, is characterized in that, prepare between the step of at least one perforate and the step of grinding the back side of described semi-conductor chip, also comprise in the front of described semi-conductor chip:
Filled conductive material in described perforate.
3. sample preparation methods as claimed in claim 2, it is characterized in that, described conductive material is platinum.
4. as the sample preparation methods in claim 1-3 as described in any one, it is characterized in that, carry out, between the step of corrosion treatment, also comprising in the step peeled off the front of described semi-conductor chip with to the xsect of described semi-conductor chip:
Focused ion beam is adopted to carry out pre-service to the xsect of described semi-conductor chip.
5. as the sample preparation methods in claim 1-3 as described in any one, it is characterized in that, prepare between the step of at least one perforate and the step that the back side of described semi-conductor chip is ground from the front of described semi-conductor chip, also comprise:
A substrate is pasted in the front of described semi-conductor chip.
6. sample preparation methods as claimed in claim 5, it is characterized in that, described substrate is electrically-conductive backing plate, and described semi-conductor chip and described electrically-conductive backing plate are pasted by conducting resinl.
7. as the sample preparation methods in claim 1-3 as described in any one, it is characterized in that, the step that the back side of described semi-conductor chip is ground comprised:
The back side of described semi-conductor chip is roughly ground, until the backside surface of described semi-conductor chip is apart from described perforate 50nm ~ 1000nm;
Fine grinding is carried out to the back side of described semi-conductor chip, exposes described perforate.
8. sample preparation methods as claimed in claim 1, it is characterized in that, described semi-conductor chip comprises some stacked retes, described in treat geodesic structure arrangement in a described rete wherein.
9. sample preparation methods as claimed in claim 1, it is characterized in that, the treating fluid of described corrosion treatment comprises the combination of one or more in hydrofluorite, nitric acid and acetic acid, and the processing time of described corrosion treatment is 10s ~ 30s.
10. sample preparation methods as claimed in claim 1, is characterized in that, prepare a described perforate from the front of described semi-conductor chip, and described perforate be annular, and surrounds described one and treat geodesic structure.
11. sample preparation methods as claimed in claim 1, is characterized in that, prepare four described perforates from the front of described semi-conductor chip, described perforate is bar shaped, and four described perforates are centered around a described surrounding treating geodesic structure.
12. sample preparation methods as claimed in claim 1, is characterized in that, adopt focused ion beam to prepare at least one described perforate in the front of described semi-conductor chip.
13. 1 kinds of SIMS analysis methods, comprising:
There is provided adopt as sample preparation methods as described in any one in claim 1-12 prepare as described in analyze sample;
A described position for the treatment of geodesic structure is determined according to described perforate;
From the one side that described analysis sample was polished, treat that geodesic structure carries out SIMS analysis to described one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410395360.6A CN105334085B (en) | 2014-08-12 | 2014-08-12 | Sample preparation methods and SIMS analysis method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410395360.6A CN105334085B (en) | 2014-08-12 | 2014-08-12 | Sample preparation methods and SIMS analysis method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105334085A true CN105334085A (en) | 2016-02-17 |
| CN105334085B CN105334085B (en) | 2018-03-20 |
Family
ID=55284737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410395360.6A Active CN105334085B (en) | 2014-08-12 | 2014-08-12 | Sample preparation methods and SIMS analysis method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105334085B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105910866A (en) * | 2016-04-20 | 2016-08-31 | 中国科学院地质与地球物理研究所 | Apparatus for preparing ion probe indium target and preparation method of the ion probe indium target |
| CN108267348A (en) * | 2017-12-29 | 2018-07-10 | 北京智芯微电子科技有限公司 | The nano high-precision preparation method of IC product cross sections |
| CN109148315A (en) * | 2018-08-27 | 2019-01-04 | 苏州芯联成软件有限公司 | The discriminating conduct of two through-hole between metallic layers connection in a kind of chip |
| CN111812139A (en) * | 2020-07-06 | 2020-10-23 | 长江存储科技有限责任公司 | Chip internal structure analysis method and sample bearing device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1123479A (en) * | 1997-07-08 | 1999-01-29 | Nippon Steel Corp | Method for inspecting surface flaw of welded part of steel pipe |
| KR20010066141A (en) * | 1999-12-31 | 2001-07-11 | 황인길 | a manufacturing method of semiconductor devices |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN102565680A (en) * | 2010-12-27 | 2012-07-11 | 无锡华润上华半导体有限公司 | Failure analysis method for semiconductor device |
| CN102856247A (en) * | 2011-06-30 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Back silicon through hole making method |
| CN102854429A (en) * | 2011-06-28 | 2013-01-02 | 上海华碧检测技术有限公司 | Failure point positioning method for semiconductor power device failure analysis |
| CN103913358A (en) * | 2014-04-10 | 2014-07-09 | 武汉新芯集成电路制造有限公司 | Preparation method and failure analysis method for transmission electron microscope (TEM) sample |
-
2014
- 2014-08-12 CN CN201410395360.6A patent/CN105334085B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1123479A (en) * | 1997-07-08 | 1999-01-29 | Nippon Steel Corp | Method for inspecting surface flaw of welded part of steel pipe |
| KR20010066141A (en) * | 1999-12-31 | 2001-07-11 | 황인길 | a manufacturing method of semiconductor devices |
| CN102253325A (en) * | 2010-05-21 | 2011-11-23 | 中芯国际集成电路制造(上海)有限公司 | Method for analyzing chip failure |
| CN102565680A (en) * | 2010-12-27 | 2012-07-11 | 无锡华润上华半导体有限公司 | Failure analysis method for semiconductor device |
| CN102854429A (en) * | 2011-06-28 | 2013-01-02 | 上海华碧检测技术有限公司 | Failure point positioning method for semiconductor power device failure analysis |
| CN102856247A (en) * | 2011-06-30 | 2013-01-02 | 中芯国际集成电路制造(上海)有限公司 | Back silicon through hole making method |
| CN103913358A (en) * | 2014-04-10 | 2014-07-09 | 武汉新芯集成电路制造有限公司 | Preparation method and failure analysis method for transmission electron microscope (TEM) sample |
Non-Patent Citations (2)
| Title |
|---|
| LEI ZHU ET AL.: "SIMS Sample Preparation Mehtod for GOX Analysis with Small-Size Polysilicon Patterns", 《PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS》 * |
| 赵春荣: "深亚微米集成电路的失效定位技术", 《万方学位论文》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105910866A (en) * | 2016-04-20 | 2016-08-31 | 中国科学院地质与地球物理研究所 | Apparatus for preparing ion probe indium target and preparation method of the ion probe indium target |
| CN108267348A (en) * | 2017-12-29 | 2018-07-10 | 北京智芯微电子科技有限公司 | The nano high-precision preparation method of IC product cross sections |
| CN109148315A (en) * | 2018-08-27 | 2019-01-04 | 苏州芯联成软件有限公司 | The discriminating conduct of two through-hole between metallic layers connection in a kind of chip |
| CN109148315B (en) * | 2018-08-27 | 2020-11-10 | 苏州芯联成软件有限公司 | Method for distinguishing through hole connection between two metal layers in chip |
| CN111812139A (en) * | 2020-07-06 | 2020-10-23 | 长江存储科技有限责任公司 | Chip internal structure analysis method and sample bearing device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105334085B (en) | 2018-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Williams et al. | Identifying parasitic current pathways in CIGS solar cells by modelling dark J–V response | |
| Moseley et al. | Recombination by grain-boundary type in CdTe | |
| CN105334085A (en) | Sample preparation method and secondary ion mass spectrometry method | |
| US10101246B2 (en) | Method of preparing a plan-view transmission electron microscope sample used in an integrated circuit analysis | |
| CN103808540B (en) | Transmission electron microscope sample preparation method | |
| Alberi et al. | Measuring long-range carrier diffusion across multiple grains in polycrystalline semiconductors by photoluminescence imaging | |
| US20060138323A1 (en) | Method of Applying Micro-Protection in Defect Analysis | |
| CN101625302B (en) | Method for preparing transmission electron microscope sample | |
| Bauer et al. | Avalanche breakdown in multicrystalline solar cells due to preferred phosphorous diffusion at extended defects | |
| Young et al. | Dual-beam (FIB-SEM) systems: techniques and automated applications | |
| CN105046007A (en) | Positioning method for reverse engineering of integrated circuit chip | |
| US20220349843A1 (en) | Detection Method for the Radiation-induced Defects of Oxide Layer in Electronic Devices | |
| Raghuwanshi et al. | Influence of boron clustering on the emitter quality of implanted silicon solar cells: an atom probe tomography study | |
| Kwapil et al. | Influence of surface texture on the defect‐induced breakdown behavior of multicrystalline silicon solar cells | |
| CN101055848A (en) | A test structure and method for detecting charge effects using a delayed inversion point technique | |
| US20210028033A1 (en) | System and method for analyzing a semiconductor device | |
| CN106290544B (en) | A kind of SIMS analysis method | |
| CN104037106A (en) | Method for semiconductor chip failure analysis | |
| Bender et al. | Surface contamination and electrical damage by focused ion beam: conditions applicable to the extraction of TEM lamellae from nanoelectronic devices | |
| CN111855706B (en) | Method for detecting radiation-induced displacement defect of semiconductor material | |
| Clement et al. | Microscopy needs for next generation devices characterization in the semiconductor industry | |
| Vivet et al. | Electrical homo-junction delineation techniques: A comparative study | |
| CN103811410B (en) | The method finding through hole Weak link | |
| Forcolin | Development and simulation of 3D diamond detectors | |
| Michałowski et al. | A-Crater-within-a-Crater Approach for Secondary Ion Mass Spectrometry Evaluation of the Quality of Interfaces of Multilayer Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |