CN105320040B - Power-on time sequence control circuit, control method, electric supply installation and electric terminal - Google Patents
Power-on time sequence control circuit, control method, electric supply installation and electric terminal Download PDFInfo
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- CN105320040B CN105320040B CN201510812561.6A CN201510812561A CN105320040B CN 105320040 B CN105320040 B CN 105320040B CN 201510812561 A CN201510812561 A CN 201510812561A CN 105320040 B CN105320040 B CN 105320040B
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- 238000009434 installation Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 title claims abstract description 11
- 230000005611 electricity Effects 0.000 claims description 16
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- 238000006243 chemical reaction Methods 0.000 claims description 7
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- 238000012986 modification Methods 0.000 description 3
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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Abstract
The present invention, which provides power-on time sequence control circuit, control method, electric supply installation and electric terminal, the circuit, to be included：Trigger element, including the first trigger and the second trigger；Two inputs of each trigger, which are connected to a delay circuit, makes the delay of out-put supply control signal for the delay sum of two input end signals, out-put supply drive signal is distinguished with driving power unit by the output signal of two triggers, delay inequality between each power driving signal forms the electrifying timing sequence of power subsystem, realizes accurately upper electric timing_delay estimation and safe electrifying timing sequence.
Description
Technical field
The present invention relates to power supply technical field, is filled more particularly to power-on time sequence control circuit, control method, power supply
Put and electric terminal.
Background technology
In more power electronic systems, IC chip integrated level improves, and complexity and quantity also greatly increase.It is more electric to ensure
Source electronic system normally upper electricity, and energy normal table reliably works, it is necessary to be controlled to power supply electrifying sequential.Meanwhile electricity
Source SECO is also even more important to the latch-up for eliminating complicated IC chip.Irrational electrifying timing sequence can influence IC chip
The job stability of working life and more power electronic systems.
In the prior art, controlling the scheme of the electrifying timing sequence of more power supplys mainly has following three kinds：The first is to utilize electricity
The Enable Pin control of source module；Second is to be controlled upper electricity by adjusting the time constant of power supply soft-start circuit；3rd
Kind is to utilize special electrifying timing sequence controller.
The first scheme is ended using the diode current flow of power supply output control series connection electric in prime, after directly controlling
The power circuit at end enables, this method to be mainly characterized by circuit simple, be adapted to two to be wanted substantially to three-way power and each power supply
Upper electricity when seeking common ground.Due to being simple diode as ON-OFF control circuit, the time delay of uncontrollable each road power supply electrifying, and
It is unreliable to work, and easily burns diode when power supply electrifying timing sequence itself and bigger desired value difference.
Second scheme is to be controlled upper electricity by adjusting the time constant of power supply soft-start circuit, for multiple power supplies
Situation about being provided by the power module of each separation, each power module control the upper electricity of out-put supply using the soft-start circuit of separation
Order, but because the startup time of each module and power-on time are different, the time parameter set by soft-start circuit can not
Suitable for the power module of different manufacturers, controllability is poor, and the supply voltage simultaneously for first upper electricity is the electricity of upper electricity after using
The power source design that source voltage conversion forms, still can not be in this way.
The third scheme controls the upper of each road power supply by PLDs such as power supply electrifying time schedule controller CPLD
Electric order and sequential.CPLD controllers are seldom exclusive on end product, are individually for electrifying timing sequence increase CPLD controllers just
It is increase Material Cost and software development cost, processing scheme is complicated.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide power-on time sequence control circuit, control
Method, electric supply installation and electric terminal, for solving the problems, such as that electrifying timing sequence controls unreliable or cost high in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of power-on time sequence control circuit, including：Triggering
Unit, including the first trigger and the second trigger；Two inputs of first trigger are connected to the first delay
The first delay circuit and the second delay circuit, wherein, first delay circuit be used for set first delay, second delay electricity
Road is used to set the second delay, so that the first power drives that at least one first output end is exported letter of first trigger
Number delay for described first delay and second delay sum；Two inputs of second trigger are connected to the 3rd
Delay circuit and the 4th delay circuit；Wherein, the 3rd delay circuit is used to set the 3rd delay, and the 4th delay circuit is used for
The 4th delay is set, so that the second source drive signal that at least one second output end is exported of second trigger prolongs
When for the described 3rd delay and the 4th delay sum；The output end of the output end of first trigger and second trigger
Power subsystem all the way is connected respectively, to pass through the delay inequality shape between first power driving signal and second source drive signal
Into the electrifying timing sequence of two-way power subsystem.
In one embodiment of the invention, first delay circuit, the second delay circuit, the 3rd delay circuit and the 4th
Delay circuit is RC delay circuits.
In one embodiment of the invention, the power subsystem includes：Power supply chip；First output end and second defeated
Going out the mode of end connection power supply chip includes：The Enable Pin of power supply chip is connected to control the output of power supply chip.
In one embodiment of the invention, the output end of the power subsystem is drawn for the negative of connection load through switching device
End is carried, the switching device has control terminal；The mode of the output end of the first output end second connection power supply chip includes：Even
The control terminal of the switching device is connect, it is logical to control power supply chip and load to connect to control the on-off of the switching device
It is or disconnected.
In one embodiment of the invention, the switching device is metal-oxide-semiconductor, and the control terminal is the grid of the metal-oxide-semiconductor.
In one embodiment of the invention, the switching device is N-channel MOS pipe, and its source electrode connects the power subsystem
Output end, drain electrode connects the load end；Second output end connects the grid of the metal-oxide-semiconductor and connect by pull-up resistor
To the source electrode of the metal-oxide-semiconductor.
In one embodiment of the invention, the power subsystem is DC-DC power source conversion device.
In order to achieve the above objects and other related objects, the present invention provides a kind of electric supply installation, including：When described upper electric
Sequence control circuit；And each power subsystem.
In order to achieve the above objects and other related objects, the present invention provides a kind of electric terminal, including：Described power supply dress
Put.
In order to achieve the above objects and other related objects, the present invention provides a kind of power-on time sequence control method, applied to institute
The power-on time sequence control circuit stated.
As described above, power-on time sequence control circuit, control method, electric supply installation and the electric terminal of the present invention, realize essence
True upper electric timing_delay estimation and safe electrifying timing sequence.
Brief description of the drawings
Fig. 1 is shown as the module principle schematic diagram of power-on time sequence control circuit of the present invention in an embodiment.
Fig. 2 is shown as the circuit theory schematic diagram of power-on time sequence control circuit of the present invention in an embodiment.
Fig. 3 a and 3b are shown as power-on time sequence control circuit connection two-way power subsystem of the present invention in an embodiment
Circuit theory schematic diagram.
Fig. 4 a and 4b are shown as power-on time sequence control circuit connection two-way power subsystem of the present invention in another embodiment
Circuit theory schematic diagram.
Component label instructions
1 power-on time sequence control circuit
11 trigger elements
111 first triggers
112 second triggers
12 first delay circuits
13 second delay circuits
14 the 3rd delay circuits
15 the 4th delay circuits
2 power subsystems
3 power subsystems
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the case where not conflicting, following examples and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way
Think, only show the component relevant with the present invention in schema then rather than according to component count, shape and the size during actual implement
Draw, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout kenel
It is likely more complexity.
As shown in figure 1, the present invention provides a kind of power-on time sequence control circuit 1, including：Trigger element 11, including first touch
Send out the trigger 112 of device 111 and second；Two inputs of first trigger 111 are connected to the first of the first delay
The delay circuit of delay circuit 12 and second, wherein, first delay circuit 12 is used to set the first delay, the second delay circuit
For setting the second delay, so that the first power drives that at least one first output end is exported of first trigger 111
The delay of signal is the described first delay and the second delay sum；Two inputs of second trigger 112 connect respectively
There are the 3rd delay circuit 14 and the 4th delay circuit 15；Wherein, the 3rd delay circuit 14 is delayed for setting the 3rd, and the 4th
Delay circuit 15 is used to set the 4th delay so that at least one second output end of second trigger 112 exported the
The delay of two power driving signals is the described 3rd delay and the 4th delay sum；The output end of first trigger 111 and
The output end of second trigger 112 connects power subsystem all the way respectively, to pass through first power driving signal and
Delay inequality between two power driving signals forms two-way power supply：That is the first power subsystem 2 and second source unit 3 it is upper electric when
Sequence.
As shown in Figure 2, there is provided the embodiment that a specific foregoing circuit is realized：
First delay circuit, the second delay circuit, the 3rd delay circuit and the 4th delay circuit are RC delay circuits,
The trigger element is, for example, dual trigger type Schmidt trigger chip, and the trigger chip model is, for example,
CD74HC123NSR, it is made up of two pieces of Schmidt triggers, also can is other types trigger in other embodiments certainly；From
And form and combined by the Schmidt trigger chip U5 of four RC delay circuits and a dual trigger, in the present embodiment, two-way
Power supply is only citing, in other embodiments, can also have more polylith Schmidt trigger and correspond to and control more multiple power supplies,
Quantity is not limited with the present embodiment；Four RC delay circuits, which are divided into two-way A and B, A and B, respectively two RC input time delay circuits
With an output control pin, specifically：
The output control on A roads is Power1_CTRL in figure, i.e. the first power driving signal, two input RC delay circuits
A1 and A2 is R23, C25 and R22, C24 respectively, Power1_CTRL time TA=TA1+TA2；
The output control on B roads is Power2_CTRL, i.e. second source drive signal, two input RC delay circuits B1 and
B2 is R24, C26 and R5, C5 respectively, Power2_CTRL time TB=TB1+TB2；
RC delay time calculation formula：T=-R*C*ln ((E-V)/E)；
Wherein, "-" is negative sign, and resistance R and electric capacity C are the main devices of RC series connection delay circuits, and R unit is ohm,
C unit is farad, and E is the magnitude of voltage between series resistance and electric capacity, and V is reached during electric capacity charge or discharge
Magnitude of voltage, ln are natural logrithms.
By above calculation formula, the voltages of E in the present invention are VDDH i.e. 3.3V, and the voltages of V in the present invention are
CMOS level Vih=2.4V, delay time is directly proportional to resistance value, capacitance, that is, only needs to adjust resistance capacitance value just
Specific delay time can be determined, delay time is embodied in the output control on the output control Power1_CTRL and B roads on A roads
Power2_CTRL time difference t, t=TA-TB, A1, A2, B1 and B2 time are calculated separately below：
A1=-R*C*ln ((E-V)/E)=- 100000 ohm of * 0.00001 farad of * ln0.27=13 seconds
A2=-R*C*ln ((E-V)/E)=- 100000 ohm of * 0.00001 farad of * ln0.27=13 seconds
B1=-R*C*ln ((E-V)/E)=- 10000 ohm of * 0.000001 farad of * ln0.27=0.13 seconds
B2=-R*C*ln ((E-V)/E)=- 10000 ohm of * 0.000001 farad of * ln0.27=0.13 seconds
The TA=TA1+TA2=26 seconds；
The TB=TB1+TB2=0.26 seconds；
The t=TA-TB=25.74 seconds, in other words, in the present embodiment, the delay inequality of two-way power supply output is 25.74 seconds,
Certainly, two-way power driving signal is only shown in the present embodiment, in other embodiments, it is possible to provide the power drives letter of more multichannel
Number, with
The embodiment that power subsystem is connected on the power-on time sequence control circuit is provided in conjunction with diagram below：
Embodiment 1：
In one embodiment, as shown in figs. 3 a and 3b, the power subsystem is DC-DC power source conversion device；
The power subsystem includes：Power supply chip (i.e. U6 and U23 in figure)；First output end and the second output end connect
Connecing the mode of power supply chip includes：The Enable Pin (EN) of power supply chip is connected to control the output of power supply chip
Specifically as illustrated, U6 and U23 are two-way DCDC (DC conversion power) respectively, the enabled control of this two-way power supply is defeated
The time TB for going out the time TA and Power2_CTRL by Power1_CTRL respectively is determined, because TA and TB having times are poor, this
Time difference is exactly the sequential of two-way power supply output.
R25 and R242 is 100K weak pull-downs in figure, and the enable pin to U6 and U23 provides an initial shape not exported
State, U6 and U23 is set not to export.When being reached Deng the TA times, Power1_CTRL provides high level, and driving U6 starts to export direct current；
When being reached Deng the TB times, Power2_CTRL provides high level, and driving U23 starts to export direct current.Complete SECO；The control
The advantages of mode processed is direct control DC-DC (DC conversion power), it is not necessary to which additional devices cost is low, is adapted to small load current
The SECO scheme of lower cost solution.
Embodiment 2：
In another embodiment, as shown in Fig. 4 a and Fig. 4 b, the output end of the power subsystem (DC-DC) is through switching device
(Q5 and Q6) draws the load end for connection load, and the switching device is that Q5 and Q6 is controlled source metal-oxide-semiconductor, opening point by
Power1_CTRL and Power2_CTRL time determines that R241 and R243 are 100K weak pull-ups, and providing one to Q5 and Q6 cuts
Original state only, when metal-oxide-semiconductor ends, the not upper electricity of load R240 and R245.
It is similar that the SECO mode of the present embodiment is same as above embodiment 1, but control point be at loading nose (even Vout),
DC-DC (DC conversion power) is exactly allowed first to complete No Load Start；The advantages of control mode is that electricity can not reduce on bringing onto load
Power-on surge current, damage of the big surge current to load is avoided, be adapted to the SECO demand of large load current.
In other embodiments, the present invention provide can also a kind of electric supply installation, including：Described electrifying timing sequence control electricity
Road；And each power subsystem；The present invention may also provide a kind of electric terminal, including：Described electric supply installation.
The electric supply installation is, for example, external power supply, or built-in power part etc., the electric terminal are, for example, interior
Telecommunication terminal, such as router etc..
In addition, can also the present invention a kind of power-on time sequence control method is provided, applied to described power-on time sequence control circuit,
For by controlling each delay to realize the SECO of power subsystem.
As described above, power-on time sequence control circuit, control method, electric supply installation and the electric terminal of the present invention, realize essence
True upper electric timing_delay estimation and safe electrifying timing sequence.The present invention effectively overcomes various shortcoming of the prior art and has height and produce
Industry value.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (6)
- A kind of 1. power-on time sequence control circuit, it is characterised in that including：Trigger element, including the first trigger and the second trigger；Two inputs of first trigger are connected to the first delay circuit and the second delay circuit of the first delay, Wherein, first delay circuit is used to set the first delay, and the second delay circuit is used to set the second delay, so that described the The delay of at least the first power driving signal that one first output end is exported of one trigger is the described first delay and second Be delayed sum；Two inputs of second trigger are connected to the 3rd delay circuit and the 4th delay circuit；Wherein, it is described 3rd delay circuit is used to set the 3rd delay, and the 4th delay circuit is used to set the 4th delay, so that second trigger At least second source drive signal that one second output end is exported delay for the described 3rd delay and the 4th delay sum；The output end of first trigger and the output end of second trigger connect power subsystem all the way respectively, to pass through Delay inequality between first power driving signal and second source drive signal forms the electrifying timing sequence of two-way power subsystem；The output end of the power subsystem draws the load end for connection load through switching device, and the switching device has control End；The mode of the output end of the first output end second connection power supply chip includes：The control terminal of the switching device is connected, with The on-off of the switching device is controlled to control power supply chip and the on-off of load connection；The switching device is metal-oxide-semiconductor, and the control terminal is the grid of the metal-oxide-semiconductor；The switching device is N-channel MOS pipe, and its source electrode connects the output end of the power subsystem, and drain electrode connects the load End；Second output end connects the grid of the metal-oxide-semiconductor and the source electrode of the metal-oxide-semiconductor is connected to by pull-up resistor；The power subsystem is DC-DC power source conversion device.
- 2. power-on time sequence control circuit according to claim 1, it is characterised in that first delay circuit, second prolong When circuit, the 3rd delay circuit and the 4th delay circuit be RC delay circuits.
- 3. power-on time sequence control circuit according to claim 1, it is characterised in that the power subsystem includes：Power supply core Piece；The mode of first output end and the second output end the connection power supply chip includes：Be connected to the Enable Pin of power supply chip with Control the output of power supply chip.
- A kind of 4. electric supply installation, it is characterised in that including：Such as electrifying timing sequence according to any one of claims 1 to 3 control electricity Road；And each power subsystem.
- A kind of 5. electric terminal, it is characterised in that including：Electric supply installation as claimed in claim 4.
- 6. a kind of power-on time sequence control method, it is characterised in that applied to upper electricity as claimed any one in claims 1 to 3 Sequential control circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510812561.6A CN105320040B (en) | 2015-11-20 | 2015-11-20 | Power-on time sequence control circuit, control method, electric supply installation and electric terminal |
| PCT/CN2016/101385 WO2017084447A1 (en) | 2015-11-20 | 2016-09-30 | Power-on timing sequence control circuit, control method, power supply apparatus and electronic terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510812561.6A CN105320040B (en) | 2015-11-20 | 2015-11-20 | Power-on time sequence control circuit, control method, electric supply installation and electric terminal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105320040A CN105320040A (en) | 2016-02-10 |
| CN105320040B true CN105320040B (en) | 2018-04-06 |
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| CN201510812561.6A Active CN105320040B (en) | 2015-11-20 | 2015-11-20 | Power-on time sequence control circuit, control method, electric supply installation and electric terminal |
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| Country | Link |
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| CN (1) | CN105320040B (en) |
| WO (1) | WO2017084447A1 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105320040B (en) * | 2015-11-20 | 2018-04-06 | 上海斐讯数据通信技术有限公司 | Power-on time sequence control circuit, control method, electric supply installation and electric terminal |
| CN106681209A (en) * | 2016-12-30 | 2017-05-17 | 广州周立功单片机科技有限公司 | Power supply sequential circuit and power supply sequential circuit control system |
| CN108963996A (en) * | 2018-07-24 | 2018-12-07 | 郑州云海信息技术有限公司 | A kind of method and device reducing transient state inrush current |
| CN109004923A (en) * | 2018-08-28 | 2018-12-14 | 深圳市新国都技术股份有限公司 | Sequential control circuit |
| CN109617544B (en) * | 2018-12-04 | 2023-06-13 | 凌云光技术股份有限公司 | Power-on time sequence control equipment, system and method |
| CN109557857B (en) * | 2018-12-10 | 2021-03-16 | 浪潮(北京)电子信息产业有限公司 | Method, device and system for controlling time sequence starting signal based on Intel platform |
| CN109885437A (en) * | 2019-02-25 | 2019-06-14 | 西安易朴通讯技术有限公司 | Baseboard management controller BMC, terminal and power-up state diagnotic module, method |
| CN110650569B (en) * | 2019-09-20 | 2022-05-10 | 上海源微电子科技有限公司 | LED driving chip with frequency modulation and application |
| CN112785985B (en) * | 2019-11-04 | 2022-03-11 | 海信视像科技股份有限公司 | Display device |
| CN110880302A (en) * | 2019-12-05 | 2020-03-13 | 山东超越数控电子股份有限公司 | LCD screen anti-screen-splash system based on domestic processor and implementation method |
| CN112269347B (en) * | 2020-12-24 | 2021-03-16 | 深圳市鼎阳科技股份有限公司 | Power-on and power-off time sequence control device |
| CN114661130A (en) * | 2022-03-09 | 2022-06-24 | 湖南智领通信科技有限公司 | Power supply control circuit of CPU module and design method |
| CN115631724A (en) * | 2022-10-31 | 2023-01-20 | 厦门天马显示科技有限公司 | Display module, driving method thereof and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100446305B1 (en) * | 2002-08-20 | 2004-09-01 | 삼성전자주식회사 | Power supply voltage-, temperature-independent R-C oscillator using controllable Schmitt trigger |
| CN2655309Y (en) * | 2003-07-16 | 2004-11-10 | 华为技术有限公司 | Power supply time sequence controlling circuit |
| CN105320040B (en) * | 2015-11-20 | 2018-04-06 | 上海斐讯数据通信技术有限公司 | Power-on time sequence control circuit, control method, electric supply installation and electric terminal |
-
2015
- 2015-11-20 CN CN201510812561.6A patent/CN105320040B/en active Active
-
2016
- 2016-09-30 WO PCT/CN2016/101385 patent/WO2017084447A1/en active Application Filing
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|---|---|---|---|---|
| JPS56145404A (en) * | 1980-03-19 | 1981-11-12 | Omron Tateisi Electronics Co | Input circuit of sequence controller |
| CN201159850Y (en) * | 2008-01-29 | 2008-12-03 | 深圳华北工控有限公司 | Sequence control circuit |
| CN101963792A (en) * | 2010-10-29 | 2011-02-02 | 珠海市鑫和电器有限公司 | Time sequence control circuit and control method thereof |
| CN102809931A (en) * | 2011-05-30 | 2012-12-05 | 鸿富锦精密工业（深圳）有限公司 | Time sequence control circuit for power supply |
| CN203522681U (en) * | 2013-10-18 | 2014-04-02 | 深圳市新格林耐特通信技术有限公司 | Double-time-delay power-on sequential control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105320040A (en) | 2016-02-10 |
| WO2017084447A1 (en) | 2017-05-26 |
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Effective date of registration: 20201209 Address after: Dai Xi Zhen Shang Qiang Lu, Wuxing District, Huzhou City, Zhejiang Province Patentee after: HUZHOU AIDI ELECTRIC Co.,Ltd. Address before: 201616 No. 3666 Sixian Road, Songjiang District, Shanghai Patentee before: Phicomm (Shanghai) Co.,Ltd. |
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Effective date of registration: 20221114 Address after: 529400 South of the 5th floor, No. 108, Enzhou Industrial Avenue, Encheng Street, Enping City, Jiangmen City, Guangdong Province Patentee after: Enping Yingli Electronic Technology Co.,Ltd. Address before: Dai Xi Zhen Shang Qiang Lu, Wuxing District, Huzhou City, Zhejiang Province Patentee before: HUZHOU AIDI ELECTRIC Co.,Ltd. |
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Denomination of invention: Power on timing control circuit, control method, power supply device, and electronic terminal Granted publication date: 20180406 Pledgee: Agricultural Bank of China Limited Enping City sub branch Pledgor: Enping Yingli Electronic Technology Co.,Ltd. Registration number: Y2024980025850 |