CN105306023A - Pulse delay circuit - Google Patents
Pulse delay circuit Download PDFInfo
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- CN105306023A CN105306023A CN201410268440.5A CN201410268440A CN105306023A CN 105306023 A CN105306023 A CN 105306023A CN 201410268440 A CN201410268440 A CN 201410268440A CN 105306023 A CN105306023 A CN 105306023A
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Abstract
The invention relates to a pulse delay circuit. The pulse delay circuit comprises a pull-down unit, a first pull-up unit, a first delay unit, a second delay unit, a second pull-up unit and an inverse-phase buffer, wherein the pull-down unit is provided with a control end, a first end and a second end; the control end is used for receiving an input pulse signal; the first end is connected to a node b; the second end is connected to first voltage; the first pull-up unit is provided with a control end, a first end and a second end; the control end is connected to a node c; the first end is connected to second voltage; the second end is connected to the node b; the first delay unit is provided with a reset end, an input end and an output end; the input end is connected to the node b; the output end is connected to the node c; the second delay unit is provided with an input end and an output end; the input end is connected to the node c; the output end is connected to a node d; the second pull-up unit is provided with a control end, a first end and a second end; the control end is connected to the node d; the first end is connected to the second voltage; the second end is connected to the node c; the inverse-phase buffer is provided with an input end and an output end; the input end is connected to the node c; the output end is connected to the reset end of the first delay unit; and the output end of the inverse-phase buffer generates a delay pulse signal.
Description
Technical field
The present invention relates to a kind of delay circuit, and in particular to a kind of pulse delay circuit.
Background technology
As everyone knows, delay circuit becomes output signal after input signal can being postponed a special time.Therefore, after a pulse signal (pulsesignal) input delay circuit, delay (delaytime, the t of this special time can be produced between the pulse signal of its delayed pulse signal exported (delayedpulsesignal) and input
d).
But, as pulse duration (pulsewidth, t in pulse signal
width) very narrow (being too narrow to lower than special time interval, such as 5ns) time, in the delayed pulse signal utilizing general delay circuit to export, the waveform (waveform) of its pulse will serious distortion (distortion).
Please refer to Fig. 1, its illustrate is known pulse delay circuit.Pulse delay circuit 100 comprises rising trigger (risingtrigger) 102, first delay cell 104, decline trigger (fallingtrigger) 106, second delay cell 108.
Rising trigger 102 and decline trigger 106 receive input pulse signal Pin.Rising edge flip-flops 102 produces the first triggering signal Tr at the rising edge (risingedge) of input pulse signal Pin and inputs the first delay cell 104; Decline trigger 106 produces the second triggering signal Tf at the trailing edge (fallingedge) of input pulse signal Pin and inputs the second delay cell 108.
Moreover the first delay cell 104 and the second delay cell 108 by after the first triggering signal Tr and the second triggering signal Tf Late phase special time together, can synthesize the pulse signal Pout of delay respectively.
Please refer to Fig. 2, its illustrate is another pulse delay circuit known.Pulse delay circuit 200 comprises delay cell 202, monostable flip-flop (monostablemultivibrator) 204.Wherein, the input signal Pin_d that is delayed after receiving input signal Pin of delay cell 202.And the pulse signal Pout that the input signal Pin_d postponed can be delayed after inputting monostable flip-flop 204 again.
Substantially, the input signal Pin_d of delay may cause wave distortion.Moreover according to the triggering of the input signal Pin_d postponed, monostable flip-flop 204 can produce the pulse signal Pout of the undistorted delay of waveform.
But in the field of IC design, the circuit of known monostable flip-flop 204 is complicated, has the shortcoming that layout area (layoutsize) is excessive.
Summary of the invention
Main purpose of the present invention is to propose a kind of new architecture and the less pulse delay circuit of circuit layout area.
The present invention relates to a kind of pulse delay circuit, comprising: a drop-down unit, have a control end and receive an input pulse signal, a first end is connected to a node b, and one second end is connected to one first voltage; One first pull-up unit, have a control end and be connected to a node c, a first end is connected to one second voltage, and one second end is connected to this node b; First delay cell, has a replacement end, and an input is connected to this node b, and an output is connected to this node c; One second delay cell, have an input and be connected to this node c, an output is connected to a node d; One second pull-up unit, have a control end and be connected to this node d, a first end is connected to this second voltage, and one second end is connected to this node c; And an inverter buffer, have an input and be connected to this node c, an output is connected to this replacement end of this first delay cell, and this output of this inverter buffer produces a pulse signal postponed.
In order to have better understanding to above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinating accompanying drawing, being described in detail below:
Accompanying drawing explanation
Fig. 1 illustrate is known pulse delay circuit.
Fig. 2 illustrate is another pulse delay circuit known.
Fig. 3 A and Fig. 3 B illustrate are pulse delay circuit of the present invention and coherent signal schematic diagram thereof.
It is the first delay cell schematic diagram that Fig. 4 A and Fig. 4 B illustrates.
It is the second delay cell schematic diagram that Fig. 5 A and Fig. 5 B illustrates.
[symbol description]
100,200: pulse delay circuit
102: rising trigger
104: the first delay cells
106: decline trigger
108: the second delay cells
202: delay cell
204: monostable flip-flop
300: pulse delay circuit
302: the first pull-up elements
304: drop down element
306: the first delay cells
308: the second delay cells
310: the second pull-up elements
312,402,502: inverter
Embodiment
Please refer to Fig. 3 A and Fig. 3 B, its illustrate is pulse delay circuit of the present invention and coherent signal schematic diagram thereof.Pulse delay circuit 300 comprises the first pull-up element (pullupelement) 302, drop down element (pulldownelement) 304, first delay cell 306, second delay cell 308, second pull-up element 310, inverter 312.
Drop-down unit 304 has control end and receives input pulse signal Pin, and first end is connected to node b, and the second end is connected to earthed voltage GND.First pull-up unit 302 has control end and is connected to node c, and first end is connected to a power source voltage Vcc, and the second end is connected to node b.First delay cell 306 has a replacement end (R), and its input is connected to node b, and output is connected to node c.Second delay cell 308 has an input and is connected to node c, and output is connected to node d.Second pull-up unit 310 has control end and is connected to node d, and first end is connected to a power source voltage Vcc, and the second end is connected to node c.Inverter 312 has an input and is connected to node c, and output is connected to the replacement end (R) of the first delay cell, and the pulse signal Pout that inverter 312 output is delayed.Moreover above-mentioned inverter 312 can be considered an inverter buffer (invertedbuffer).In addition, in order to improve the slope of the pulse signal Pout of delay, inverter buffer also can realize via serial connection odd number (such as 3 or 5) inverter.
According to embodiments of the invention, drop-down unit 304 is a N-type transistor Mn1, and its grid is the control end of drop-down unit 304, drains as the first end of drop-down unit 304, and source electrode is the second end of drop-down unit 304.First pull-up unit 302 is a P-type crystal pipe Mp1, and its grid is the control end of the first pull-up unit 302, and source electrode is the first end of the first pull-up unit 302, and drain electrode is the second end of the first pull-up unit 302.Second pull-up unit 310 is a P-type crystal pipe Mp2, and its grid is the control end of the second pull-up unit 310, and source electrode is the first end of the second pull-up unit 310, and drain electrode is the second end of the second pull-up unit 310.
When the replacement end (R) of the first delay cell 306 receives high level, the first delay cell 306 is reset and cannot normal operation; And when receiving low level, the first delay cell 306 can normal operation.Moreover, when the first delay cell 306 normal operation, by the signal become after signal delay first delay time (td1) on node b on node c.
Second delay cell 308, can normal operation constantly without replacement end, its signal that will become after signal delay second delay time (td2) on node c on node d.
As shown in Figure 3 B, when input pulse signal Pin is low level time point t0, the signal on node b, node c, node d is high level, and the pulse signal Pout of delay is low level.Wherein, high level can be power source voltage Vcc, and low level can be earthed voltage GND.
At time point t1, input pulse signal Pin is changed to high level by low level.Now, the signal on node b is also pulled down to low level by high level by drop down element 304 action, and the signal on node c, node d maintains high level, and the pulse signal Pout of delay maintains low level.
At time point t2, input pulse signal Pin is changed to low level by high level, and drop down element 304 stops action, and the signal on node b, node c, node d remains unchanged, and the pulse signal Pout of delay maintains low level.
Because the signal trailing edge on node b can be postponed the first delay time (td1) by the first delay cell 306.Therefore, at the three time point t3 of time point t1 after the first delay time (td1), the signal on node c becomes low level from high level.Meanwhile, because the signal on node c becomes low level, the first pull-up element 302 action will be made, the signal on node b will be pulled to high level by low level; Further, the pulse signal Pout of the delay that inverter 312 exports is changed to high level by low level, and resets the first delay cell 306.Moreover the signal on node d maintains high level.
Because the signal trailing edge on node c can be postponed the second delay time (td2) by the second delay cell 308.Therefore, at the four time point t4 of time point t3 after the second delay time (td2), the signal on node d becomes low level from high level.Meanwhile, because the signal on node d becomes low level, the second pull-up element 310 action will be made, the signal on node c will be pulled to high level by low level; Further, the pulse signal Pout of delay that inverter 312 exports is changed to low level by high level, makes the first delay cell 306 can normal operation.Moreover the signal on node b maintains high level.
At time point t5, the signal on node d is changed to high level by low level, and the voltage on node b, node c maintains high level, and the pulse signal Pout of delay maintains low level.
When time point t6, input pulse signal Pin is changed to high level again by low level.Its operating principle is identical with time point t1, repeats no more.
From above explanation, pulse delay circuit 300 of the present invention utilizes the rising edge of input pulse signal Pin to carry out action drop down element 304, and pulse delay circuit 300 is come into operation, with the pulse signal Pout be delayed.
Moreover, differ the first time of delay (td1) between input pulse signal Pin and the pulse signal Pout of delay.This first time of delay (td1) is controlled by the first delay cell 306.
In addition, the pulse duration (pulsewidth) of the pulse signal Pout of delay is the second time of delay (td2).In other words, the pulse duration of the pulse signal Pout of delay is controlled by the second delay cell 308.
Please refer to Fig. 4 A and Fig. 4 B, it illustrates is the first delay cell and coherent signal schematic diagram thereof.First delay cell 306 comprises an inverter 402, resistance R1, capacitor C1, N-type transistor Mn2 and Mn3, P-type crystal pipe Mp3 and Mp4.Wherein, the size of the first time of delay can be determined by the numerical value of resistance R1 and capacitor C1.
Inverter 402 input is connected to node b, contact resistance R1 between inverter 402 output and node e.The drain electrode of N-type transistor Mn2 is connected to node e, and grid is connected to node b, and source electrode is connected to earthed voltage GND.Capacitor C1 is connected between node e and earthed voltage GND.P-type crystal pipe Mp3 source electrode is connected to power source voltage Vcc, and grid is connected to node e; P-type crystal pipe Mp4 source electrode is connected to P-type crystal pipe Mp3 and drains, and grid is the replacement end (R) of the first delay cell 306, and drain electrode is connected to node c; N-type transistor Mn3 drain electrode is connected to node c, and grid is connected to node e, and source electrode is connected to earthed voltage GND.
As shown in Figure 4 B, at time point t1, the first delay cell 306 normal operation.Now, the signal on node b reduces to low level by high level, and N-type transistor Mn2 is failure to actuate (turnoff) and inverter 402 output is converted to high level.In addition, inverter 402 output produces a charging current via resistance R1 toward capacitor C1, makes the voltage of node e increase gradually by earthed voltage GND.Now, P-type crystal pipe Mp4 action (turnon), and N-type transistor Mn3 is failure to actuate (turnoff), the signal on node c maintains high level.
When time point t3, the voltage rise of node e, to power source voltage Vcc, makes N-type transistor Mn3 action (turnon), and P-type crystal pipe Mp4 is failure to actuate (turnoff), and the signal on node c is converted to low level by high level.In addition, because the signal on node b changes into high level by low level, make N-type transistor Mn2 action (turnon) and make the voltage of node e be down to earthed voltage GND.In other words, according to the signal intensity on node b, the signal on node e can change between earthed voltage GND and power source voltage Vcc.
Moreover the signal on input pulse signal Pin, node b, node c, node d, the clock signal Pout of delay is all identical with Fig. 3 B, repeats no more.
Please refer to Fig. 5 A and Fig. 5 B, it illustrates is the second delay cell and coherent signal schematic diagram thereof.Second delay cell 308 comprises an inverter 502, resistance R2, capacitor C2, N-type transistor Mn5, P-type crystal pipe Mp5.Wherein, the size of the second time of delay can be determined by the numerical value of resistance R2 and capacitor C2.
Inverter 502 input is connected to node c, contact resistance R2 between inverter 502 output and node f.Capacitor C2 is connected between node f and earthed voltage GND.P-type crystal pipe Mp5 source electrode is connected to power source voltage Vcc, and grid is connected to node f, and drain electrode is connected to node d.N-type transistor Mn5 drain electrode is connected to node d, and grid is connected to node f, and source electrode is connected to earthed voltage GND.
As shown in Figure 5 B, at time point t3, the signal on node c reduces to low level by high level, and inverter 502 output is converted to high level.In addition, inverter 502 output produces a charging current via resistance R2 toward capacitor C2, makes the voltage of node f start to rise gradually.Now, P-type crystal pipe Mp5 action (turnon), and N-type transistor Mn5 is failure to actuate (turnoff), the signal on node d maintains high level.
When time point t4, the voltage rise of node f, to power source voltage Vcc, makes N-type transistor Mn5 action (turnon), and P-type crystal pipe Mp5 is failure to actuate (turnoff), and the signal on node d is converted to low level by high level.In addition, because the signal on node c changes into high level by low level, inverter 502 output becomes low level, and capacitor C2 produces a discharging current via resistance R2 toward inverter 502 output, makes the voltage of node f start to decline gradually.
When time point t5, the voltage drop of node f, to earthed voltage GND, makes P-type crystal pipe Mp5 action (turnon), and N-type transistor Mn5 is failure to actuate (turnoff), and the signal on node d is high level by low transition.In other words, according to the signal intensity on node c, the signal on node f can change between power source voltage Vcc and earthed voltage GND.
Moreover the signal on input pulse signal Pin, node b, node c, node d, node e, the clock signal Pout of delay is all identical with Fig. 4 B, repeats no more.
Therefore, the invention has the advantages that and propose a kind of pulse delay circuit, its simple structure and circuit layout area is very little.Further, can adjust for the first time of delay via the numerical value of the resistance R1 in control first delay cell 306 and capacitor C1; And adjusted for the second time of delay via the numerical value of the resistance R2 in control second delay cell 308 and capacitor C2.Wherein, input pulse signal Pin via the control of the first delay cell 306, after delay first time of delay, the pulse signal Pout that can be delayed.The pulse signal Pout postponed is via the control of the second delay cell 308, and the pulse duration making the pulse signal Pout postponed was the second time of delay.
In sum, although the present invention is with preferred embodiment openly as above, so itself and be not used to limit the present invention.Those skilled in the art of the invention without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when being as the criterion depending on appended claims confining spectrum.
Claims (9)
1. a pulse delay circuit, comprising:
Drop-down unit, have control end and receive input pulse signal, first end is connected to node (b), and the second end is connected to the first voltage;
First pull-up unit, has control end and is connected to node (c), and first end is connected to the second voltage, and the second end is connected to this node (b);
First delay cell, have and reset end, input is connected to this node (b), and output is connected to this node (c);
Second delay cell, have input and be connected to this node (c), output is connected to node (d);
Second pull-up unit, has control end and is connected to this node (d), and first end is connected to this second voltage, and the second end is connected to this node (c); And
Inverter buffer, has input and is connected to this node (c), and output is connected to this replacement end of this first delay cell, and the pulse signal that this output of this inverter buffer is delayed.
2. pulse delay circuit as claimed in claim 1, wherein drop-down unit is the first N-type transistor, and grid receives this input pulse signal, and source electrode is connected to this first voltage, and drain electrode is connected to this node (b).
3. pulse delay circuit as claimed in claim 2, wherein the first pull-up unit is the first P-type crystal pipe, and grid is connected to this node (c), and source electrode is connected to this second voltage, and drain electrode is connected to this node (b).
4. pulse delay circuit as claimed in claim 3, wherein the second pull-up unit is the second P-type crystal pipe, and grid is connected to this node (d), source electrode is connected to this second voltage, drain electrode is connected to this node c, and this first voltage is earthed voltage, and this second voltage is supply voltage.
5. pulse delay circuit as claimed in claim 1, wherein the signal trailing edge on this node (b) was postponed for the first time of delay by this first delay cell, and the signal trailing edge on this node (c) is postponed the second delay time by this second delay cell.
6. pulse delay circuit as claimed in claim 5, wherein this first delay cell comprises:
Inverter, has output and input is connected to this node (b);
Resistance, is connected between this output and node (e) of this inverter;
First N-type transistor, have drain electrode and be connected to this node (e), grid is connected to this node (b), and source electrode is connected to the first voltage;
Capacitor, is connected between this node (e) and this first voltage;
First P-type crystal pipe, have source electrode and be connected to this second voltage, grid is connected to this node (e);
Second P-type crystal pipe, have the drain electrode that source electrode is connected to this first P-type crystal pipe, grid is held as this replacement, and drain electrode is connected to this node (c); And
Second N-type transistor, have drain electrode and be connected to this node (c), grid is connected to this node (e), and source electrode is connected to this first voltage.
7. pulse delay circuit as claimed in claim 6, wherein, this first voltage is earthed voltage, and this second voltage is supply voltage; And the numerical value changing this resistance and this capacitor is to adjust this first time of delay.
8. pulse delay circuit as claimed in claim 5, wherein this second delay cell comprises:
Inverter, has output and input is connected to this node (c);
Resistance, is connected between this output and node (f) of this inverter;
Capacitor, is connected between this node (f) and this first voltage;
P-type crystal pipe, have source electrode and be connected to this second voltage, grid is connected to this node (f), and drain electrode is connected to this node (d); And
N-type transistor, have drain electrode and be connected to this node (d), grid is connected to this node (f), and source electrode is connected to this first voltage.
9. pulse delay circuit as claimed in claim 8, wherein, this first voltage is earthed voltage, and this second voltage is supply voltage; And the numerical value changing this resistance and this capacitor is to adjust this second time of delay.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410268440.5A CN105306023B (en) | 2014-06-16 | 2014-06-16 | Pulse delay circuit |
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|---|---|---|---|
| CN201410268440.5A CN105306023B (en) | 2014-06-16 | 2014-06-16 | Pulse delay circuit |
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| CN105306023B CN105306023B (en) | 2017-12-01 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112825479A (en) * | 2019-11-20 | 2021-05-21 | 合肥格易集成电路有限公司 | Delay circuit and chip |
| CN114545807A (en) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN114545809A (en) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
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| CN102347761A (en) * | 2010-07-27 | 2012-02-08 | 中兴通讯股份有限公司 | Dynamic delay, and phase-frequency detector (PFD) and phase lock loop adopting same |
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| CN1459683A (en) * | 2002-05-24 | 2003-12-03 | 三星电子株式会社 | Circuit and method for producing internal clock signal |
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| CN112825479A (en) * | 2019-11-20 | 2021-05-21 | 合肥格易集成电路有限公司 | Delay circuit and chip |
| CN112825479B (en) * | 2019-11-20 | 2024-07-09 | 合肥格易集成电路有限公司 | Delay circuit and chip |
| CN114545807A (en) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN114545809A (en) * | 2020-11-25 | 2022-05-27 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN114545807B (en) * | 2020-11-25 | 2024-03-26 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
| CN114545809B (en) * | 2020-11-25 | 2024-05-03 | 长鑫存储技术有限公司 | Control circuit and delay circuit |
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| CN105306023B (en) | 2017-12-01 |
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