CN105304729B - Flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof - Google Patents

Flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof Download PDF

Info

Publication number
CN105304729B
CN105304729B CN201510585315.1A CN201510585315A CN105304729B CN 105304729 B CN105304729 B CN 105304729B CN 201510585315 A CN201510585315 A CN 201510585315A CN 105304729 B CN105304729 B CN 105304729B
Authority
CN
China
Prior art keywords
group semiconductor
layer
type
graphene layer
graphene
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201510585315.1A
Other languages
Chinese (zh)
Other versions
CN105304729A (en
Inventor
张希威
孟丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anyang Normal University
Original Assignee
Anyang Normal University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anyang Normal University filed Critical Anyang Normal University
Priority to CN201510585315.1A priority Critical patent/CN105304729B/en
Publication of CN105304729A publication Critical patent/CN105304729A/en
Application granted granted Critical
Publication of CN105304729B publication Critical patent/CN105304729B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0296—Inorganic materials including, apart from doping material or other impurities, only AIIBVI compounds, e.g. CdS, ZnS, HgCdTe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035209—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures
    • H01L31/035227—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions comprising a quantum structures the quantum structure being quantum wires, or nanorods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
    • H01L31/1032—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type the devices comprising active layers formed only by AIIBVI compounds, e.g. HgCdTe IR photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1828—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIBVI compounds, e.g. CdS, ZnS, CdTe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0083—Processes for devices with an active region comprising only II-VI compounds
    • H01L33/0087—Processes for devices with an active region comprising only II-VI compounds with a substrate not being a II-VI compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/24—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate of the light emitting region, e.g. non-planar junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/28—Materials of the light emitting region containing only elements of group II and group VI of the periodic system
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention discloses flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof.It includes flexible substrate, graphene layer, II VI races semiconductor axial direction p n junction nanowires array, PMMA insulating barriers, aluminium electrode, gold/Ti electrode.Graphene layer is transferred on the silicon substrate with silicon dioxide layer first；Then II VI races semiconductor axial direction p n junction nanowire arrays are grown on graphene layer using chemical vapour deposition technique；PMMA insulating barriers are filled between the p n junction nanowire arrays gap of II VI races semiconductor axial direction followed by spin-coating method；E-beam evaporation is recycled to prepare aluminium electrode on PMMA insulating barriers and prepare gold/Ti electrode on the exposed side of graphene layer；Device is integrally finally transferred to flexible substrate from silicon substrate using sacrifice layer etching transfer method.Patent of the present invention employs graphene and II VI races semiconductor axial direction p n junction nanowire arrays, effectively increases the density and ductility of inorganic flexible opto-electronic device.

Description

Flexible light based on graphene and the axial p-n junction nano-wire array of II-VI group semiconductor Electronic device and preparation method thereof
Technical field：
It is more particularly to a kind of to be based on graphene and II-VI group semiconductor the present invention relates to nano photoelectronic devices field Flexible optoelectronic part of axial p-n junction nano-wire array and preparation method thereof.
Background technology：
Along with the high speed information of society, people and organically blending for information turn into the important development of future information technology Trend, and flexibility is once realized as all kinds of electronic devices of information carrier, it will inherently promote the height of people and information Effect interaction.Therefore Global Academy and industrial circle all turn one's attention to the flexible electronic technology for representing future thrust.Its is general Read from the research to organic electronics, but organic semiconducting materials can not emphasize high property due to the limitation of self character Can and high stability contemporary electronic systems in extensively using (A.J.Baca, J.H.Ahn, Y.G.Sun, M.A.Meitl, E.Menard, H.S.Kim, W.M.Choi, D.H.Kim, Y.Huang, J.A.Rogers, Angew.Chem.Int.Ed., 47, 5524(2008)).Then, Erie Ruo Yi universities Rogers professors and professor Huang are proposed based on the soft of traditional inorganic semiconductor Property electronic device, they prepare inorganic functional thin-film device using existing semiconductor silicon technique, are then transferred to flexible substrate, Discharge inorganic functional device complete buckling under the contraction of prestretching stretching strain, so that it is extending soft to realize that whole device possesses Property (A.J.Baca, J.H.Ahn, Y.G.Sun, M.A.Meitl, E.Menard, H.S.Kim, W.M.Choi, D.H.Kim, Y.Huang, J.A.Rogers, Angew.Chem.Int.Ed., 47,5524 (2008)).But such devices ductility is relatively low, And it is often that inorganic thin filmization is generally local in order to obtain bigger ductility, and each funtion part is connected by wire. This measure can reduce effective area of the film in whole device, and then reduce device density.Therefore, how to handle ductility and This pair of paradox of device density turn into the subject matter that flexible inorganic development of electronic devices faces at this stage.
The content of the invention：
The present invention is in view of the shortcomings of the prior art, it is proposed that one kind is based on graphene and the axial p-n junction of II-VI group semiconductor Flexible optoelectronic part of nano-wire array and preparation method thereof, to realize the flexible inorganic with high device density and ductility Opto-electronic device.
To achieve these goals, the present invention is proposed one kind and received based on graphene and the axial p-n junction of II-VI group semiconductor The flexible optoelectronic part of nanowire arrays, it is characterised in that：Including one layer of flexible substrate (1), the flexible substrate (1) is provided with Graphene layer (2), the graphene layer (2) is provided with by p-type II-VI group semiconductor nanowires part (3) and n-type II-VI The array structure of the axial p-n junction nano wire of II-VI group semiconductor of race's semiconductor nanowires part (4) composition, the II-VI group Semiconductor axial direction is provided with PMMA (PolymethylMethacrylate, poly-methyl methacrylate in p-n junction nano-wire array gap Ester) insulating barrier (5), n-type II-VI group semiconductor nanowires part (4) the array head is exposed in the PMMA insulating barriers (5) outside, aluminium electrode (6) is provided with the PMMA insulating barriers (5), on the exposed side of the graphene layer (2) provided with gold/ Ti electrode (7).
Preferably, the flexible substrate (1) is PET (Polyethylene terephthalate, poly terephthalic acid Glycol ester), PDMS (Polydimethylsiloxane, dimethyl silicone polymer), PEN (polyethylene Naphthalate, PEN) or PI (Polyimide, polyimides).
Preferably, the graphene layer (2) is individual layer or number layer graphene.
Preferably, the p-type II-VI group semiconductor nanowires part (3) is p-type ZnSe, ZnS, ZnTe, CdSe, CdS or CdTe nano wires, a diameter of 100-500nm of the p-type II-VI group semiconductor nanowires part (3), length is 5- 10μm；Described n-type II-VI group semiconductor nanowires part (4) is that n-type ZnSe, ZnS, ZnTe, CdSe, CdS or CdTe receive Rice noodles, a diameter of 100-500nm of described n-type II-VI group semiconductor nanowires part (4), length is 5-10 μm；It is described P-type II-VI group semiconductor nanowires part (3) constitute II- with described n-type II-VI group semiconductor nanowires part (4) The axial p-n junction nano wire of VI races semiconductor.
Preferably, the aluminium electrode (6) is shaped as square net shape；Aluminium electrode (6) thickness is 100- 200nm, width is 3-5 μm.Preferably, the thickness of layer gold is 100-200nm, the thickness of titanium layer in the gold/Ti electrode (7) For 5-10nm, layer gold is upper, and titanium layer is under.To achieve the above object, preparation method of the invention comprises the following steps：
1) graphene layer is placed on the silicon substrate covered with silica；
2) 5-10nm gold nanoparticle films are deposited on graphene layer using e-beam evaporation, for II-VI group half Catalysis nucleation in the p-n junction nanowire growth process of conductor axial direction；
3) II-VI group being grown on graphene layer is prepared in horizontal pipe furnace using chemical vapour deposition technique partly to lead Body axial direction p-n junction nano-wire array；
3a) porcelain boat for filling the II-VI group semiconductor powder that purity is 99.99% is positioned in the middle part of horizontal pipe furnace i.e. At heating source, being placed on the silicon substrate covered with silica and surface evaporation has the graphite of 5-10nm gold nanoparticle films Alkene layer is placed on the rear portion of horizontal pipe furnace；
3b) closed body of heater, is evacuated to pressure in body of heater and is less than 3 × 10-3Pa；Open heating source and temperature is risen into 800- 1050℃；
3c) using 100SCCM gas flow introduce argon hydrogen protection gas (wherein the gas volume ratio of argon gas and hydrogen is 95: 5)；
Gaseous state p-doping source 3d) is introduced with 1-10SCCM gas flow, received to grow p-type II-VI group semiconductor Rice noodles part, this process is maintained 15-30 minutes, then stops introducing gaseous state p-doping source；
Gaseous state n-type doped source 3e) is introduced with 1-5SCCM gas flow, received for growing n-type II-VI group semiconductor Rice noodles part, this process is maintained 15-30 minutes, then stops introducing gaseous state n-type doped source；
Heating source 3f) is closed, stops introducing argon hydrogen protection gas, body of heater is down to room temperature naturally, open body of heater, taking-up is placed in Graphene layer on silicon substrate covered with silica, obtains the II-VI group semiconductor axial direction p-n being grown on graphene layer Junction nanowire array；
4) PMMA insulating barriers is coated the axial p-n junction nano-wire array of II-VI group semiconductor using spin-coating method and fill it Internal interstices；
5) using plasma lithographic technique etching PMMA surface of insulating layer, makes n-type II-VI group semiconductor nanowires portion The head divided is exposed outside PMMA insulating barriers；
6) use e-beam evaporation to prepare thickness for 100-200nm in PMMA insulating layer top portions, width be 3-5 μm just Square grid trellis aluminium electrode；
7) using electron beam evaporation technique the exposed side of graphene layer successively evaporation thickness for 5-10nm titanium and 100-200 nanometers of gold electrode；
8) it is using sacrifice layer etching transfer method that device prepared by above-mentioned preparation method is overall from covered with silica It is transferred on silicon substrate in flexible substrate.
Compared with prior art, the present invention has following beneficial outcomes：
1. in the present invention, due to the axial p-n junction nano wire of II-VI group semiconductor and the minimum contact area of graphene and Flexible potential quality that graphene has in itself (under the mechanical deformation such as bending, flexible, extruding still can holding structure and performance stabilization Property) etc. reason cause device that there is fabulous ductility, the axial p-n junction nano-wire array of II-VI group semiconductor is effective in addition Device density is added, thus overcomes the shortcoming that conventional flex solar cell ductility and integrated level can not get both；
2. device architecture is simple in the present invention, preparation technology is simple.
Brief description of the drawings：
Fig. 1 is the cross-sectional view of the present invention.
Fig. 2 is the cross-sectional view of the present invention in the bent state.
Fig. 3 is the fabrication processing figure of the present invention.
Embodiment：
Reference picture 1, the present invention includes flexible substrate (1), graphene layer (1), by p-type II-VI group semiconductor nanowires portion Divide the axial p-n junction nano-wire array knot of II-VI group semiconductor of (3) and n-type II-VI group semiconductor nanowires part (4) composition Structure, PMMA insulating barriers (5), aluminium electrode (6), gold/Ti electrode (7), wherein flexible substrate (1) are provided with graphene layer (2), graphite Being grown on alkene layer (2) has by p-type II-VI group semiconductor nanowires part (3) and n-type II-VI group semiconductor nanowires part (4) the axial p-n junction nanowire array structure of the II-VI group semiconductor of composition, II-VI group semiconductor axial direction p-n junction nanometer linear array Arrange and PMMA insulating barriers (5) are filled with gap, n-type II-VI group semiconductor nanowires part (4) array head is exposed in PMMA Outside insulating barrier (5), deposition has to deposit on aluminium electrode (6), graphene layer (2) exposed side and had on PMMA insulating barriers (5) Gold/Ti electrode (7).
With reference to Fig. 3, making given below is soft based on graphene and the axial p-n junction nano-wire array of II-VI group semiconductor Three embodiments of property opto-electronic device：
Embodiment 1：
1) single-layer graphene is placed on the silicon substrate covered with silica, such as Fig. 3-A；
2) 5nm gold nanoparticle films, such as Fig. 3-B, for ZnSe are deposited on graphene layer using e-beam evaporation Catalysis nucleation in axial p-n junction nanowire growth process；
3) the ZnSe axial directions p-n being grown on graphene layer is prepared in horizontal pipe furnace using chemical vapour deposition technique Junction nanowire array, such as Fig. 3-C and 3-D；
3a) porcelain boat for filling the ZnSe powder that purity is 99.99% is positioned in the middle part of horizontal pipe furnace at i.e. heating source, The graphene layer that being placed on the silicon substrate covered with silica and surface evaporation has 5nm gold nanoparticle films is placed on water The rear portion of flat tube furnace；
3b) closed body of heater, is evacuated to pressure in body of heater and is less than 3 × 10-3Pa；Open heating source and temperature is risen to 1050 ℃；
Argon hydrogen protection gas 3c) is introduced with 100SCCM gas flow；
Ammonia/argon gas gaseous mixture 3d) is introduced with 5SCCM gas flow, to grow p-type ZnSe nanowire portions, this Process is maintained 15 minutes, then stops introducing ammonia/argon gas gaseous mixture；
High-purity hydrogen chloride gas 3e) is introduced with 2SCCM gas flow, for growing n-type ZnSe nanowire portions, this Process is maintained 15 minutes, then stops introducing high-purity hydrogen chloride gas；
Heating source 3f) is closed, stops introducing argon hydrogen protection gas, body of heater is naturally cooling to room temperature, open body of heater, taking-up is put In graphene layer on the silicon substrate covered with silica, the axial p-n junction nanometers of the ZnSe being grown on graphene layer are obtained Linear array；
4) PMMA insulating barriers is coated the axial p-n junction nano-wire arrays of ZnSe using spin-coating method and and fill its internal interstices Between, such as Fig. 3-E；
5) using plasma lithographic technique etching PMMA surface of insulating layer, makes the head of n-type ZnSe nanowire portions naked It is exposed at outside PMMA insulating barriers, exposed length is 50nm, such as Fig. 3-F；
6) e-beam evaporation is used to prepare thickness for 100nm in PMMA insulating layer top portions, width is 3 μm of square net Trellis aluminium electrode, such as Fig. 3-G；
7) using electron beam evaporation technique in titanium and 100nm of the exposed side of graphene layer successively evaporation thickness for 5nm Gold electrode, such as Fig. 3-H；
8) it is using sacrifice layer etching transfer method that device prepared by above-mentioned preparation method is overall from covered with silica It is transferred on silicon substrate in PET flexible substrates；
8a) will be by step 1 for 0.5% hydrofluoric acid solution using volume ratio) -7) prepared by silica in device Layer etching, etch period is 3 minutes, such as Fig. 3-I；Graphene layer and device architecture thereon is set integrally to be come off from silicon substrate, Such as Fig. 3-G；
8b) device architecture using deionized water cleaning graphene layer and thereon 2 times, such as Fig. 3-K；
8c) device architecture by graphene layer and thereon is transferred in PET flexible substrates, such as Fig. 3-L, and completion is entirely based on The preparation of the flexible optoelectronic part of graphene and the axial p-n junction nano-wire arrays of ZnSe, such as Fig. 3-M.
The flexible optoelectronic part based on graphene and the axial p-n junction nano-wire arrays of ZnSe prepared by the present embodiment can It is used as flexible blue light-emitting diode.
Embodiment 2：
1) bilayer graphene is placed on the silicon substrate covered with silica, such as Fig. 3-A；
2) 7nm gold nanoparticle films, such as Fig. 3-B, for CdTe are deposited on graphene layer using e-beam evaporation Catalysis nucleation in axial p-n junction nanowire growth process；
3) the CdTe axial directions p-n being grown on graphene layer is prepared in horizontal pipe furnace using chemical vapour deposition technique Junction nanowire array, such as Fig. 3-C and 3-D；
3a) porcelain boat for filling the CdTe powder that purity is 99.99% is positioned in the middle part of horizontal pipe furnace at i.e. heating source, The graphene layer that being placed on the silicon substrate covered with silica and surface evaporation has 7nm gold nanoparticle films is placed on water The rear portion of flat tube furnace；
3b) closed body of heater, is evacuated to pressure in body of heater and is less than 3 × 10-3pa；Open heating source and temperature is risen to 850 DEG C；
Argon hydrogen protection gas 3c) is introduced with 100SCCM gas flow；
Phosphine/argon gas gaseous mixture 3d) is introduced with 7SCCM gas flow, to grow p-type CdTe nanowire portions, this Process is maintained 20 minutes, then stops introducing phosphine/argon gas gaseous mixture；
High-purity hydrogen chloride gas 3e) is introduced with 3SCCM gas flow, for growing n-type CdTe nanowire portions, this Process is maintained 20 minutes, then stops introducing high-purity hydrogen chloride gas；
Heating source 3f) is closed, stops introducing argon hydrogen protection gas, body of heater is naturally cooling to room temperature, open body of heater, taking-up is put In graphene layer on the silicon substrate covered with silica, the axial p-n junction nanometers of the CdTe being grown on graphene layer are obtained Linear array；
4) PMMA insulating barriers is coated the axial p-n junction nano-wire arrays of CdTe using spin-coating method and and fill its internal interstices Between, such as Fig. 3-E；
5) using plasma lithographic technique etching PMMA surface of insulating layer, makes the head of n-type CdTe nanowire portions naked It is exposed at outside PMMA insulating barriers, exposed length is 100nm, such as Fig. 3-F；
6) e-beam evaporation is used to prepare thickness for 150nm in PMMA insulating layer top portions, width is 4 μm of square net Trellis aluminium electrode, such as Fig. 3-G；
7) using electron beam evaporation technique in titanium and 150nm of the exposed side of graphene layer successively evaporation thickness for 7nm Gold electrode, such as Fig. 3-H；
8) it is using sacrifice layer etching transfer method that device prepared by above-mentioned preparation method is overall from covered with silica It is transferred on silicon substrate in PDMS flexible substrates；
8a) will be by step 1 for 0.5% hydrofluoric acid solution using volume ratio) -7) prepared by silica in device Layer etching, etch period is 4 minutes, such as Fig. 3-I；Graphene layer and device architecture thereon is set integrally to be come off from silicon substrate, Such as Fig. 3-G；
8b) device architecture using deionized water cleaning graphene layer and thereon 3 times, such as Fig. 3-K；
8c) device architecture by graphene layer and thereon is transferred in PDMS flexible substrates, such as Fig. 3-L, completes whole base In the preparation of graphene and the flexible optoelectronic part of the axial p-n junction nano-wire arrays of CdTe, such as Fig. 3-M.
The flexible optoelectronic part based on graphene and the axial p-n junction nano-wire arrays of CdTe prepared by the present embodiment can It is used as flexible solar battery.
Embodiment 3：
1) 3 layer graphenes are placed on the silicon substrate covered with silica, such as Fig. 3-A；
2) 10nm gold nanoparticle films, such as Fig. 3-B, for ZnS are deposited on graphene layer using e-beam evaporation Catalysis nucleation in axial p-n junction nanowire growth process；
3) the ZnS axial directions p-n being grown on graphene layer is prepared in horizontal pipe furnace using chemical vapour deposition technique Junction nanowire array, such as Fig. 3-C and 3-D；
3a) porcelain boat for filling the ZnS powder that purity is 99.99% is positioned in the middle part of horizontal pipe furnace at i.e. heating source, The graphene layer that being placed on the silicon substrate covered with silica and surface evaporation has 10nm gold nanoparticle films is placed on The rear portion of horizontal pipe furnace；
3b) closed body of heater, is evacuated to pressure in body of heater and is less than 3 × 10-3Pa；Open heating source and temperature is risen to 1000 ℃；
Argon hydrogen protection gas 3c) is introduced with 100SCCM gas flow；
Phosphine/argon gas gaseous mixture 3d) is introduced with 10SCCM gas flow, to grow p-type ZnS nanowire portions, this Process is maintained 30 minutes, then stops introducing phosphine/argon gas gaseous mixture；
High-purity hydrogen chloride gas 3e) is introduced with 5SCCM gas flow, for growing n-type ZnS nanowire portions, this mistake Journey is maintained 30 minutes, then stops introducing high-purity hydrogen chloride gas；
Heating source 3f) is closed, stops introducing argon hydrogen protection gas, body of heater is naturally cooling to room temperature, open body of heater, taking-up is put In graphene layer on the silicon substrate covered with silica, the axial p-n junction nano wires of the ZnS being grown on graphene layer are obtained Array；
4) PMMA insulating barriers is coated the axial p-n junction nano-wire arrays of ZnS using spin-coating method and and fill its internal interstices Between, such as Fig. 3-E；
5) using plasma lithographic technique etching PMMA surface of insulating layer, makes the head of n-type ZnS nanowire portions naked It is exposed at outside PMMA insulating barriers, exposed length is 150nm, such as Fig. 3-F；
6) e-beam evaporation is used to prepare thickness for 200nm in PMMA insulating layer top portions, width is 5 μm of square net Trellis aluminium electrode, such as Fig. 3-G；
7) using electron beam evaporation technique in titanium and 200nm of the exposed side of graphene layer successively evaporation thickness for 10nm Gold electrode, such as Fig. 3-H；
8) it is using sacrifice layer etching transfer method that device prepared by above-mentioned preparation method is overall from covered with silica It is transferred on silicon substrate in PEN flexible substrates；
8a) will be by step 1 for 0.5% hydrofluoric acid solution using volume ratio) -7) prepared by silica in device Layer etching, etch period is 5 minutes, such as Fig. 3-I；Graphene layer and device architecture thereon is set integrally to be come off from silicon substrate, Such as Fig. 3-G；
8b) device architecture using deionized water cleaning graphene layer and thereon 3 times, such as Fig. 3-K；
8c) device architecture by graphene layer and thereon is transferred in PEN flexible substrates, such as Fig. 3-L, and completion is entirely based on The preparation of the flexible optoelectronic part of graphene and the axial p-n junction nano-wire arrays of ZnS, such as Fig. 3-M.
The flexible optoelectronic part based on graphene and the axial p-n junction nano-wire arrays of ZnS prepared by the present embodiment can It is used as flexible UV photodetector.

Claims (10)

1. a kind of flexible optoelectronic part based on graphene and the axial p-n junction nano-wire array of II-VI group semiconductor, its feature It is：Including one layer of flexible substrate (1), the flexible substrate (1) is provided with graphene layer (2), the graphene layer (2) and set By the II-VI being made up of p-type II-VI group semiconductor nanowires part (3) and n-type II-VI group semiconductor nanowires part (4) In the array structure of the axial p-n junction nano wire of race's semiconductor, the axial p-n junction nano-wire array gap of the II-VI group semiconductor Provided with PMMA (PolymethylMethacrylate, polymethyl methacrylate) insulating barrier (5), the n-type II-VI group half Nanowires part (4) array head is exposed outside the PMMA insulating barriers (5), is set on the PMMA insulating barriers (5) Have and gold/Ti electrode (7) is provided with aluminium electrode (6), the exposed side of the graphene layer (2).
2. opto-electronic device according to claim 1, it is characterised in that：The flexible substrate (1) is PET (Polydimethylsiloxane gathers by (Polyethyleneterephthalate, polyethylene terephthalate), PDMS Dimethyl siloxane), PEN (polyethylenenaphthalate, PEN) or PI (Polyimide, Polyimides).
3. opto-electronic device according to claim 1, it is characterised in that：The graphene layer (2) is individual layer or several layers of stone Black alkene.
4. opto-electronic device according to claim 1, it is characterised in that：Described p-type II-VI group semiconductor nanowires Partly (3) are p-type ZnSe, ZnS, ZnTe, CdSe, CdS or CdTe nano wire, the p-type II-VI group semiconductor nanowires portion Divide a diameter of 100-500nm of (3), length is 5-10 μm；Described n-type II-VI group semiconductor nanowires part (4) is n- Type ZnSe, ZnS, ZnTe, CdSe, CdS or CdTe nano wire, described n-type II-VI group semiconductor nanowires part (4) it is straight Footpath is 100-500nm, and length is 5-10 μm；Described p-type II-VI group semiconductor nanowires part (3) and described n-type The axial p-n junction nano wire of II-VI group semiconductor nanowires part (4) composition II-VI group semiconductor.
5. opto-electronic device according to claim 1, it is characterised in that：The aluminium electrode (6) is shaped as square net Shape, aluminium electrode (6) thickness is 100-200nm, and width is 3-5 μm.
6. opto-electronic device according to claim 1, it is characterised in that：The thickness of layer gold is in the gold/Ti electrode (7) 100-200nm, the thickness of titanium layer is 5-10nm, and layer gold is upper, and titanium layer is under.
7. a kind of preparation of the flexible optoelectronic part based on graphene and the axial p-n junction nano-wire array of II-VI group semiconductor Method, comprises the following steps：
1) graphene layer is placed on the silicon substrate covered with silica；
2) 5-10nm gold nanoparticle films are deposited on graphene layer using e-beam evaporation, for II-VI group semiconductor Catalysis nucleation in axial p-n junction nanowire growth process；
3) the II-VI group semiconductor axle being grown on graphene layer is prepared in horizontal pipe furnace using chemical vapour deposition technique To p-n junction nano-wire array；
3a) porcelain boat for filling the II-VI group semiconductor powder that purity is 99.99% is positioned in the middle part of horizontal pipe furnace and heated At source, being placed on the silicon substrate covered with silica and surface evaporation has the graphene layer of 5-10nm gold nanoparticle films It is placed on the rear portion of horizontal pipe furnace；
3b) closed body of heater, is evacuated to pressure in body of heater and is less than 3 × 10-3pa；Open heating source and temperature is risen into 800-1050 ℃；
Argon hydrogen protection gas 3c) is introduced with 100SCCM gas flow, the wherein gas volume ratio of argon gas and hydrogen is 95: 5；
Gaseous state p-doping source 3d) is introduced with 1-10SCCM gas flow, to grow p-type II-VI group semiconductor nanowires Part, this process is maintained 15-30 minutes, then stops introducing gaseous state p-doping source；
Gaseous state n-type doped source 3e) is introduced with 1-5SCCM gas flow, for growing n-type II-VI group semiconductor nanowires Part, this process is maintained 15-30 minutes, then stops introducing gaseous state n-type doped source；
Heating source 3f) is closed, stops introducing argon hydrogen protection gas, body of heater is down to room temperature naturally, open body of heater, taking-up is placed in covering There is graphene layer on the silicon substrate of silica, obtain the axial p-n junction of the II-VI group semiconductor being grown on graphene layer and receive Nanowire arrays；
4) PMMA insulating barriers are made to coat the axial p-n junction nano-wire array of II-VI group semiconductor and fill inside it using spin-coating method Gap；
5) using plasma lithographic technique etching PMMA surface of insulating layer, makes n-type II-VI group semiconductor nanowires part Head is exposed outside PMMA insulating barriers；
6) e-beam evaporation is used to prepare thickness for 100-200nm in PMMA insulating layer top portions, width is 3-5 μm of square Latticed aluminium electrode；
7) using electron beam evaporation technique in titanium and 100-200 of the exposed side of graphene layer successively evaporation thickness for 5-10nm The gold electrode of nanometer；
8) transfer method is etched using sacrifice layer to serve as a contrast device entirety prepared by above-mentioned preparation method from the silicon covered with silica It is transferred on bottom in flexible substrate.
8. method according to claim 7, it is characterised in that step 3) described in gaseous state p-doping source be ammonia/argon The gas volume ratio of gas gaseous mixture, wherein argon gas and ammonia be 95: 5, or phosphine/hydrogen, wherein hydrogen and phosphine gas body Product is than being 95: 5；Gaseous state n-type doped source is high-purity hydrogen chloride gas, and its purity is 99.999%.
9. method according to claim 7, it is characterised in that step 5) described in using plasma lithographic technique carve PMMA surface of insulating layer is lost, makes the head of n-type II-VI group semiconductor nanowires part exposed outside PMMA insulating barriers, n-type The exposed length of II-VI group semiconductor nanowires part is 50-150nm.
10. method according to claim 7, it is characterised in that step 8) described in sacrifice layer etching transfer method its step It is as follows：
A) will be by step 1 for 0.5% hydrofluoric acid solution using volume ratio) -7) prepared by silicon dioxide layer in device carve Erosion, etch period is 1-5 minutes；Graphene layer and device architecture thereon is set integrally to be come off from silicon substrate；
B) device architecture using deionized water (DI) cleaning graphene layer and thereon 2-3 times；
C) device architecture by graphene layer and thereon is transferred in flexible substrate.
CN201510585315.1A 2015-09-08 2015-09-08 Flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof Expired - Fee Related CN105304729B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510585315.1A CN105304729B (en) 2015-09-08 2015-09-08 Flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510585315.1A CN105304729B (en) 2015-09-08 2015-09-08 Flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof

Publications (2)

Publication Number Publication Date
CN105304729A CN105304729A (en) 2016-02-03
CN105304729B true CN105304729B (en) 2017-08-22

Family

ID=55201737

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510585315.1A Expired - Fee Related CN105304729B (en) 2015-09-08 2015-09-08 Flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof

Country Status (1)

Country Link
CN (1) CN105304729B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785443A (en) * 2016-08-26 2018-03-09 中国科学院金属研究所 Transparent flexible non-polar GaN nano wire ultraviolet detector and preparation method thereof
CN108428746A (en) * 2017-02-12 2018-08-21 无锡马丁格林光伏科技有限公司 A kind of absorbing film for thermophotovoltaic
CN107068864B (en) 2017-04-14 2019-05-28 武汉华星光电技术有限公司 The production method of Organic Thin Film Transistors
CN108538927B (en) * 2018-03-30 2019-12-31 南京信息工程大学 Flexible solar blind ultraviolet detector and preparation method thereof
CN108447925B (en) * 2018-04-27 2024-01-30 安阳师范学院 Flexible heterojunction solar cell array based on horizontally arranged nanowire films and preparation method thereof
CN109003889B (en) * 2018-07-30 2021-09-17 合肥工业大学 Preparation method of II-VI semiconductor film on flexible substrate
CN111326610A (en) * 2018-12-14 2020-06-23 中国科学院半导体研究所 Nano-column LED chip based on insulating substrate and preparation method thereof
CN110148526B (en) * 2019-04-24 2021-05-04 金华莱顿新能源科技有限公司 ZnSN nanowire material for super capacitor and preparation method thereof
CN111254414B (en) * 2020-01-21 2022-03-29 西安工程大学 Preparation and transfer method of flexible graphene-based silicon nanowire heterojunction
CN112216772B (en) * 2020-09-07 2022-03-08 深圳远芯光路科技有限公司 III-group nitride nanowire flexible light-emitting diode and preparation method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100084383A (en) * 2009-01-16 2010-07-26 양원동 Graphene solar cell module and manufacturing method thereof
CN102254969B (en) * 2011-08-17 2012-11-14 中国科学院苏州纳米技术与纳米仿生研究所 Nanopillar array-based photoelectric device and manufacturing method thereof
CN102593198B (en) * 2012-03-02 2013-11-27 合肥工业大学 Manufacturing method of II-VI group laminating integrated nano photovoltaic device and
CN104465807B (en) * 2014-12-18 2016-06-22 商丘师范学院 A kind of CZTS nano-array thin film solar photovoltaic cell and preparation method thereof

Also Published As

Publication number Publication date
CN105304729A (en) 2016-02-03

Similar Documents

Publication Publication Date Title
CN105304729B (en) Flexible optoelectronic part based on graphene and II VI races semiconductor axial direction p n junction nanowire arrays and preparation method thereof
Xia et al. CVD growth of perovskite/graphene films for high-performance flexible image sensor
CN101779271B (en) Structures of and methods for forming vertically aligned Si wire arrays
Plass et al. Flexible polymer‐embedded Si wire arrays
Lin et al. Graphene/semiconductor heterojunction solar cells with modulated antireflection and graphene work function
Perraud et al. Full process for integrating silicon nanowire arrays into solar cells
Stelzner et al. Silicon nanowire-based solar cells
Yang et al. Fully transparent resistive memory employing graphene electrodes for eliminating undesired surface effects
Zhang et al. Semiconductor nanostructure-based photovoltaic solar cells
US7999176B2 (en) Nanostructured solar cells
JP2007142386A (en) Photovoltaic structure with conductive nanowire array electrode
Xu et al. SnS2/Si vertical heterostructure for high-performance photodetection with large photocurrent and fast speed
TW200845404A (en) Photovoltaic cell and method of making thereof
CN102781816A (en) Fullerene-doped nanostructures and methods therefor
Kang et al. Transfer of ultrathin molybdenum disulfide and transparent nanomesh electrode onto silicon for efficient heterojunction solar cells
TW200952194A (en) Photovoltaic devices with enhanced efficiencies using high-aspect-ratio nanostructures
TW200919751A (en) Distributed coax photovoltaic device
Wu et al. Direct synthesis of high-density lead sulfide nanowires on metal thin films towards efficient infrared light conversion
JP5379811B2 (en) Photovoltaic devices using high aspect ratio nanostructures and methods for making same
CN205069659U (en) Flexible schottky solar cell based on graphite alkene and n - type II -VI semiconductor nanowire array of clan
CN101971360A (en) Composite nanorod-based structures for generating electricity
Tchoe et al. Individually addressable, high-density vertical nanotube Schottky diode crossbar array
CN107123468A (en) A kind of transparent conductive film containing function point analysis layer
Chen et al. Fabrication of silver sulfide thin films for efficient organic solar cells with high short-circuit currents based on double heterojunctions
Maity et al. Hybrid-organic-photodetector containing chemically treated ZnMgO layer with promising and reliable detectivity, responsivity and low dark current

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20170822

Termination date: 20200908