CN105304586A - Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same - Google Patents
Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same Download PDFInfo
- Publication number
- CN105304586A CN105304586A CN201510807435.1A CN201510807435A CN105304586A CN 105304586 A CN105304586 A CN 105304586A CN 201510807435 A CN201510807435 A CN 201510807435A CN 105304586 A CN105304586 A CN 105304586A
- Authority
- CN
- China
- Prior art keywords
- chip
- thin film
- layer
- metal layer
- monomer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
The invention discloses a chip embedded-type encapsulation structure with a reinforcing structure and an encapsulation method of the same, which belong to the technical field of semiconductor encapsulation. The chip embedded-type encapsulation structure with the reinforcing structure comprises chip single bodies and a thin film encapsulating body, wherein one or more than one chip single bodies are embedded from the back face into the thin film encapsulating body, the upper surfaces of the chip single bodies and the upper surface of the thin film encapsulating body are covered by an insulated thin film layer I, an opening of the insulated thin film layer I is disposed in the upper surface of a chip electrode, a re-wiring metal layer is formed on the upper surface of the insulated thin film layer, the re-wiring metal layer is respectively electrically connected to the chip electrodes, an input end/output end is disposed on the outmost layer of the re-wiring metal layer, a connecting part is formed at the input end/output end, and the back face of the thin film encapsulating body is equipped with a silicon substrate reinforcing plate. The encapsulation method disclosed by the invention reduces thicknesses of products, increases product reliability and realizes the multi-chip encapsulation structure through wafer-level technological forming.
Description
Technical field
The present invention relates to a kind of chip embedded encapsulating structure and method for packing thereof with strengthening structure, belonging to technical field of semiconductor encapsulation.
Background technology
Along with the development of semiconductor silicon technique, the critical size of chip is more and more less, in order to reduce costs, tends to the chip fabrication technique selecting more advanced integrated level higher when carrying out chip manufacturing, this just makes the size of chip more and more less, and the I/O density of chip surface is also more and more higher.But meanwhile the manufacturing process of printed circuit board (PCB) and surface mounting technology do not have greatly improved.For the chip that this I/O density ratio is higher, if carry out wafer level packaging, can form interconnection in order to ensure chip to be packaged and printed substrate must be low-density packaging pin by highdensity I/O fan-out, that is carry out the encapsulation of level chip fan-out, as shown in Figure 1, its chip to be packaged (1-1) realizes fan-out connection by substrate (1-6).But along with further developing of portable electric appts, electronic installation as mobile phone one class has been converted into the integrated system of comprehensive multifrequency nature from single communication tool, become versatile exquisite instrument, the deficiency of existing level chip fan-out packaging structure highlights day by day, is in particular in:
1, existing level chip fan-out packaging structure needs substrate (1-6) to realize fan-out, for the little chip with high number of pins then need multilager base plate (1-6) repeatedly fan-out could complete interconnection with printed substrate, not only increase mismatch probability and the heat radiation difficulty of ever-increasing interconnect pitch, reduce the reliability of product, and the existence of substrate (1-6) makes the thickness of whole encapsulating structure reduce, the body thickness of general existing level chip fan-out packaging structure is at 700 ~ 1500 microns;
2, existing level chip fan-out packaging structure needs substrate (1-6) to realize fan-out, often limits adding of the various chips with difference in functionality, is unfavorable for the integrated development of portable electric appts.
Summary of the invention
The object of the invention is to the deficiency overcoming current chip packages structure, a kind of thinning product thickness be provided, improve product reliability, realize the chip embedded encapsulating structure with reinforcement structure and the method for packing thereof of multi-chip package.
the object of the present invention is achieved like this:
A kind of chip embedded encapsulating structure with strengthening structure of the present invention, it comprises the chip monomer that upper surface is provided with chip electrode and related circuit layout, the upper surface of the chip body of described chip monomer covers chip surface passivation layer and offers chip surface passivation layer opening, the upper surface exposed chip surface passivation layer opening of chip electrode
Also comprise thin film encapsulation body, chip monomer described in one or more embeds in thin film encapsulation body by the back side, insulating thin layer I is covered at the upper surface of described chip monomer and the upper surface of thin film encapsulation body, and offer insulating thin layer I opening in the upper surface of described chip electrode, discontinuous interconnection metal layer again and insulating thin layer II is optionally formed at the upper surface of insulating thin layer I, described interconnection metal layer again fills insulating thin layer I opening, described interconnection metal layer again and chip electrode described in each realize being electrically connected, and optionally realize two or more association described chip electrode between electric connection, input/output terminal is provided with at the outermost layer of interconnection metal layer again, described insulating thin layer II covers interconnection metal layer again and exposes its input/output terminal, connector is formed at described input/output terminal place, the back side of described thin film encapsulation body arranges silica-based stiffener, described silica-based stiffener arranges integrated structure towards the one side of thin film encapsulation body.
Further, described integrated structure is a plurality of protrusion or is depressed in the texture structure of described silica-based stiffener towards that face of thin film encapsulation body.
Alternatively, described integrated structure is a kind of or several arbitrarily combination of fusiform structure, dots structure, wave structure.
Further, the thickness range of described silica-based stiffener is for being not more than 200 microns.
Further, the thickness range of described silica-based stiffener is 50 ~ 100 microns.
Further, described interconnection metal layer is again single or multiple lift.
Further, the input/output terminal of described interconnection metal layer is again arranged at the periphery of the vertical area of chip monomer.
Further, described insulating thin layer I opening is implanted into metal column, and described metal column connects interconnection metal layer and chip electrode again.
The method for packing of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention, comprises step:
Step one, gets IC wafers, and its surface is provided with chip electrode and related circuit layout, and the chip surface passivation layer being covered in wafer upper surface offers the upper surface of chip surface passivation layer opening exposed chip electrode above chip electrode;
Step 2, carries out parameter testing to IC wafers, and reduction process is carried out at the back side of qualified IC wafers, then cuts into plural independently chip monomer;
Step 3, the prop carrier body of prop carrier pastes stripping film;
Step 4, by chip monomer, upside-down mounting is on prop carrier in an orderly manner, and chip monomer is fixed by stripping film and prop carrier body;
Step 5, under vacuum conditions, prop carrier pastes thin film encapsulation chip monomer, forms thin film encapsulation body;
Step 6, is bonded to the back side of thin film encapsulation body by silica-based stiffener, and upper and lower 180 degree of upsets;
Step 7, peels off the surface of chip monomer and thin film encapsulation body, and cleans the surface of chip monomer, and remove residue, the upper surface of exposed chip electrode by prop carrier body and stripping film;
Step 8, pastes insulating thin layer I at the upper surface of chip monomer and the upper surface of thin film encapsulation body;
Step 9, utilizes photoetching process or laser technology to form the upper surface of insulating thin layer I opening exposed chip electrode;
Step 10, utilizes ripe Wiring technique again to form interconnection metal layer again, and be provided with input/output terminal at the outermost layer of interconnection metal layer again, insulating thin layer II covers interconnection metal layer again, and exposes its input/output terminal;
Step 11, forms connector at the input/output terminal place of interconnection metal layer again;
Step 12, is thinned to silica-based stiffener by the lower surface of silica-based stiffener and leaves thickness h, carries out plural of cutting formation independently packaging body by what complete above by wafer level technique with the chip embedded encapsulating structure strengthening structure.
Further, in step 6, described silica-based stiffener is provided with integrated structure towards that face at the back side of thin film encapsulation body, and this integrated structure is shaped by dry method or wet etching.
Compare and existing scheme, the invention has the beneficial effects as follows:
1, by thin film technique, in conjunction with wafer level, interconnection metal layer technology and flip-chip technology realize the fan-out packaging structure of single or multiple lift again in the present invention, be low-density packaging pin to guarantee that the little chip of the especially high number of pins of chip to be packaged or super tiny chip and printed substrate can realize highdensity I/O fan-out, do not need substrate, insert or underfill, be thinned whole encapsulating structure;
2, the present invention adopts the restructuring wafer encapsulation technology of chip package system collaborative design and advanced person and reliable interconnection technique, achieve the multichip packaging structure of difference in functionality, be conducive to the integrated development of portable electric appts, achieve the miniaturization of encapsulating structure, slimming and lightweight simultaneously;
3, apply materials of the present invention, adopts thin-film material to be embedded in wherein by chip to be packaged, makes all around four faces and the back side of chip to be packaged all obtain physics and electic protection, prevent external interference, improve the reliability of encapsulating products;
4, the present invention utilizes film Filming Technology to replace existing technology, reduce the requirement of packaging technology to equipment, the film back side is provided with the intensity that the silica-based stiffener strengthening structure not only further enhances thin film encapsulation body simultaneously, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer, contribute to the reliability improving encapsulating products.
Accompanying drawing explanation
Fig. 1 is the generalized section of existing level chip fan-out packaging structure;
Fig. 2 is the flow chart of the method for packing of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention;
Fig. 3 A is the generalized section of the embodiment one of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention;
Fig. 3 B is the front schematic view of thin film encapsulation body in Fig. 3 A, chip monomer, soldered ball position relationship;
Fig. 4 A ~ 4O is the flow chart of the method for packing of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention of Fig. 3 A;
Fig. 5 A is the generalized section of the embodiment two of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention;
Fig. 5 B is the front schematic view of thin film encapsulation body in Fig. 5 A, chip monomer, soldered ball position relationship;
Fig. 6 is the generalized section of the embodiment three of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention;
In figure:
IC wafers 100
Chip monomer 10, chip monomer 20
Chip body 11, chip body 21
Chip electrode 13, chip electrode 23
Chip surface passivation layer 15, chip surface passivation layer 25
Chip surface passivation layer opening 151, chip surface passivation layer opening 251
Thin film encapsulation body 3
Plural layer is Wiring technique layer 4 again
Interconnection metal layer 41 again
Input/output terminal 411
Insulating thin layer I 51
Insulating thin layer I opening 511
Insulating thin layer II 52
Connector 6
Silica-based stiffener 7;
Prop carrier T1
Prop carrier body T11
Stripping film T13
Line of cut 8.
Embodiment
See Fig. 2, the technological process of the method for packing of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention is as follows:
S1: get IC wafers, carries out reduction process to the back side of IC wafers, then cuts into plural independently chip monomer;
S2: by the upside-down mounting of chip monomer on prop carrier;
S3: paste wrap film to the chip monomer on prop carrier under vacuum conditions, forms thin film encapsulation body;
S4: the back side silica-based stiffener being bonded to thin film encapsulation body;
S5: prop carrier is peeled off chip monomer and thin film encapsulation body;
S6: paste insulating thin layer I at the upper surface of chip monomer and the upper surface of thin film encapsulation body;
S7: utilize photoetching process or laser technology to form the upper surface of insulating thin layer I opening exposed chip electrode;
S8: utilize ripe Wiring technique again to form interconnection metal layer again, be provided with input/output terminal at the outermost layer of interconnection metal layer again, insulating thin layer II covers interconnection metal layer again, and exposes its input/output terminal;
S9: form connector at the input/output terminal place of interconnection metal layer again;
S10: the said structure completing packaging technology is cut into a plural number encapsulation monomer.
Describe the present invention more fully hereinafter with reference to accompanying drawing now, exemplary embodiment of the present invention shown in the drawings, thus scope of the present invention is conveyed to those skilled in the art by the disclosure fully.But the present invention can realize in many different forms, and should not be interpreted as being limited to the embodiment set forth here.
Embodiment one, see Fig. 3 A and Fig. 3 B
Fig. 3 A is the generalized section of the embodiment one of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention, chip embedded encapsulating structure of the present invention comprises the chip monomer 10 that a back side embeds thin film encapsulation body 3, the upper surface of the chip body 11 of chip monomer 10 is provided with chip electrode 13 and related circuit layout thereof, chip surface passivation layer 15 covers the upper surface of chip body 11 and offers chip surface passivation layer opening 151, the upper surface exposed chip surface passivation layer opening 151 of chip electrode 13.The material of thin film encapsulation body 3 includes but not limited to epoxy-plastic packaging material; it is generally curing agent with High Performance Phenolic Resins; adding silicon powder etc. is filler; and add multiple additive mixture and form; it is first in molten condition at high temperature 175 ~ 185 DEG C; all around four faces and the back side of tight parcel chip monomer 10; can harden gradually after cooling; final molding; all around four faces and the back side of chip monomer 10 is made all to obtain physics and electic protection; prevent external interference, to improve its reliability.
Insulating thin layer I 51 covers the upper surface of chip monomer 10 and the upper surface of thin film encapsulation body 3, and offer insulating thin layer I opening 511 in the upper surface of chip electrode 13 by photoetching process or laser technology, the size of insulating thin layer I opening 511 is not more than the size of chip surface passivation layer opening 151, the rounded or polygon such as quadrangle, hexagon of the shape of its cross section.The material of insulating thin layer I 51 is generally the macromolecule such as epoxy resin, polyimides organic insulating material.Discontinuous interconnection metal layer again 41 is optionally formed at the upper surface of insulating thin layer I 51 and fills insulating thin layer I opening 511.Interconnection metal layer 41 and chip electrode 13 realize being electrically connected again.Also can implant the metal column that copper etc. has conducting function in insulating thin layer I opening 511, this metal column connects interconnection metal layer 41 again and realizes being electrically connected with chip electrode 13.Interconnection metal layer 41 can be individual layer again, and as shown in Figure 3A, be provided with input/output terminal 411 at the outermost layer of interconnection metal layer 41 again, the number of input/output terminal 411 is arranged according to actual needs.For little chip or the super tiny chip of high number of pins, its input/output terminal 411 can be made to be arranged at the periphery of the vertical area of little chip or super tiny chip by the epitaxy technology of wafer level interconnection metal layer again, so that electrode signal fan-out that is individuality is less, electrode comparatively dense connects.As little for 1 × 1mm chip made 3 × 3mm encapsulating structure, I/O:20, pitch:0.4mm.Connector 6 can be formed at input/output terminal 411 place; connector 6 can be solder bumps, welding block or other metal connecting piece; solder bumps for connector 6 in Fig. 3 B; show the front schematic view of chip monomer 10 and the position relationship of thin film encapsulation body 3, solder bumps; visible; chip monomer 10 is arranged at the inside of thin film encapsulation body 3, and it all obtains physics and electic protection in four faces and the back side all around, improves its reliability.
The back side of thin film encapsulation body 3 arranges the silica-based stiffener 7 of silicon material, its thickness is not more than 200 microns, and be good with its thickness range 50 ~ 100 microns, not only strengthen the intensity of thin film encapsulation body 3, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer 10, also contribute to the reliability promoting encapsulating products.
A kind of encapsulating structure with strengthening the chip embedded encapsulating structure of structure and can obtain body thickness 500 ~ 800 microns of the present invention, thinner more than traditional encapsulating structure, gentlier, less.Further, this silica-based stiffener is provided with the integrated structure of the shape such as fusiform structure, dots structure, wave structure of a plurality of protrusion or depression towards the one side of thin film encapsulation body, to strengthen the adhesion of itself and thin film encapsulation body 3, also the reliability improving encapsulating products is contributed to, as shown in three profiles amplified of Fig. 3 A.This integrated structure also can be the mixing composition of the shapes such as fusiform structure, dots structure, wave structure.
The method for packing of above-described embodiment one of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention, see Fig. 4 A to 4P, its technique comprises the steps:
Step one, see Fig. 4 A, get IC wafers 100, its surface is provided with chip electrode 13 and related circuit layout, and the chip surface passivation layer 15 being covered in IC wafers 100 upper surface offers the upper surface of chip surface passivation layer opening 151 exposed chip electrode 13 above chip electrode 13;
Step 2, see Fig. 4 B, carries out parameter testing to the IC wafers 100 shown in Fig. 4 A, reduction process is carried out at the back side of qualified IC wafers 100, its thickness thinning is determined according to actual conditions, then cuts into plural independently chip monomer 10, as shown in Figure 4 B;
Step 3, see Fig. 4 C, the prop carrier body T11 of prop carrier T1 pastes stripping film T13, and stripping film T13 can be UV stripping film, can also be hot stripping film, and this stripping film T13 is stripped in subsequent technique;
Step 4, see Fig. 4 D, by the chip monomer 10 of test passes, upside-down mounting is on prop carrier T1 in an orderly manner, and the front of chip monomer 10 is fixed by stripping film T13 and prop carrier body T11, and the distance between adjacent two chip monomers 10 needs to carry out arranging and increasing according to actual process;
Step 5, see Fig. 4 E, prop carrier T1 pastes thin film encapsulation chip monomer 10, form thin film encapsulation body 3, paste process entails to carry out under vacuum conditions, and by film heating to 175 ~ 185 DEG C, when making it be in molten condition, complete gapless attaching process;
Step 6, see Fig. 4 F, is bonded to another surface of thin film encapsulation body 3 by silica-based stiffener 7, and upper and lower 180 degree of upsets;
Step 7, see Fig. 4 G, by stripping technology, peels off the surface of chip monomer 10 and thin film encapsulation body 3, and cleans the surface of chip monomer 10, and remove residue, the upper surface of exposed chip electrode 13 by prop carrier body T11 and stripping film T13;
Step 8, see Fig. 4 H, pastes insulating thin layer I 51 at the upper surface of chip monomer 10 and the upper surface of thin film encapsulation body 3;
Step 9, see Fig. 4 I, utilizes photoetching process or laser technology to form the upper surface of insulating thin layer I opening 511 exposed chip electrode 13;
Step 10, see Fig. 4 J and 4K, the ripe layer process of wiring metal is again utilized to form interconnection metal layer 41 again, several input/output terminals 411 are provided with at the outermost layer of interconnection metal layer 41 again, as shown in fig. 4j, insulating thin layer II 52 covers interconnection metal layer 41 again, and exposes the input/output terminal 411 of interconnection metal layer 41 again;
Step 11, see Fig. 4 L, form connector 6 at input/output terminal 411 place of interconnection metal layer 41 again, connector 6 can be soldered ball projection, welding block or other metal connecting piece;
Step 12, see Fig. 4 M, is thinned to Rational Thickness h by the lower surface of silica-based stiffener 7, is cut along line of cut 8 the chip embedded encapsulating structure completed above by wafer level technique, forms plural independently packaging body, as shown in Fig. 4 N.
The additive with functions such as that resist warping, antistatic, reinforcement particles is added in thin film encapsulation body 3 in above-mentioned steps five, strengthen the proper property of thin film encapsulation body 3, the silica-based stiffener 7 in step 12 can be made in the encapsulating structure of some product to remove completely, to make the thickness of whole encapsulating structure thinning further, again the chip embedded encapsulating structure completed above by wafer level technique is cut along line of cut 8, form plural independently packaging body, as shown in Fig. 4 O.
In above-mentioned steps six, get silica-based stiffener 7 a surface be manufactured with integrated structure, this integrated structure is generally be shaped by dry method or wet etching in advance, also simply can be shaped by physical method, such as, use forming tool to apply the shaping surface of external force at silica-based stiffener 7.During another surface bond with thin film encapsulation body 3 of silica-based stiffener 7, that having a silica-based stiffener 7 of integrated structure facing to thin film encapsulation body 3, to improve the reliability of encapsulating products.
Embodiment two, see Fig. 5 A and Fig. 5 B
The number of chip monomer can be more than one, adopts chip package system collaborative design, can realize the chip package of more difference in functionalitys.
Fig. 5 A is the generalized section of the embodiment two of a kind of chip embedded encapsulating structure with reinforcement structure of the present invention, chip embedded encapsulating structure of the present invention comprises chip monomer 10 and the chip monomer 20 that two back sides embed thin film encapsulation body 3, and its upper surface is generally flush formation.The material of thin film encapsulation body 3 includes but not limited to epoxy-plastic packaging material; it is generally curing agent with High Performance Phenolic Resins; adding silicon powder etc. is filler; and add multiple additive mixture and form; it is first in molten condition at high temperature 175 ~ 185 DEG C; all around four faces and the back side of tight parcel chip monomer 10; can harden gradually after cooling; final molding; all around four faces and the back side of chip monomer 10 and chip monomer 20 is made all to obtain physics and electic protection; prevent external interference, to improve its reliability.
The upper surface of the chip body 11 of chip monomer 10 is provided with chip electrode 13 and related circuit layout thereof, chip surface passivation layer 15 covers the upper surface of chip body 11 and offers chip surface passivation layer opening 151, the upper surface exposed chip surface passivation layer opening 151 of chip electrode 13.The upper surface of the chip body 21 of chip monomer 20 is provided with chip electrode 23 and related circuit layout thereof, chip surface passivation layer 25 covers the upper surface of chip body 21 and offers chip surface passivation layer opening 251, the upper surface exposed chip surface passivation layer opening 251 of chip electrode 23.Insulating thin layer I 51 covers the upper surface of chip monomer 10, the upper surface of chip monomer 20 and the upper surface of thin film encapsulation body 3, and offer insulating thin layer I opening 511 in the upper surface of chip electrode 13, the size of insulating thin layer I opening 511 is not more than the size of chip surface passivation layer opening 151, chip surface passivation layer opening 251, the rounded or polygon such as quadrangle, hexagon of the shape of its cross section.Interconnection metal layer 41 is formed at the upper surface of insulating thin layer I 51 and fills insulating thin layer I opening 511 again.Interconnection metal layer 41 realizes being electrically connected with chip electrode 13, chip electrode 23 respectively again.Also can implant the metal column that copper etc. has conducting function in insulating thin layer I opening 511, this metal column connects interconnection metal layer 41 and chip electrode 13, chip electrode 23 respectively again, realizes being electrically connected.Interconnection metal layer 41 can be individual layer again, and as shown in Figure 5A, the part of chip monomer 10 and chip monomer 20 adjacent again interconnection metal layer 41 is connected chip monomer 10 and chip monomer 20 simultaneously, makes to realize between chip monomer 10 and chip monomer 20 being electrically connected.In actual package structure, if the number of chip monomer is more than three or three, non-conterminous but also can realize being electrically connected by interconnection metal layer again between two or more chip electrodes be associated.Be provided with several input/output terminals 411 at the outermost layer of interconnection metal layer 41 again, the parameter such as number, position, shape of input/output terminal 411 is arranged according to actual needs.Connector 6 can be formed at input/output terminal 411 place; connector 6 can be solder bumps, welding block or other metal connecting piece; solder bumps for connector 6 in Fig. 5 B; show the front schematic view of chip monomer 10, chip monomer 20 and the position relationship of thin film encapsulation body 3, solder bumps; visible chip monomer 10, chip monomer 20 are arranged at the inside of thin film encapsulation body 3; it all obtains physics and electic protection in four faces and the back side all around, improves its reliability.
The back side of thin film encapsulation body 3 arranges the silica-based stiffener 7 of silicon material, not only further enhance the intensity of thin film encapsulation body 3, reduce the angularity of whole encapsulating structure, and strengthen the heat dispersion of chip monomer 10, chip monomer 20, also contribute to the reliability improving encapsulating products.
The method for packing of above-described embodiment two and the method for packing of embodiment one similar, difference is: interconnection metal layer 41 needs to set up the connection between chip monomer 10 and chip monomer 20 again, realizes the electric connection of whole encapsulating structure.
Embodiment three, see Fig. 6
The encapsulating structure of embodiment three and embodiment one, embodiment two are similar, and difference is: interconnection metal layer 41 also can form plural layer Wiring technique layer again for two-layer or two-layer above again, to realize the fan-out packaging structure of multilayer, as shown in Figure 6.Plural layer again Wiring technique layer with three layers of example; comprise again interconnection metal layer 41, again interconnection metal layer 43, again interconnection metal layer 45; be communicated with to meet multi information; and insulating thin layer II 52 is also multilayer; with plural layer again Wiring technique layer mate; be separately positioned on wherein, play the effects such as insulation, protection, reinforcing.The material of insulating thin layer II 52 is generally the macromolecule such as epoxy resin, polyimides organic insulating material.Be provided with input/output terminal at the outermost layer of plural layer Wiring technique layer again, the number of input/output terminal is arranged according to actual needs.Plural layer again Wiring technique layer 4 input/output terminal place formed connector 6, connector 6 can be solder bumps, welding block or other metal connecting piece.
The method for packing of the method for packing of above-described embodiment three and embodiment one, embodiment two is similar, and difference is: plural layer again Wiring technique layer needs by repeatedly interconnection metal layer process forming again.
A kind of chip embedded encapsulating structure and method for packing thereof with strengthening structure of the present invention is not limited to above preferred embodiment, chip monomer 10 of the present invention, chip monomer 20 is for IC chip, because it can reduce body thickness effectively, improve the flexibility of encapsulation, at the advantage highly significant of slim and microminiaturized application aspect, and its good heat dispersion, the application of this encapsulation also can expand to many different fields, as wireless, optics etc., but be not limited to this, any those skilled in the art without departing from the spirit and scope of the present invention, according to any amendment that technical spirit of the present invention is done above embodiment, equivalent variations and modification, all fall in protection range that the claims in the present invention define.
Claims (10)
1. the chip embedded encapsulating structure with reinforcement structure, it comprises the chip monomer that upper surface is provided with chip electrode and related circuit layout, the upper surface of the chip body of described chip monomer covers chip surface passivation layer and offers chip surface passivation layer opening, the upper surface exposed chip surface passivation layer opening of chip electrode
It is characterized in that: also comprise thin film encapsulation body, chip monomer described in one or more embeds in thin film encapsulation body by the back side, insulating thin layer I is covered at the upper surface of described chip monomer and the upper surface of thin film encapsulation body, and offer insulating thin layer I opening in the upper surface of described chip electrode, discontinuous interconnection metal layer again and insulating thin layer II is optionally formed at the upper surface of insulating thin layer I, described interconnection metal layer again fills insulating thin layer I opening, described interconnection metal layer again and chip electrode described in each realize being electrically connected, and optionally realize two or more association described chip electrode between electric connection, input/output terminal is provided with at the outermost layer of interconnection metal layer again, described insulating thin layer II covers interconnection metal layer again and exposes its input/output terminal, connector is formed at described input/output terminal place, the back side of described thin film encapsulation body arranges silica-based stiffener, described silica-based stiffener arranges integrated structure towards the one side of thin film encapsulation body.
2. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: described integrated structure is a plurality of protrusion or is depressed in the texture structure of described silica-based stiffener towards that face of thin film encapsulation body.
3. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1 and 2, is characterized in that: described integrated structure is a kind of or several arbitrarily combination of fusiform structure, dots structure, wave structure.
4. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: the thickness range of described silica-based stiffener is for being not more than 200 microns.
5. a kind of chip embedded encapsulating structure with strengthening structure according to claim 4, is characterized in that: the thickness range of described silica-based stiffener is 50 ~ 100 microns.
6. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: described interconnection metal layer is again single or multiple lift.
7. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1 or 6, is characterized in that: the input/output terminal of described interconnection metal layer is again arranged at the periphery of the vertical area of chip monomer.
8. a kind of chip embedded encapsulating structure with strengthening structure according to claim 1, is characterized in that: described insulating thin layer I opening is implanted into metal column, and described metal column connects interconnection metal layer and chip electrode again.
9., with a method for packing for the chip embedded encapsulating structure of reinforcement structure, comprise step:
Step one, gets IC wafers, and its surface is provided with chip electrode and related circuit layout, and the chip surface passivation layer being covered in wafer upper surface offers the upper surface of chip surface passivation layer opening exposed chip electrode above chip electrode;
Step 2, carries out parameter testing to IC wafers, and reduction process is carried out at the back side of qualified IC wafers, then cuts into plural independently chip monomer;
Step 3, the prop carrier body of prop carrier pastes stripping film;
Step 4, by chip monomer, upside-down mounting is on prop carrier in an orderly manner, and chip monomer is fixed by stripping film and prop carrier body;
Step 5, under vacuum conditions, prop carrier pastes thin film encapsulation chip monomer, forms thin film encapsulation body;
Step 6, is bonded to the back side of thin film encapsulation body by silica-based stiffener, and upper and lower 180 degree of upsets;
Step 7, peels off the surface of chip monomer and thin film encapsulation body, and cleans the surface of chip monomer, and remove residue, the upper surface of exposed chip electrode by prop carrier body and stripping film;
Step 8, pastes insulating thin layer I at the upper surface of chip monomer and the upper surface of thin film encapsulation body;
Step 9, utilizes photoetching process or laser technology to form the upper surface of insulating thin layer I opening exposed chip electrode;
Step 10, utilizes ripe Wiring technique again to form interconnection metal layer again, and be provided with input/output terminal at the outermost layer of interconnection metal layer again, insulating thin layer II covers interconnection metal layer again, and exposes its input/output terminal;
Step 11, forms connector at the input/output terminal place of interconnection metal layer again;
Step 12, is thinned to silica-based stiffener by the lower surface of silica-based stiffener and leaves thickness h, carries out plural of cutting formation independently packaging body by what complete above by wafer level technique with the chip embedded encapsulating structure strengthening structure.
10. the method for packing of a kind of chip embedded encapsulating structure with reinforcement structure according to claim 9, it is characterized in that: in step 6, described silica-based stiffener is provided with integrated structure towards that face at the back side of thin film encapsulation body, and this integrated structure is shaped by dry method or wet etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510807435.1A CN105304586A (en) | 2015-11-20 | 2015-11-20 | Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510807435.1A CN105304586A (en) | 2015-11-20 | 2015-11-20 | Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105304586A true CN105304586A (en) | 2016-02-03 |
Family
ID=55201652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510807435.1A Pending CN105304586A (en) | 2015-11-20 | 2015-11-20 | Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105304586A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107644861A (en) * | 2017-10-27 | 2018-01-30 | 无锡吉迈微电子有限公司 | Chip cloth wire encapsulation construction and its realizes technique again |
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN108231607A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| WO2019127337A1 (en) * | 2017-12-28 | 2019-07-04 | 江阴长电先进封装有限公司 | Packaging structure of semiconductor chip and packaging method therefor |
| CN110534435A (en) * | 2019-08-01 | 2019-12-03 | 广东佛智芯微电子技术研究有限公司 | The packaging method of the heterogeneous integrated fan-out package structure of 3-D multi-chip |
| US11114315B2 (en) | 2017-11-29 | 2021-09-07 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
| US11232957B2 (en) | 2017-11-29 | 2022-01-25 | Pep Inovation Pte. Ltd. | Chip packaging method and package structure |
| US11233028B2 (en) | 2017-11-29 | 2022-01-25 | Pep Inovation Pte. Ltd. | Chip packaging method and chip structure |
| US11610855B2 (en) | 2017-11-29 | 2023-03-21 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
| WO2023123106A1 (en) * | 2021-12-29 | 2023-07-06 | 华为技术有限公司 | Chip packaging structure and preparation method therefor, and electronic device |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1674223A (en) * | 2004-03-25 | 2005-09-28 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| CN101083255A (en) * | 2003-09-15 | 2007-12-05 | 罗姆和哈斯电子材料有限责任公司 | Device package and methods for the fabrication and testing thereof |
| US20080088004A1 (en) * | 2006-10-17 | 2008-04-17 | Advanced Chip Engineering Technology Inc. | Wafer level package structure with build up layers |
| JP2010056266A (en) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | Method of manufacturing semiconductor apparatus |
| CN102194718A (en) * | 2010-03-15 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming the same |
| CN102299052A (en) * | 2010-06-22 | 2011-12-28 | 无锡华润上华半导体有限公司 | Method for manufacturing wafer |
| CN102479878A (en) * | 2010-11-19 | 2012-05-30 | 金元求 | Solar cell manufacturing method and solar cell manufactured by manufacturing method |
| CN102694052A (en) * | 2011-03-22 | 2012-09-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102778479A (en) * | 2011-05-09 | 2012-11-14 | 中国科学院微电子研究所 | Integratable amorphous metal oxide semiconductor gas sensor |
| CN102778481A (en) * | 2011-05-09 | 2012-11-14 | 中国科学院微电子研究所 | Induction gate type amorphous metal oxide TFT gas sensor |
| CN103426850A (en) * | 2013-08-27 | 2013-12-04 | 南通富士通微电子股份有限公司 | Wafer-level chip size packaging structure |
| CN104169367A (en) * | 2012-03-16 | 2014-11-26 | 大赛路·赢创有限公司 | Sealant paste and sealing method |
| CN205122562U (en) * | 2015-11-20 | 2016-03-30 | 江阴长电先进封装有限公司 | Chip embedded package structure with additional strengthening |
-
2015
- 2015-11-20 CN CN201510807435.1A patent/CN105304586A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101083255A (en) * | 2003-09-15 | 2007-12-05 | 罗姆和哈斯电子材料有限责任公司 | Device package and methods for the fabrication and testing thereof |
| CN1674223A (en) * | 2004-03-25 | 2005-09-28 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| US20080088004A1 (en) * | 2006-10-17 | 2008-04-17 | Advanced Chip Engineering Technology Inc. | Wafer level package structure with build up layers |
| JP2010056266A (en) * | 2008-08-28 | 2010-03-11 | Casio Comput Co Ltd | Method of manufacturing semiconductor apparatus |
| CN102194718A (en) * | 2010-03-15 | 2011-09-21 | 新科金朋有限公司 | Semiconductor device and method of forming the same |
| CN102299052A (en) * | 2010-06-22 | 2011-12-28 | 无锡华润上华半导体有限公司 | Method for manufacturing wafer |
| CN102479878A (en) * | 2010-11-19 | 2012-05-30 | 金元求 | Solar cell manufacturing method and solar cell manufactured by manufacturing method |
| CN102694052A (en) * | 2011-03-22 | 2012-09-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN102778479A (en) * | 2011-05-09 | 2012-11-14 | 中国科学院微电子研究所 | Integratable amorphous metal oxide semiconductor gas sensor |
| CN102778481A (en) * | 2011-05-09 | 2012-11-14 | 中国科学院微电子研究所 | Induction gate type amorphous metal oxide TFT gas sensor |
| CN104169367A (en) * | 2012-03-16 | 2014-11-26 | 大赛路·赢创有限公司 | Sealant paste and sealing method |
| CN103426850A (en) * | 2013-08-27 | 2013-12-04 | 南通富士通微电子股份有限公司 | Wafer-level chip size packaging structure |
| CN205122562U (en) * | 2015-11-20 | 2016-03-30 | 江阴长电先进封装有限公司 | Chip embedded package structure with additional strengthening |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108231606A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN108231607A (en) * | 2016-11-29 | 2018-06-29 | Pep创新私人有限公司 | Chip packaging method and encapsulating structure |
| CN107644861A (en) * | 2017-10-27 | 2018-01-30 | 无锡吉迈微电子有限公司 | Chip cloth wire encapsulation construction and its realizes technique again |
| US11114315B2 (en) | 2017-11-29 | 2021-09-07 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
| US11232957B2 (en) | 2017-11-29 | 2022-01-25 | Pep Inovation Pte. Ltd. | Chip packaging method and package structure |
| US11233028B2 (en) | 2017-11-29 | 2022-01-25 | Pep Inovation Pte. Ltd. | Chip packaging method and chip structure |
| US11610855B2 (en) | 2017-11-29 | 2023-03-21 | Pep Innovation Pte. Ltd. | Chip packaging method and package structure |
| WO2019127337A1 (en) * | 2017-12-28 | 2019-07-04 | 江阴长电先进封装有限公司 | Packaging structure of semiconductor chip and packaging method therefor |
| CN110534435A (en) * | 2019-08-01 | 2019-12-03 | 广东佛智芯微电子技术研究有限公司 | The packaging method of the heterogeneous integrated fan-out package structure of 3-D multi-chip |
| WO2023123106A1 (en) * | 2021-12-29 | 2023-07-06 | 华为技术有限公司 | Chip packaging structure and preparation method therefor, and electronic device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105304586A (en) | Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same | |
| CN105304605A (en) | Chip embedded encapsulation structure and encapsulation method of same | |
| US8216918B2 (en) | Method of forming a packaged semiconductor device | |
| EP2965353B1 (en) | A substrate-less interposer | |
| US11621243B2 (en) | Thin bonded interposer package | |
| US20110209908A1 (en) | Conductor package structure and method of the same | |
| CN105261609A (en) | Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices | |
| WO2017111956A1 (en) | Semiconductor package with electromagnetic interference shielding | |
| US11456243B2 (en) | Semiconductor package structure and manufacturing method thereof | |
| CN104037133B (en) | Fan-out packaging method and structure of wafer-level chip | |
| US20110031606A1 (en) | Packaging substrate having embedded semiconductor chip | |
| US9589908B1 (en) | Methods to improve BGA package isolation in radio frequency and millimeter wave products | |
| CN104505382A (en) | Wafer-level fan-out PoP encapsulation structure and making method thereof | |
| CN111883521A (en) | Multi-chip 3D packaging structure and manufacturing method thereof | |
| CN205122578U (en) | Chip embedded package structure of no solder ball | |
| KR20140108138A (en) | Packaged semiconductor device | |
| CN101145526A (en) | Semiconductor package structure having electromagnetic shielding and making method thereof | |
| KR101653563B1 (en) | Stack type semiconductor package and method for manufacturing the same | |
| US20130256915A1 (en) | Packaging substrate, semiconductor package and fabrication method thereof | |
| CN205122579U (en) | Chip embedded package structure | |
| CN205122562U (en) | Chip embedded package structure with additional strengthening | |
| US7160798B2 (en) | Method of making reinforced semiconductor package | |
| CN105304587A (en) | Encapsulation structure increasing chip reliability and wafer-level manufacture method of same | |
| US20140145348A1 (en) | Rf (radio frequency) module and method of maufacturing the same | |
| Lee et al. | Three-dimensional integrated circuit (3D-IC) package using fan-out technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160203 |
|
| RJ01 | Rejection of invention patent application after publication |