CN105304559A - Array substrate manufacturing method, array substrate and display device - Google Patents
Array substrate manufacturing method, array substrate and display device Download PDFInfo
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- CN105304559A CN105304559A CN201510646811.3A CN201510646811A CN105304559A CN 105304559 A CN105304559 A CN 105304559A CN 201510646811 A CN201510646811 A CN 201510646811A CN 105304559 A CN105304559 A CN 105304559A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
The invention relates to an array substrate manufacturing method, an array substrate and a display device and belongs to the display technology field. The method comprises steps that, a first metal pattern is formed on a backing substrate, an insulation layer is formed on the backing substrate on which the first metal patter is formed, a static shielding layer is formed at a peripheral area of the backing substrate on which the insulation layer is formed, a peripheral area metal layer is formed at the peripheral area of the backing substrate on which the static shielding layer is formed; a peripheral pattern is formed through the composition technology on the peripheral area metal layer and the static shielding layer. According to the array substrate manufacturing method, after the static shielding layer is formed at the peripheral area of the backing substrate, the metal layer is formed on the static shielding layer of the peripheral area, a problem that a relatively low product yield caused by damage to the circuit on the array substrate because of ESD can be solved, the ESD is generated by the metal layer during formation in the peripheral area and the first metal pattern, the ESD is prevented from being generated by the metal layer during formation in the peripheral area and the first metal pattern, and the yield is improved.
Description
Technical field
The present invention relates to Display Technique field, particularly a kind of manufacture method of array base palte, array base palte and display unit.
Background technology
Array base palte is the important component part of display unit, and array base palte generally includes underlay substrate and is formed at the various film layer structures on underlay substrate.
Have a kind of manufacture method of array base palte in correlation technique, first the method forms the first metal pattern on underlay substrate, forms insulating barrier, semiconductor layer and the second metal pattern successively afterwards on the underlay substrate being formed with the first metal pattern.
Inventor is realizing in process of the present invention, find that aforesaid way at least exists following defect: said method is being formed in the process for the formation of the metal level of the second metal pattern, the first metal pattern due to outer peripheral areas may arrange uneven (arrangement as holding wire may be uneven), the metal level of outer peripheral areas may produce ESD (Electro-Staticdischarge with the first metal pattern of outer peripheral areas when being formed, Electro-static Driven Comb) and the circuit destroyed on array base palte, product yield is lower.
Summary of the invention
The circuit destroyed on array base palte in order to the metal level solving outer peripheral areas in correlation technique may produce ESD with the first metal pattern when being formed, the problem that product yield is lower, the invention provides a kind of manufacture method of array base palte, array base palte and display unit.Described technical scheme is as follows:
According to a first aspect of the invention, provide a kind of manufacture method of array base palte, described method comprises:
Underlay substrate is formed the first metal pattern;
The underlay substrate being formed with described first metal pattern forms insulating barrier;
Electrostatic screen layer is formed in the outer peripheral areas of the underlay substrate being formed with described insulating barrier;
Outer peripheral areas metal level is formed in the outer peripheral areas of the underlay substrate being formed with described electrostatic screen layer;
On described outer peripheral areas metal level and described electrostatic screen layer, form peripheral pattern by patterning processes, the shape of described peripheral pattern is identical with the shape of the metal pattern of described outer peripheral areas.
Optionally, after the described underlay substrate being formed with described first metal pattern forms insulating barrier, described method also comprises:
Transparent conductive film layer is formed in the viewing area of the underlay substrate being formed with described insulating barrier;
Metal level is formed in the viewing area of the underlay substrate being formed with described transparent conductive film layer;
On described transparent conductive film layer and described metal level, the first pattern is formed by patterning processes, the orthographic projection of described first pattern on described underlay substrate is identical with the shape of the orthographic projection of metal electrode on described underlay substrate, and described metal electrode comprises source electrode, drain electrode and pixel electrode;
On the metal level forming described first pattern, formed the pattern comprising described drain electrode by patterning processes.
Optionally, the viewing area being formed with the underlay substrate of described insulating barrier is formed with electrostatic screen layer, and the electrostatic screen layer of described viewing area and the electrostatic screen layer of described outer peripheral areas are the transparent conductive film layers simultaneously formed,
The outer peripheral areas of the described underlay substrate being formed with described electrostatic screen layer forms outer peripheral areas metal level, comprising:
The underlay substrate being formed with described transparent conductive film layer forms metal level;
Described on described outer peripheral areas metal level and described electrostatic screen layer, form peripheral pattern by patterning processes, comprising:
On described metal level and described transparent conductive film layer, the second pattern is formed by patterning processes, the orthographic projection of described second pattern on described underlay substrate is identical with the shape of the orthographic projection of default metal pattern on described underlay substrate, and described default metal pattern comprises the metal pattern of source electrode, drain electrode, pixel electrode and described outer peripheral areas;
On the metal level forming described second pattern, formed the pattern comprising described drain electrode by patterning processes.
Optionally, the viewing area being formed with the underlay substrate of described insulating barrier is formed with pixel electrode,
Described electrostatic screen layer and described pixel electrode are formed in a patterning processes.
According to a second aspect of the invention, provide a kind of array base palte, described array base palte comprises:
Underlay substrate;
Described underlay substrate is provided with the first metal pattern;
The underlay substrate of described first metal pattern is provided with insulating barrier;
The outer peripheral areas of the underlay substrate of described insulating barrier is disposed with electrostatic screen layer and outer peripheral areas metal level, and the pattern of described outer peripheral areas metal level is identical with the pattern of described electrostatic screen layer.
Optionally, the underlay substrate of described insulating barrier is provided with the pattern comprising semiconductor layer;
The viewing area of the underlay substrate of described semiconductor layer is provided with the shape transparent conductive film layer identical with the first pattern, the orthographic projection of described first pattern on described underlay substrate is identical with the shape of the orthographic projection of metal electrode on described underlay substrate, and described metal electrode comprises source electrode, drain electrode and pixel electrode;
The described viewing area of the underlay substrate of the transparent conductive film layer that described shape is identical with the first pattern is provided with described source electrode and described drain electrode.
Optionally, described underlay substrate is provided with the transparent conductive film layer that shape is identical with the second pattern, the orthographic projection of described second pattern on described underlay substrate is identical with the shape of the orthographic projection of default metal pattern on described underlay substrate, and described default metal pattern comprises source electrode, drain electrode, pixel electrode and described outer peripheral areas metal level;
The underlay substrate of the transparent conductive film layer that described shape is identical with the second pattern is provided with described source electrode, described drain electrode and described outer peripheral areas metal level.
Optionally, described electrostatic screen layer is transparent conductive film layer.
According to a third aspect of the invention we, provide a kind of display unit, described display unit comprises the array base palte that second aspect provides.
The technical scheme that the embodiment of the present invention provides can comprise following beneficial effect:
By first forming electrostatic screen layer in outer peripheral areas, metal level is formed afterwards on the electrostatic screen layer of outer peripheral areas, the circuit that the metal level solving outer peripheral areas in correlation technique may produce ESD with the first metal pattern when being formed and destroy on array base palte, the problem that product yield is lower; Reach and avoid the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD, improve product yield.
Should be understood that, it is only exemplary and explanatory that above general description and details hereinafter describe, and can not limit the present invention.
Accompanying drawing explanation
Accompanying drawing to be herein merged in specification and to form the part of this specification, shows embodiment according to the invention, and is used from specification one and explains principle of the present invention.
Fig. 1 is the flow chart of the manufacture method of a kind of array base palte that the invention process exemplifies;
Fig. 2-1 is the flow chart of the manufacture method of the another kind of array base palte that the invention process exemplifies;
Fig. 2-2 to Fig. 2-8 is structural representations of underlay substrate in Fig. 2-1 illustrated embodiment;
Fig. 3-1 is the flow chart of the manufacture method of the another kind of array base palte that the invention process exemplifies;
Fig. 3-2 to Fig. 3-4 is structural representations of underlay substrate in Fig. 3-1 illustrated embodiment;
Fig. 4-1 is the structural representation of a kind of array base palte that the invention process exemplifies;
Fig. 4-2 is the structural representations of the another kind of array base palte that the invention process exemplifies.
By above-mentioned accompanying drawing, illustrate the embodiment that the present invention is clear and definite more detailed description will be had hereinafter.These accompanying drawings and text description be not in order to limited by any mode the present invention design scope, but by reference to specific embodiment for those skilled in the art illustrate concept of the present invention.
Embodiment
Here will be described exemplary embodiment in detail, its sample table shows in the accompanying drawings.When description below relates to accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawing represents same or analogous key element.Execution mode described in following exemplary embodiment does not represent all execution modes consistent with the present invention.On the contrary, they only with as in appended claims describe in detail, the example of apparatus and method that aspects more of the present invention are consistent.
Fig. 1 is the flow chart of the manufacture method of a kind of array base palte that the invention process exemplifies, and the present embodiment is applied to manufacturing array substrate to illustrate with the manufacture method of this array base palte.The manufacture method of this array base palte can comprise following several step:
In a step 101, underlay substrate forms the first metal pattern.
In a step 102, the underlay substrate being formed with the first metal pattern forms insulating barrier.
In step 103, electrostatic screen layer is formed in the outer peripheral areas of the underlay substrate being formed with insulating barrier.
At step 104, outer peripheral areas metal level is formed in the outer peripheral areas of the underlay substrate being formed with electrostatic screen layer.
In step 105, on outer peripheral areas metal level and electrostatic screen layer, form peripheral pattern by patterning processes, the shape of peripheral pattern is identical with the shape of the metal pattern of outer peripheral areas.
In sum, the manufacture method of the array base palte that the embodiment of the present invention provides, by first forming electrostatic screen layer in outer peripheral areas, metal level is formed afterwards on the electrostatic screen layer of outer peripheral areas, the circuit that the metal level solving outer peripheral areas in correlation technique may produce ESD with the first metal pattern when being formed and destroy on array base palte, the problem that product yield is lower; Reach and avoid the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD, improve product yield.
Fig. 2-1 is the flow chart of the manufacture method of the another kind of array base palte that the invention process exemplifies, and the present embodiment is applied to manufacturing array substrate to illustrate with the manufacture method of this array base palte.The manufacture method of this array base palte can comprise following several step:
In step 201, underlay substrate forms the first metal pattern.
When the manufacture method of the array base palte using the embodiment of the present invention to provide, first can form the first metal pattern on underlay substrate, this first metal pattern can comprise the grid of viewing area and the holding wire of outer peripheral areas.At the end of this step, the structure of underlay substrate can as shown in Fig. 2-2, and grid 121 and holding wire 122 are all formed on underlay substrate 11.Exemplary, can form the first metal layer on underlay substrate, form the first metal pattern on the first metal layer afterwards by patterning processes, this process can with reference to correlation technique, and the embodiment of the present invention repeats no more.
In step 202., the underlay substrate being formed with the first metal pattern forms insulating barrier.
After underlay substrate is formed the first metal pattern, insulating barrier can be formed on the underlay substrate being formed with the first metal pattern.At the end of this step, the structure of underlay substrate can as Figure 2-3, insulating barrier 13 be formed at be formed with the first metal pattern 12 underlay substrate 11 on.
In step 203, the underlay substrate being formed with insulating barrier is formed the pattern comprising semiconductor layer.
After the underlay substrate being formed with the first metal pattern forms insulating barrier, the pattern comprising semiconductor layer can be formed on the underlay substrate being formed with insulating barrier.Wherein the pattern of semiconductor layer can comprise the semiconductor layer of viewing area (as TFT regions) and the semiconductor layer of outer peripheral areas.At the end of this step, the structure of underlay substrate can be as in Figure 2-4, wherein the semiconductor layer 141 of viewing area A and the semiconductor layer 142 of outer peripheral areas B are all formed on insulating barrier 13, it should be noted that, at the end of this step, the structure of underlay substrate can also as shown in Figure 2-5, and wherein on insulating barrier 13, only viewing area A is formed with semiconductor layer 141, and outer peripheral areas B is not formed with semiconductor layer.
In step 204, the underlay substrate being formed with semiconductor layer forms transparent conductive film layer.
The underlay substrate being formed with insulating barrier is formed after comprising the pattern of semiconductor layer, transparent conductive film layer can be formed on the underlay substrate being formed with semiconductor layer, this transparent conductive film layer can be made up of ITO (Indiumtinoxide, tin indium oxide) or other transparent conductive material.This transparent conductive film layer can comprise the transparent conductive film layer of viewing area and the transparent conductive film layer of outer peripheral areas, and namely this step defines transparent conductive film layer in the viewing area of the underlay substrate being formed with insulating barrier.
It should be noted that, after this step terminates, also directly can be formed the pattern of the electrostatic screen layer comprising pixel electrode and outer peripheral areas on transparent conductive film layer by patterning processes, the embodiment of the present invention does not restrict.
In step 205, the underlay substrate being formed with transparent conductive film layer forms metal level.
After the underlay substrate being formed with semiconductor layer forms transparent conductive film layer, can form metal level on the underlay substrate being formed with transparent conductive film layer, this metal level is for the formation of the second metal pattern.At the end of this step, the structure of underlay substrate can as shown in figures 2-6, and wherein transparent conductive film layer 15 is formed at and is formed on the underlay substrate 11 of semiconductor layer 14, and metal level 16 is formed on transparent conductive film layer 15.Exemplary, metal level can be formed by electroplating technology on the underlay substrate being formed with transparent conductive film layer.It should be noted that, when the metal level 16 being positioned at outer peripheral areas B is formed, transparent conductive film layer 15 is formed due to metal level 16 with between first metal pattern 122 of outer peripheral areas B, issuable electrostatic charge can be dispersed on whole transparent conductive film layer 15 by average mark, avoid and produce ESD and destroy the problem of the circuit on array base palte.
In step 206, on metal level and transparent conductive film layer, form the second pattern by patterning processes.
After underlay substrate defines transparent conductive film layer and metal level successively, can on metal level on whole underlay substrate (comprising viewing area and outer peripheral areas) and transparent conductive film layer, the second pattern is formed by patterning processes, this the second pattern orthographic projection on underlay substrate is identical with the shape of the orthographic projection of default metal pattern on underlay substrate, and default metal pattern comprises the metal pattern of source electrode, drain electrode, pixel electrode and outer peripheral areas.This step defines the metal pattern of outer peripheral areas on the metal level of outer peripheral areas, and the shape of the transparent conductive film layer of outer peripheral areas is identical with the metal pattern of this outer peripheral areas.
At the end of this step, the structure of underlay substrate can as illustrated in figs. 2-7, and wherein transparent conductive film layer 15 and metal level 16 are all formed with the second pattern, namely now transparent conductive film layer 15 is identical with the shape of metal level 16.
It should be noted that, by patterning processes when etching metal level and transparent conductive film layer, need to use different etching liquids, this process can with reference to correlation technique, and the embodiment of the present invention repeats no more.
In step 207, on the metal level of formation second pattern, formed the pattern comprising drain electrode by patterning processes.
On the metal level of formation second pattern, formed the pattern comprising drain electrode by patterning processes.At the end of this step, the structure of underlay substrate can be as illustrated in figs. 2 through 8, wherein the viewing area A of underlay substrate 11 is formed with source S, drain D and pixel electrode 17, and outer peripheral areas B being formed with the metal pattern 18 of outer peripheral areas, the metal pattern 18 of outer peripheral areas forms the second metal pattern with source S and drain D.
So just transparent conductive film layer is made into pixel electrode, the basis of number of times not increasing patterning processes defines necessary circuit and electrostatic screen layer on underlay substrate, namely the manufacture method of array base palte that provides of the embodiment of the present invention is on the basis adding electrostatic screen layer, do not increase the number of times of patterning processes, the manufacturing cost of the array base palte manufactured by the manufacture method of the array base palte that the embodiment of the present invention is provided there is no larger change compared to the array base palte in correlation technique, but can solve the problem that in correlation technique, product yield is lower.
In addition, at the end of this step, the second metal pattern on underlay substrate is formed, and can form insulating barrier and second layer ITO layer afterwards on the underlay substrate being formed with the second metal pattern, specifically can with reference to correlation technique, and the embodiment of the present invention repeats no more.
It should be added that, the manufacture method of the array base palte that the embodiment of the present invention provides, by transparent conductive film layer is made into pixel electrode, reaching when not increasing patterning processes number of times, avoiding the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD.
In sum, the manufacture method of the array base palte that the embodiment of the present invention provides, by first forming electrostatic screen layer in outer peripheral areas, metal level is formed afterwards on the electrostatic screen layer of outer peripheral areas, the circuit that the metal level solving outer peripheral areas in correlation technique may produce ESD with the first metal pattern when being formed and destroy on array base palte, the problem that product yield is lower; Reach and avoid the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD, improve product yield.
Fig. 3-1 is the flow chart of the manufacture method of the another kind of array base palte that the invention process exemplifies, and the present embodiment is applied to manufacturing array substrate to illustrate with the manufacture method of this array base palte.The manufacture method of this array base palte can comprise following several step:
In step 301, underlay substrate forms the first metal pattern.
When the manufacture method of the array base palte using the embodiment of the present invention to provide, first can form the first metal pattern on underlay substrate, this first metal pattern can comprise the grid of viewing area and the holding wire of outer peripheral areas.At the end of this step, the structure of underlay substrate can as shown in Fig. 2-2.
In step 302, the underlay substrate being formed with the first metal pattern forms insulating barrier.
After underlay substrate is formed the first metal pattern, insulating barrier can be formed on the underlay substrate being formed with the first metal pattern.At the end of this step, the structure of underlay substrate can be as Figure 2-3.
In step 303, the underlay substrate being formed with insulating barrier forms semiconductor layer.
After the underlay substrate being formed with the first metal pattern forms insulating barrier, the pattern comprising semiconductor layer can be formed on the underlay substrate being formed with insulating barrier.Wherein the pattern of semiconductor layer can comprise the semiconductor layer of viewing area (as TFT regions) and the semiconductor layer of outer peripheral areas.At the end of this step, the structure of underlay substrate can be as in Figure 2-4.It should be noted that, at the end of this step, the structure of underlay substrate can also as shown in Figure 2-5, and wherein on insulating barrier 13, only viewing area A is formed with semiconductor layer 142, and outer peripheral areas B is not formed with semiconductor layer.
In step 304, electrostatic screen layer is formed in the outer peripheral areas of the underlay substrate being formed with semiconductor layer.
Electrostatic screen layer is formed in the outer peripheral areas of the underlay substrate being formed with insulating barrier, exemplary, first can form electrostatic screen layer on whole underlay substrate, be etched away the electrostatic screen layer of viewing area afterwards by patterning processes, leave the electrostatic screen layer of outer peripheral areas.At the end of this step, the structure of underlay substrate can as shown in figure 3-2, and the outer peripheral areas B being formed with the underlay substrate 11 of semiconductor layer 14 is formed with electrostatic screen layer 151.
It should be noted that, at the end of this step, be not formed with the region of semiconductor layer in outer peripheral areas, the structure of underlay substrate can as shown in Fig. 3-3, and the insulating barrier 13 of the wherein outer peripheral areas B of underlay substrate 11 is formed with electrostatic screen layer 151.Namely on the underlay substrate being formed with insulating barrier, electrostatic screen layer is defined.
In step 305, metal level is formed in the outer peripheral areas being formed with electrostatic screen layer.
After the outer peripheral areas of underlay substrate forms electrostatic screen layer, can form metal level in the outer peripheral areas being formed with electrostatic screen layer, this metal level is for the formation of the metal pattern of outer peripheral areas.Exemplary, metal level can be formed by electroplating technology in outer peripheral areas.It should be noted that, when the metal level of outer peripheral areas is formed, owing to being formed with electrostatic screen layer between metal level and the first metal pattern of outer peripheral areas, issuable electrostatic charge can be dispersed on whole electrostatic screen layer by average mark, avoid and produce ESD and the circuit that destroys on array base palte.At the end of this step, the structure of underlay substrate can as shown in Figure 3-4, and at the outer peripheral areas B of underlay substrate 11, metal level 16 is formed on electrostatic screen layer 151.What Fig. 3-4 illustrated is the region not being formed with semiconductor layer in outer peripheral areas B.
Within step 306, on the electrostatic screen layer and metal level of outer peripheral areas, form peripheral pattern by patterning processes, the shape of peripheral pattern is identical with the shape of the metal pattern of outer peripheral areas, the metal pattern of outer peripheral areas and source electrode and formation second metal pattern that drains.
After outer peripheral areas is formed with metal level, can on the electrostatic screen layer of outer peripheral areas and metal level, peripheral pattern is formed by patterning processes, the shape of peripheral pattern is identical with the shape of the metal pattern of outer peripheral areas, the metal pattern of outer peripheral areas and source electrode and formation second metal pattern that drains.Namely on the metal level of outer peripheral areas, defined the metal pattern of outer peripheral areas by patterning processes, and the shape of electrostatic screen layer is identical with the metal pattern of this outer peripheral areas.
After this step terminates, can form the circuit such as source drain and pixel electrode with reference to correlation technique in the viewing area of underlay substrate, the embodiment of the present invention repeats no more, and namely following step is optional step.
In step 307, transparent conductive film layer is formed in the viewing area of the underlay substrate being formed with semiconductor layer.
After outer peripheral areas forms peripheral pattern, can form transparent conductive film layer in the viewing area on the underlay substrate being formed with semiconductor layer, this transparent conductive film layer can be made up of ITO or other transparent conductive material.
In step 308, metal level is formed in the viewing area of the underlay substrate being formed with transparent conductive film layer.
After the viewing area of the underlay substrate being formed with semiconductor layer forms transparent conductive film layer, metal level can be formed in the viewing area of the underlay substrate being formed with transparent conductive film layer.At the end of this step, the structure of underlay substrate can as shown in figures 2-6, with 2-6 unlike, the outer peripheral areas on underlay substrate is formed with the metal pattern of outer peripheral areas.
In a step 309, on transparent conductive film layer and metal level, form the first pattern by patterning processes.
After the viewing area of underlay substrate defines transparent conductive film layer and metal level successively, can on the transparent conductive film layer of viewing area and metal level, the first pattern is formed by patterning processes, wherein the orthographic projection of the first pattern on underlay substrate is identical with the shape of the orthographic projection of metal electrode on underlay substrate, and metal electrode can comprise source electrode, drain electrode and pixel electrode.At the end of this step, the structure of underlay substrate can as illustrated in figs. 2-7, and wherein the transparent conductive film layer 15 of viewing area A and metal level 16 are all formed with the first pattern, namely now the transparent conductive film layer 15 of viewing area A is identical with the shape of metal level 16.
It should be noted that, by patterning processes when etching viewing area metal level and transparent conductive film layer, need to use different etching liquids, this process can with reference to correlation technique, and the embodiment of the present invention repeats no more.
In the step 310, on the metal level of formation first pattern, formed the pattern comprising drain electrode by patterning processes.
After the transparent conductive film layer and metal level of viewing area define the first pattern, on the metal level of formation first pattern, the pattern comprising drain electrode can be formed by patterning processes.At the end of this step, the structure of underlay substrate can be as illustrated in figs. 2 through 8.So just transparent conductive film layer is made into pixel electrode, the basis of number of times not increasing patterning processes has defined necessary circuit and electrostatic screen layer on underlay substrate.
It should be noted that, in the embodiment of the present invention, step 307 can also with reference to correlation technique to the manufacture method of the structure of 310 viewing areas provided, and namely do not form transparent conductive film layer in viewing area, the embodiment of the present invention repeats no more.
It should be added that, the manufacture method of the array base palte that the embodiment of the present invention provides, by being formed before metal level in viewing area, first forming transparent conductive film layer, reaching and avoiding the metal level of viewing area may produce the effect of ESD with the first metal pattern when being formed.
In sum, the manufacture method of the array base palte that the embodiment of the present invention provides, by first forming electrostatic screen layer in outer peripheral areas, metal level is formed afterwards on the electrostatic screen layer of outer peripheral areas, the circuit that the metal level solving outer peripheral areas in correlation technique may produce ESD with the first metal pattern when being formed and destroy on array base palte, the problem that product yield is lower; Reach and avoid the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD, improve product yield.
Following is apparatus of the present invention embodiment, may be used for performing the inventive method embodiment.For the details do not disclosed in apparatus of the present invention embodiment, please refer to the inventive method embodiment.
Fig. 4-1 is the structural representation of a kind of array base palte that the invention process exemplifies.This array base palte can comprise:
Underlay substrate 11; Underlay substrate 11 is provided with the first metal pattern 12.
The underlay substrate 11 of the first metal pattern 12 is provided with insulating barrier 13.
The outer peripheral areas B of the underlay substrate 11 of insulating barrier 13 is disposed with electrostatic screen layer 151 and outer peripheral areas metal level 161, and the pattern of outer peripheral areas metal level 161 is identical with the pattern of electrostatic screen layer 151.
In sum, the array base palte that the embodiment of the present invention provides, by first forming electrostatic screen layer in outer peripheral areas, metal level is formed afterwards on the electrostatic screen layer of outer peripheral areas, the circuit that the metal level solving outer peripheral areas in correlation technique may produce ESD with the first metal pattern when being formed and destroy on array base palte, the problem that product yield is lower; Reach and avoid the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD, improve product yield.
Further, please refer to Fig. 4-2, it illustrates the structural representation of the another kind of array base palte that the embodiment of the present invention provides, this array base palte adds preferred parts on the basis of the array base palte shown in Fig. 4-1, thus the array base palte that the embodiment of the present invention is provided has better performance.
Optionally, the underlay substrate 11 of insulating barrier 13 is provided with the pattern comprising semiconductor layer 14.
The viewing area A of the underlay substrate 11 of semiconductor layer 14 is provided with the shape transparent conductive film layer identical with the first pattern 153, the orthographic projection of the first pattern on underlay substrate 11 is identical with the shape of the orthographic projection of metal electrode on underlay substrate 11, and metal electrode comprises source S, drain D and pixel electrode 17.
Include pixel electrode 17 in the transparent conductive film layer 153 that shape is identical with the first pattern, the electrostatic screen layer of outer peripheral areas B is also transparent conductive film layer.
The viewing area A of the underlay substrate 11 of the transparent conductive film layer 153 that shape is identical with the first pattern is provided with source S and drain D.
The transparent conductive film layer 153 that shape is identical with the first pattern and source S and drain D are after the viewing area A of the underlay substrate 11 being formed with insulating barrier 13 forms transparent conductive film layer and metal level successively, the transparent conductive film layer and metal level of viewing area A form the first pattern by patterning processes, and on the metal level being formed with the first pattern, formed after comprising the pattern of drain electrode by patterning processes formation.
Optionally, the underlay substrate 11 of insulating barrier 13 is provided with the pattern comprising semiconductor layer 14.
The underlay substrate 11 of semiconductor layer 14 is provided with the shape transparent conductive film layer identical with the second pattern 152 (comprising the transparent conductive film layer of viewing area A and the transparent conductive film layer of outer peripheral areas B), the orthographic projection of the second pattern on underlay substrate 11 is identical with the shape of the orthographic projection of default metal pattern on underlay substrate 11, and default metal pattern comprises source S, drain D, pixel electrode 17 and outer peripheral areas metal level 161.
The transparent conductive film layer 152 that shape is identical with the second pattern comprises the electrostatic screen layer in outer peripheral areas B and the pixel electrode 17 in the A of viewing area, and namely pixel electrode and electrostatic screen layer are formed in a patterning processes.
The underlay substrate 11 of the transparent conductive film layer 152 that shape is identical with the second pattern is provided with the metal pattern 161 of source S, drain D and outer peripheral areas.
The metal pattern 161 of the transparent conductive film layer 152 that shape is identical with the second pattern and source S, drain D and outer peripheral areas is form metal level and transparent conductive film layer successively on the underlay substrate 11 being formed with insulating barrier after, metal level and transparent conductive film layer form the second pattern by patterning processes, and formed after the pattern of drain electrode is comprised by patterning processes formation to the metal level being formed with the second pattern.
It should be added that, the array base palte that the embodiment of the present invention provides, by transparent conductive film layer is made into pixel electrode, reaching when not increasing patterning processes number of times, avoiding the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD.
It should be added that, the array base palte that the embodiment of the present invention provides, by being formed before metal level in viewing area, first forming transparent conductive film layer, reaching and avoiding the metal level of viewing area may produce the effect of ESD with the first metal pattern when being formed.
In sum, the array base palte that the embodiment of the present invention provides, by first forming electrostatic screen layer in outer peripheral areas, metal level is formed afterwards on the electrostatic screen layer of outer peripheral areas, the circuit that the metal level solving outer peripheral areas in correlation technique may produce ESD with the first metal pattern when being formed and destroy on array base palte, the problem that product yield is lower; Reach and avoid the metal level of outer peripheral areas when being formed and the first metal pattern produces the effect of ESD, improve product yield.
In addition, the embodiment of the present invention also provides a kind of display unit, and this display unit can comprise the array base palte shown in the array base palte shown in Fig. 4-1 or Fig. 4-2.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1. a manufacture method for array base palte, is characterized in that, described method comprises:
Underlay substrate is formed the first metal pattern;
The underlay substrate being formed with described first metal pattern forms insulating barrier;
Electrostatic screen layer is formed in the outer peripheral areas of the underlay substrate being formed with described insulating barrier;
Outer peripheral areas metal level is formed in the outer peripheral areas of the underlay substrate being formed with described electrostatic screen layer;
On described outer peripheral areas metal level and described electrostatic screen layer, form peripheral pattern by patterning processes, the shape of described peripheral pattern is identical with the shape of the metal pattern of described outer peripheral areas.
2. method according to claim 1, is characterized in that, after the described underlay substrate being formed with described first metal pattern forms insulating barrier, described method also comprises:
The underlay substrate being formed with described insulating barrier is formed the pattern comprising semiconductor layer;
Transparent conductive film layer is formed in the viewing area of the underlay substrate being formed with described semiconductor layer;
Metal level is formed in the viewing area of the underlay substrate being formed with described transparent conductive film layer;
On described transparent conductive film layer and described metal level, the first pattern is formed by patterning processes, the orthographic projection of described first pattern on described underlay substrate is identical with the shape of the orthographic projection of metal electrode on described underlay substrate, and described metal electrode comprises source electrode, drain electrode and pixel electrode;
On the metal level forming described first pattern, formed the pattern comprising described drain electrode by patterning processes.
3. method according to claim 1, it is characterized in that, the viewing area being formed with the underlay substrate of described insulating barrier is formed with electrostatic screen layer, and the electrostatic screen layer of described viewing area and the electrostatic screen layer of described outer peripheral areas are the transparent conductive film layers simultaneously formed
The outer peripheral areas of the described underlay substrate being formed with described electrostatic screen layer forms outer peripheral areas metal level, comprising:
The underlay substrate being formed with described transparent conductive film layer forms metal level;
Described on described outer peripheral areas metal level and described electrostatic screen layer, form peripheral pattern by patterning processes, comprising:
On described metal level and described transparent conductive film layer, the second pattern is formed by patterning processes, the orthographic projection of described second pattern on described underlay substrate is identical with the shape of the orthographic projection of default metal pattern on described underlay substrate, and described default metal pattern comprises the metal pattern of source electrode, drain electrode, pixel electrode and described outer peripheral areas;
On the metal level forming described second pattern, formed the pattern comprising described drain electrode by patterning processes.
4. method according to claim 1, is characterized in that, the viewing area being formed with the underlay substrate of described insulating barrier is formed with pixel electrode,
Described electrostatic screen layer and described pixel electrode are formed in a patterning processes.
5. an array base palte, is characterized in that, described array base palte comprises:
Underlay substrate;
Described underlay substrate is provided with the first metal pattern;
The underlay substrate of described first metal pattern is provided with insulating barrier;
The outer peripheral areas of the underlay substrate of described insulating barrier is disposed with electrostatic screen layer and outer peripheral areas metal level, and the pattern of described outer peripheral areas metal level is identical with the pattern of described electrostatic screen layer.
6. array base palte according to claim 5, is characterized in that,
The underlay substrate of described insulating barrier is provided with the pattern comprising semiconductor layer;
The viewing area of the underlay substrate of described semiconductor layer is provided with the shape transparent conductive film layer identical with the first pattern, the orthographic projection of described first pattern on described underlay substrate is identical with the shape of the orthographic projection of metal electrode on described underlay substrate, and described metal electrode comprises source electrode, drain electrode and pixel electrode;
The described viewing area of the underlay substrate of the transparent conductive film layer that described shape is identical with the first pattern is provided with described source electrode and described drain electrode.
7. array base palte according to claim 5, is characterized in that,
Described underlay substrate is provided with the transparent conductive film layer that shape is identical with the second pattern, the orthographic projection of described second pattern on described underlay substrate is identical with the shape of the orthographic projection of default metal pattern on described underlay substrate, and described default metal pattern comprises source electrode, drain electrode, pixel electrode and described outer peripheral areas metal level;
The underlay substrate of the transparent conductive film layer that described shape is identical with the second pattern is provided with described source electrode, described drain electrode and described outer peripheral areas metal level.
8. array base palte according to claim 5, is characterized in that,
Described electrostatic screen layer is transparent conductive film layer.
9. a display unit, is characterized in that, described display unit comprises the arbitrary described array base palte of claim 5 to 8.
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