CN105261681B - 一种半导体元件及其制备方法 - Google Patents
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Abstract
本发明提出了一种半导体元件,包括具有AlxN1‑x层和AlyO1‑y层(0<x<1,0<y<1)的超晶格结构缓冲层,所述超晶格结构缓冲层在芯片制程的侧壁腐蚀过程中,可减小化学溶液的腐蚀程度,提高芯片良率。同时提出一种制备方法,制备该超晶格结构缓冲层,实现本发明效果。
Description
技术领域
本发明属于半导体技术领域,特别涉及一种半导体元件及其制备方法。
背景技术
半导体元件的切割技术由金刚石刀切割逐渐发展为普通激光切割,一般来说,激光的波长为355nm或者266nm,其特点在于它既能划开蓝宝石衬底,也能划开各种膜层,比如氮化镓层,布拉格反射层、金属层等。而针对切割而言,既可以利用激光对外延片的表面进行划裂形成表面切割道,也可以利用激光聚焦衬底内部形成隐形切割道,从而达到分离单个芯粒的目的。
当使用激光对外延片的表面进行划裂形成表面切割道时,激光烧灼后形成的杂质附着于切割道侧壁,阻挡了光的出射,影响半导体元件的外量子效率。故为避免该烧灼杂质对发光亮度的影响,通常是在激光形成切割道后再使用化学溶液浸泡腐蚀以去除激光烧灼杂质,清洁切割道的侧壁。
物理气相沉积法(PVD法)具有工艺过程简单、对环境污染小、原材消耗少、成膜均匀致密、与基板的结合力强等特点,目前被越来越多地应用于半导体元件的制备中,通常较多地用于外延片底层的制备,例如沉积氮化铝层作为缓冲层,可降低及缓冲衬底与外延层之间因晶格失配和热失配产生的缺陷和应力,改善半导体元件的器件质量。
然而由于PVD法形成的氮化铝层具有多晶格及各向异性等特性,其较易被化学溶液腐蚀,故当外延片包含PVD法形成的缓冲层时,再利用激光对外延片表面切割后浸泡化学溶液时容易产生缓冲层或缓冲层与衬底接触表面的过腐蚀现象,导致形成的芯粒电性异常,降低生产良率。
发明内容
针对上述问题,本发明提出了一种半导体元件,包括至少具有AlxN1-x层和AlyO1-y层,0<x<1,0<y<1,的超晶格结构缓冲层,所述超晶格结构缓冲层在芯片制程的侧壁腐蚀过程中,用于减小化学溶液的腐蚀程度,提高芯片良率。同时提出一种制备方法,制备获得该超晶格结构缓冲层,实现本发明效果。
本发明提供的技术方案为:一种半导体元件,包括:衬底、缓冲层、N型半导体层、发光层和P型半导体层,其中,所述缓冲层为包括AlxN1-x层和AlyO1-y层,0<x<1,0<y<1,循环层叠的超晶格结构层,所述超晶格结构层的第一个循环层叠层中AlxN1-x层置于AlyO1-y层与所述衬底之间;所述缓冲层在芯片制程的侧壁腐蚀过程中,用于减小化学溶液的腐蚀程度,提高芯片良率。
优选的,所述缓冲层中第一个循环层叠层中AlxN1-x层置于AlyO1-y层与所述衬底之间。
优选的,所述 AlxN1-x层厚度≥AlyO1-y层厚度。
优选的,所述 AlxN1-x层厚度为5~500埃。
优选的,所述 AlyO1-y层厚度为5~500埃。
优选的,所述缓冲层与N型半导体层之间还包括一非掺杂半导体层。
优选的,所述超晶格结构层的循环次数≥2。
相较于常规氮化铝单层结构,本发明提出的超晶格结构缓冲层,相当于将常规氮化铝单层缓冲层分割成多层薄膜结构,并在多层膜中***AlyO1-y层,实验结果发现,AlxN1-x层和AlyO1-y层的接触面较AlxN1-x层本体对化学溶液的腐蚀耐受性更强,因此本结构的超晶格结构增加了AlxN1-x层和AlyO1-y层的接触面,从而提升缓冲层的抗化学溶液腐蚀的特性;且由于AlyO1-y层的存在,使得缓冲层的晶格应力发生改变,最终形成的超晶格缓冲层较原氮化铝缓冲层的晶体质量得到提高,从而在后续芯片制程的侧壁腐蚀过程中,即使用化学溶液腐蚀处理去除芯粒侧壁附着物时,降低对缓冲层的腐蚀程度,减小对芯粒电性能的影响。同时,由于多层膜对于光的折射角度的改变,此超晶格结构层可增加光的取出效率,提升半导体元件的外量子效率。
同时,为制备上述半导体底层结构,本发明提供一种半导体元件的制备方法,所述方法包括步骤:
S1、提供一衬底;
S2、利用物理气相沉积法于所述衬底表面沉积AlxN1-x层和AlyO1-y层,0<x<1,0<y<1,组成的超晶格结构缓冲层,所述缓冲层在后续芯片制程时减小化学溶液的腐蚀程度,提高芯片良率;
S3、利用化学气相沉积法于所述缓冲层表面沉积N型半导体层、发光层和P型半导体层组成的外延层,其中,低温制备的缓冲层在后续高温外延层制备过程中实现退火再结晶,用于释放在后沉积制程中的应力。
其中,所述步骤S2具体为:利用物理气相沉积法先于衬底表面沉积AlxN1-x层,再于所述AlxN1-x层表面沉积AlyO1-y层,并依次循环层叠形成超晶格结构缓冲层。
因为常规化学气相沉积法(MOCVD)无法在沉积过程中掺入氧元素,故本方法利用PVD法沉积形成超晶格结构缓冲层,引入AlyO1-y层,利用其抗腐蚀特性,及与AlxN1-x层晶格特性差异,改善本发明半导体元件中缓冲层特性,释放后续沉积外延层产生的应力,同时使其更利于后续芯片端制程。
优选的,所述步骤S2中,利用物理气相沉积法先于衬底表面沉积AlxN1-x层,再于所述AlxN1-x层表面沉积AlyO1-y层,并依次循环层叠形成超晶格结构缓冲层。
优选的,所述两种方法中步骤S3还包括,于缓冲层表面先沉积一非掺杂半导体层,再沉积N型半导体层。
优选的,所述 AlxN1-x层厚度≥AlyO1-y层厚度。
优选的,所述 AlxN1-x层厚度为5~500埃。
优选的,所述 AlyO1-y层厚度为5~500埃。
优选的,所述超晶格结构层的循环次数≥2。
本发明至少具有以下有益效果:
1、本发明提出的一种半导体元件,其缓冲层为包括AlxN1-x层和AlyO1-y层,0<x<1,0<y<1,的超晶格结构,由于AlxN1-x层与AlyO1-y层界面处,对化学溶液的腐蚀耐受性较强,因此,相对于单层AlxN1-x层,AlxN1-x层和AlyO1-y层的交替排列,使其界面增多,从而整体提高缓冲层的抗腐蚀性,同时AlyO1-y材料层本身具有的抗腐蚀性,进一步增强缓冲层的抗腐蚀性,避免芯片制程侧壁腐蚀时的过腐蚀现象。
2、相较于MOCVD法沉积膜层,PVD在沉积过程中可掺入氧元素,因此本发明利用PVD法沉积包括AlyO1-y层的超晶格结构缓冲层,AlyO1-y层的抗腐蚀性及其与AlxN1-x层的晶格特性差异,改善了缓冲层特性,进而释放后续沉积外延沉积过程产生的应力。
3、利用超晶格多层膜结构对于光的折射角度的影响,改善光的取出效率,进而提升半导体元件的内外量子效率。
附图说明
附图用来提供对本发明的进一步理解,并且构成说明书的一部分,与本发明的实施例一起用于解释本发明,并不构成对本发明的限制。此外,附图数据是描述概要,不是按比例绘制。
图1为本发明实施例一之半导体元件结构示意图。
图2为本发明实施例一之缓冲层结构示意图。
图3为本发明实施例二之半导体元件结构示意图。
图4为本发明实施例三之半导体元件结构示意图。
图中标示:10.衬底;20. 缓冲层;21. AlxN1-x层;22. AlyO1-y层;30. N型半导体层;40.发光层;50.P型半导体层;60. 非掺杂半导体层;a. AlxN1-x层本体;b. AlxN1-x层21与AlyO1-y层22接触界面。
具体实施方式
下面结合附图和实施例对本发明的具体实施方式进行详细说明。
实施例1
参看附图1~2,本发明中的一种半导体元件,包括衬底10,缓冲层20,N性半导体层30、发光层40和P型半导体层50,其中,缓冲层20为至少包含厚度为5~500埃的AlxN1-x层21和厚度为5~500埃的AlyO1-y层22,0<x<1,0<y<1,的超晶格结构层,且超晶格结构层的循环次数≥2,AlxN1-x层21的厚度≥AlyO1-y层22厚度。实验发现,当AlxN1-x层21厚度与AlyO1-y层22厚度比值越大时,缓冲层20的晶格质量越优。本发明结构中,利用包含AlxN1-x层21和AlyO1-y层22的超晶格结构形成缓冲层20,减小后续芯片制程的侧壁腐蚀过程中,化学溶液对侧壁的腐蚀程度,提高芯片良率。
继续参看附图1~2,相对于AlxN1-x层21本体a,AlxN1-x层21与AlyO1-y层22接触界面位置b对化学溶液的腐蚀耐受性更强,因此,相对于常规结构中的单层氮化铝层,AlxN1-x层21和AlyO1-y层22的交替排列使其接触界面b增多,从而整体提高缓冲层20的抗腐蚀性;同时由于AlyO1-y层材料22本身具有的抗腐蚀性,进一步增强缓冲层20的抗腐蚀性,避免芯片制程中侧壁腐蚀时的过腐蚀现象。另外,因AlxN1-x层21和AlyO1-y层22晶格差异较大,故超晶格结构中AlxN1-x层21和AlyO1-y层22接触界面被挤压变形,从而使得缓冲层20整体释放应力的能力增加,缓解后续沉积外延层的晶格应力,改善因应力造成的翘曲。同时,当缓冲层20为多层膜层叠结构时,利用其不同材料层对光的折射率差异,调节缓冲层20对发光层40发射光的折射角度,增大光取出效率,提高半导体元件的外量子效率。
为实现上述结构及其作用,本发明提出一种半导体元件的制备方法:
S1、提供衬底10,所述衬底为蓝宝石、SiC(6H-SiC或4H-SiC)、Si、GaAs 、GaN衬底或晶格常数(lattice constant)接近于氮化物半导体的单晶氧化物,此处优选蓝宝石衬底。
S2、将衬底10置入PVD机台腔室,利用PVD法于衬底10表面沉积至少包括厚度为5~500埃的AlxN1-x层21和厚度为5~500埃的AlyO1-y层22,0<x<1,0<y<1,的超晶格结构缓冲层20,超晶格结构的循环次数≥2,AlxN1-x层21的厚度≥AlyO1-y层22厚度。缓冲层20在后续芯片制程的侧壁腐蚀过程,可减小化学溶液的腐蚀程度,提高芯片良率;而因为常规MOCVD法无法沉积含氧元素的AlyO1-y层22,故本发明利用PVD法引入AlyO1-y层22,实现了本发明的结构特征。
S3、将沉积有缓冲层20的晶片转入MOCVD腔室,利用MOCVD法于缓冲层20表面沉积N型半导体层30、发光层40和P型半导体层50组成的外延层,其中,后续外延层制备过程中的高温环境对低温PVD生长的缓冲层20起到使其退火再结晶的作用,缓冲层的退火过程有利于释放在后沉积制程中的应力,改善半导体元件的晶体质量。
本发明方法利用PVD法与MOCVD法相结合的方式制备半导体元件,首先利用PVD法沉积缓冲层20,获得含氧元素的缓冲层20,在不影响PVD法沉积的氮化铝层形成缓冲层的基础上减小缓冲层20被化学溶液腐蚀的程度,改善化学溶液处理后的元件电学性能。随后,在缓冲层20表面利用MOCVD法沉积N型半导体层30、发光层40和P型半导体层50组成的外延层形成半导体元件。
实施例2
参看附图3,本实施例与实施例1的区别在于,本发明的缓冲层20为包括厚度为5~500埃的AlxN1-x层21和厚度为5~500埃的AlyO1-y层22,0<x<1,0<y<1,的超晶格结构层,且在该超晶格结构层的第一个循环层叠层中AlxN1-x层21置于AlyO1-y层22与所述衬底10之间,所述超晶格结构层的循环次数≥2,AlxN1-x层21的厚度≥AlyO1-y层22厚度。
本实施例采取的制备方法与实施例1的制备方法区别为:S2、将衬底10置入PVD机台腔室,利用PVD法先于衬底10表面沉积厚度为5~500埃的AlxN1-x层21和厚度为5~500埃的AlyO1-y层22,0<x<1,0<y<1,组成的超晶格结构缓冲层20,此步骤中,先于衬底10表面沉积一AlxN1-x层21,再于AlxN1-x层21表面沉积AlyO1-y层22,依次循环层叠形成超晶格结构;超晶格结构的循环次数至少2个。试验结果表明,于衬底10表面既可以先沉积AlxN1-x层21,也可以先沉积AlyO1-y层22,此处优先选用在衬底10表面先沉积AlxN1-x层21。同样,本实施例制备的缓冲层20在后续芯片制程的侧壁腐蚀过程中,可减小化学溶液的腐蚀程度,提高芯片良率。
实施例3
参看附图4,本实施例与实施例1的区别在于,在缓冲层20与N型半导体层30之间沉积非掺杂半导体层60,利用该层进一步改善后续外延层的晶体质量,提升半导体元件的光电性能。
应当理解的是,上述具体实施方案为本发明的优选实施例,本发明的范围不限于该实施例,凡依本发明所做的任何变更,皆属本发明的保护范围之内。
Claims (7)
1.一种半导体元件,包括:衬底、缓冲层、N型半导体层、发光层和P型半导体层,其特征在于:所述缓冲层为包括AlxN1-x层和AlyO1-y层,0<x<1,0<y<1,循环层叠的超晶格结构层,所述超晶格结构层的第一个循环中所述AlyO1-y层置于所述AlxN1-x层之上,所述超晶格结构层在芯片制程的侧壁腐蚀过程中,用于减小化学溶液的腐蚀程度,提高芯片良率。
2.根据权利要求1所述的一种半导体元件,其特征在于:所述超晶格结构层的循环次数≥2。
3.根据权利要求1所述的一种半导体元件,其特征在于:所述 AlxN1-x层厚度≥AlyO1-y层厚度。
4.根据权利要求1所述的一种半导体元件,其特征在于:所述 AlxN1-x层厚度、AlyO1-y层厚度为5~500埃。
5.根据权利要求1所述的一种半导体元件,其特征在于:所述缓冲层与N型半导体之间包括一非掺杂半导体层。
6.一种半导体元件的制备方法,其特征在于,所述方法包括步骤:
S1、提供一衬底;
S2、利用物理气相沉积法于所述衬底表面沉积包括AlxN1-x层和AlyO1-y层,0<x<1,0<y<1,循环层叠的超晶格结构缓冲层,所述缓冲层在后续芯片制程的侧壁腐蚀过程中,用于减小化学溶液的腐蚀程度,提高芯片良率;
S3、利用化学气相沉积法于所述缓冲层表面沉积N型半导体层、发光层和P型半导体层组成的外延层;
其中,所述步骤S2中,利用物理气相沉积法先于衬底表面沉积AlxN1-x层,再于所述AlxN1-x层表面沉积AlyO1-y层,并依次循环层叠形成超晶格结构缓冲层。
7.根据权利要求6所述的一种半导体元件的制备方法,其特征在于:所述步骤S3还包括,于缓冲层表面先沉积一非掺杂半导体层,再沉积N型半导体层。
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