CN105227192B - A kind of method encoded for multi-mode BCH code and the encoder using this method - Google Patents
A kind of method encoded for multi-mode BCH code and the encoder using this method Download PDFInfo
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Abstract
The present invention discloses a kind of method encoded for multi-mode BCH code and the encoder using this method.This method includes step: establishing multiple encoder matrixs；The encoder matrix is combined with side alignment thereof, to form an associate(d) matrix；Common subexpression is found in the associate(d) matrix；And an information is encoded using the associate(d) matrix.
Description
Technical field
The present invention is used for different BCH codes especially with regard to a kind of multi-mode encoding device about a kind of encoder, comprising appointing
Digital m in what code length, code rate or GF (2m).
Background technique
Bose-Chaudhuri-Hocquenghem (BCH) code is the mistake for being commonly used for very much storage with communication equipment
More code, BCH code can be detected and correct due to the noise and defect in storage device channels, the mistake occurred at random.BCH code
Coding is often realized using the combination of linear feedback shift register and certain logical integrated circuits.Existing linear feedback is moved
Bit register circuit is as shown in Figure 1.In order to accelerate operation, which usually adopts parallel calculation mode and designs.Symbol p in Fig. 1
Indicate in j-th of frequency, the R'(j of the input to synchronize calculating) the position p data.After coding, calculating is exported
As a result Z (j).If the code length is n, the program of coding can be completed after [n/p] a frequency.
About Bose-Chaudhuri-Hocquenghem Code, detailed description are as follows.One has n coding BCH code words, has k information, encoded
A generator polynomial is applied in journey:
G (x)=xR+g'R-1xR-1+g'R-2xR-2+…+g'2x2+g'1x1+g'0,
And wherein R=n-k+1.When the encoder for carrying out p parallel computation coding can be synchronized using one, for a tool
There are the initial treatment data of the position n of k information to be cut into R'(1 as unit of p), R'(2) ... R'(n/p) (R'(n/p) be not required to
To be p), and it is input to the encoder in every frequency sequentially to carry out operation.Based on a general formula, in j-th of frequency (1≤j
≤ n/p) in, the calculated value of output are as follows: Z (j)=Fp×[Z(j-1)+R'(j)].It should be noted that all elements are all in Z (0)
0.In order to facilitate operation, following presentation
In, R'(j) be j-th p.Z (j) has R, is respectively expressed as Z0(j)、Z1(j)…ZR-1(j)。
Expression is further described below in other above formulas:
Enable F'=[FPPreceding P column | FP], the transposed matrix of available Z (j):
It is able to satisfy the circuit of the above operation, can also reach encoding operation as shown in Figure 1.The code word of one coding can be in the
It is obtained after [n/p] frequency.
Method above-mentioned can be only used in identical Galois field GF (2m), and code rate is fixed with code length.It answers certain
For, it may be necessary to different code length, code rate, the power m in GF (2m) and parallel parameter p.Traditionally, these demands can lead to
Specific Bose-Chaudhuri-Hocquenghem Code device is crossed to realize.Thus, the complexity of hardware is got higher.In order to reduce hardware complexity, certain designers
Some multiplexers may be added into linear feedback shift register with shared buffer would.However, more because these are added
Task device and the area cost that has more and delay can undermine the value of product itself.
Therefore, it is necessary to one kind for different BCH codes, can share the method for a linear feedback shift register and use the party
The encoder of method.In addition, this method can increase the search space of common subexpression in a matrix, to reduce hardware logic face
Product.
Summary of the invention
As described above, in the design circuit existing scheme of the coding of BCH code, the complexity of hardware is higher and area cost
Greatly.Therefore a kind of for different BCH codes, the method for a linear feedback shift register and the encoder using this method can be shared
Be very there is an urgent need to.
Therefore, according to a kind of aspect of the invention, a method of it is encoded for multi-mode BCH code, comprising the steps of: establish
Multiple encoder matrixs；The encoder matrix is combined with side alignment thereof, to form an associate(d) matrix；It is found in the associate(d) matrix
Common subexpression；And an information is encoded using the associate(d) matrix, wherein each encoder matrix has following form
AndWherein it is with p for the initial treatment data of a position n with k information
Unit cutting, R are defined as R=n-k+1；g'R-1、g'R-2... and g'0For a generator polynomial g (x)=xR+g'R-1xR-1+g'R- 2xR-2+…+g'2x2+g'1x1+g'0Coefficient；Any two encoder matrix has identical or different n and/or k.
Conceive according to this case, in associate(d) matrix, is not supplied to sentence 0 shared by encoder matrix element.Encoder matrix according to
Sequence is arranged in the side of the associate(d) matrix.An at least encoder matrix use another coding in the associate(d) matrix in the associate(d) matrix
The common subexpression of matrix.0 is formed when encoder matrix the smallest in associate(d) matrix can be accommodated in neighbouring other encoder matrixs
A part of place, which is set at this and each neighbouring encoder matrix in two sides.Preferably two
A adjacent encoder matrix is separated with multiple 0.
In addition, according to another aspect of the invention, a kind of encoder for multi-mode BCH code coding includes: a knot
Matrix unit is closed, to provide multiple encoder matrixs, the element in one of encoder matrix is had p defeated with one
Enter data multiplication, and exporting result in a first frequency is a calculating data；One linear feedback shift register, to linear
It is an output data that ground, which shifts the calculating data, and the output data is exported in a second frequency；And an adder, to connect
The output data and the processing data with p cuttings are received, which is added with the processing data of cutting, and in
It is another input data to the associate(d) matrix unit that the addition result is exported in the second frequency, wherein a n with k information
The initial treatment data of position are cut as unit of p, and the processing data as cutting inputs the adder in order；One coding
Code word is obtained in [n/p] a frequency；Second frequency lags behind one frequency of first frequency.
The encoder matrix forms an associate(d) matrix in the associate(d) matrix unit with side alignment thereof, and the associate(d) matrix
Unit is according to corresponding BCH code, using an encoder matrix interior element or an encoder matrix interior element together in another encoder matrix
Common subexpression, carry out multiplying.And wherein each encoder matrix has following form
Wherein the initial treatment data of the position n for this with k information are cut as unit of p, and R is defined as R=n-k
+1；g'R-1、g'R-2... and g'0For a generator polynomial g (x)=xR+g'R-1xR-1+g'R-2xR-2+…+g'2x2+g'1x1+g'0's
Coefficient；Any two encoder matrix has identical or different n and/or k.
Detailed description of the invention
Fig. 1 is the conventional codec for a BCH code；
Fig. 2 is the encoder provided by the present invention for encoding multi-mode BCH code；
Fig. 3 shows the structure for the associate(d) matrix portion in an embodiment；
Fig. 4 shows the structure for the associate(d) matrix portion in another embodiment；
Fig. 5 shows the structure for the associate(d) matrix portion in another embodiment；
Fig. 6 shows the structure for the associate(d) matrix portion in another embodiment；
Fig. 7 is the flow chart of a coding method provided by the invention.
Description of symbols: 10- encoder；100- associate(d) matrix unit；110- associate(d) matrix portion；120- logical operation
Portion；200- linear feedback shift register；300- adder.
Specific embodiment
The present invention will be more specifically described referring to following embodiment.
Please see Fig. 2 to Fig. 4, explanation is used according to one embodiment of the invention.One is used to encode the volume of multi-mode BCH code
Code device 10 includes an associate(d) matrix unit 100, a linear feedback shift register 200 and an adder 300.Each BCH code
Mode can have the power m in different code rates, code length or Galois field GF (2m).By the encoder 10, any quantity mould
The combination of formula can be all able to achieve.
Associate(d) matrix unit 100 is used to provide multiple encoder matrixs, an encoder matrix interior element or one are encoded square
For battle array interior element together with the common subexpression in another encoder matrix, the input data for having p with one carries out multiplying.
It can also be further in a first frequency, and exporting aforementioned result is a calculating data.Encoder matrix is with side alignment thereof
An associate(d) matrix is formed in the associate(d) matrix unit 100.Associate(d) matrix unit 100 carries out multiplication fortune according to corresponding BCH code
It calculates.Associate(d) matrix is stored in an associate(d) matrix portion 110.In order to have more specific understanding to associate(d) matrix portion 110, figure is please referred to
3。
Fig. 3, which is shown, to be used in an embodiment, the structure in associate(d) matrix portion 110.It should be noted that the associate(d) matrix portion 110
It can be any electronic component, such as read-only memory (ROM) array, to remember the element (0 or 1) of the encoder matrix.?
In Fig. 3,3 squares are used to respectively indicate 3 encoder matrixs.Entire area of the associate(d) matrix portion 110 in associate(d) matrix unit 100
It is indicated with R1x (R1+R2+R3).Each sub- area F1 (encoder matrix 1 with side length R1), the F2 (coding with side length R2
Matrix 2) and F3 (with side length R3 encoder matrix 3) be used to encoder matrix is described in the relative position in associate(d) matrix portion 110.Often
The element placement of one encoder matrix is in corresponding sub- area.
It is supplied as shown in figure 3, not being encoded in associate(d) matrix and sentencing 0 shared by matrix element.Comparatively ideal situation is to compile
Code matrix sequential is in the side of the associate(d) matrix, preferably sequential from large to small.Certainly, other sequences, such as by
As low as big or insertion is the smallest between two big persons and feasible mode.In the upper side of associate(d) matrix, encoder matrix R1, R2
It is arranged by left bank to the right side with R3.Have a little it should be noted that another side length of associate(d) matrix should be with maximum encoder matrix R1's
Side length is identical.This is the method for maintaining associate(d) matrix area to minimize and (save area cost) and reduce space waste.
According to the present invention, each encoder matrix can be used to be multiplied with a p input data and then export its result.One
The initial treatment data of the position n with k information are cut as unit of p, and the processing data as cutting inputs in order
The adder.These steps were described in prior art, and details are not described herein again.Thus, each encoder matrix has below
Form
And
R is defined as R=n-k+1；g'R-1、g'R-2... and g'0For a generator polynomial g (x)=xR+g'R-1xR-1+g'R-2xR-2
+…+g'2x2+g'1x1+g'0Coefficient.It can be understood that any two encoder matrix can have identical or different n and/or
k.This means that the code word of the coding from each encoder matrix can have in different code rates, code length or Galois field GF (2m)
Power m.In short, associate(d) matrix can provide the BCH code of different mode according to its design.
Associate(d) matrix unit 100 further has a logical operation section 120, to carry out multiplying.According to of the invention
Spirit, certain common subexpressions in two or more encoder matrixs, can be found and utilize.For example, if F1
There is common subexpression with F2, the calculating of the multiplying of BCH codes different for two can be utilized by logical operation section 120
Common subexpression carries out in F1.Also that is, an at least encoder matrix has used another coding in associate(d) matrix in associate(d) matrix
The common subexpression of matrix.In this way, which multiplexer just can avoid being used in linear feedback shift register 200.This
Sample design, which is advantageous in that, can avoid because being inserted into multiplexer, and cause using additional area with therefore caused by delay.According to
According to the present invention, other encoder matrixs do not have common subexpression, such as F3, also may be present.All encoder matrixs do not need all
With common subexpression.
The common linear feedback shift register as, linear feedback shift register 200 can linearly shift this
Calculating data are an output data, and the output data is exported in a second frequency.Adder 300 receives the output data
(in such as Fig. 2 shown in Z (j)) has p with one, and the processing data of the cutting from initial treatment data are (such as R ' (j) institute in Fig. 2
Show), which is added with the processing data of cutting, and exporting the addition result in the second frequency is another input
Data are to the associate(d) matrix unit.Second frequency falls behind one frequency of first frequency.By adder 300 input data again it is defeated
Enter to associate(d) matrix unit 100 to be used in second frequency to calculate.The code word Z (as shown in Figure 2) of one coding can be in [n/
P] a frequency obtains.
In another embodiment, which can occupy identical space.See Fig. 4.F1 and F2 in Fig. 4 have
There is identical area and occupy the space of same size, but is functionally not identical.According to spirit of the invention, encoder matrix
The encoder matrix of two same sizes is arranged together by arrangement, as shown in F1 and F2.Lesser F3 is placed in by F2.Associate(d) matrix
Rest part filled up with 0.
Certainly, the quantity of encoder matrix is not limited to 3.It can be it is any be greater than or equal to 2 number.In Fig. 5, answer
With 4 encoder matrixs (F1, F2, F3 and F4).The smallest encoder matrix (F4) can be accommodated in neighbour in associate(d) matrix unit 110
Nearly other encoder matrixs (F2 and F3) are formed in a part of 0 place.The smallest encoder matrix (F4) is located at 0 position and two
Each neighbouring two encoder matrixs (F2 and F3) in side.F4 need not be arranged in close to F3, the upper side of associate(d) matrix.
From the perspective of designer, 0 may be added between two adjacent encoder matrixes and recognize each encoder matrix,
It works and can more easily carry out to remove.In this case, two adjacent encoder matrixes will pass through multiple 0 and separate.
See Fig. 6.As described above, the embodiment of Fig. 6 is described between F1 and F2 by arranging F3.Also that is, the smallest encoder matrix formula
It is arranged among two biggish matrixes.This is another arrangement mode for being different from other embodiments again.
From above explanation, a kind of method for multi-mode BCH code coding can be found.Please refer to Fig. 7.This method has
Following steps: multiple encoder matrixs (S01) is established；The encoder matrix is combined with side alignment thereof, to form an associate(d) matrix
(S02)；It is found in the associate(d) matrix common subexpression (S03), and uses associate(d) matrix coding one information (S04).Often
One encoder matrix should have form below:
And
n、k、R、g'R-1、g'R-2... and g'0Definition it is stated that as above.It is not encoder matrix element institute in associate(d) matrix
Sentencing for accounting for 0 is supplied.Encoder matrix sequential is in the side of the associate(d) matrix.At least an encoder matrix makes in the associate(d) matrix
The common subexpression of another encoder matrix in the associate(d) matrix.When encoder matrix the smallest in associate(d) matrix can be accommodated in
Neighbouring other encoder matrixs form a part of 0 place, which is set at this and two sides each neighbouring one
Encoder matrix.Two adjacent encoder matrixes are separated with multiple 0.
Although the present invention has been disclosed by way of example above, it is not intended to limit the present invention., any technical field
Middle tool usually intellectual, without departing from the spirit and scope of the present invention, when can make it is a little change and retouch, therefore the present invention
Protection scope when depending on this case claim define subject to.
Claims (15)
1. a kind of method for multi-mode BCH code coding, which is characterized in that include step:
Establish multiple encoder matrixs；
The encoder matrix is combined with side alignment thereof, to form an associate(d) matrix；
Common subexpression is found in the associate(d) matrix；And
An information is encoded using the associate(d) matrix,
Wherein, each encoder matrix has following form
And
Wherein the initial treatment data of a position n with k information are cut as unit of p, R is defined as R=n-k+1；
g'R-1、g'R-2... and g'0For a generator polynomial g (x)=xR+g'R-1xR-1+g'R-2xR-2+…+g'2x2+g'1x1+g'0Be
Number；Any two encoder matrix has identical or different n and/or k；N is the length of initial treatment data, and k is the length of information
Degree, p are manageable data number in a frequency, and n and p are positive integer and n >=p.
2. the method for multi-mode BCH code coding as described in claim 1, wherein being not coding square in associate(d) matrix
0 is sentenced shared by array element element to supply.
3. the method for multi-mode BCH code coding as described in claim 1, wherein encoder matrix sequential is in the combination
The side of matrix.
4. the method for multi-mode BCH code coding as described in claim 1, wherein at least one in the associate(d) matrix encodes
Matrix uses the common subexpression of another encoder matrix in the associate(d) matrix.
5. the method for multi-mode BCH code coding as described in claim 1, wherein when coding square the smallest in associate(d) matrix
Battle array can be accommodated in neighbouring other encoder matrixs and form a part in place of 0, the smallest encoder matrix be set to be formed 0 it
Each neighbouring encoder matrix in place and two sides.
6. the method for multi-mode BCH code coding as described in claim 1, two of them adjacent encoder matrix is with multiple 0
It separates.
7. it is a kind of for multi-mode BCH code coding encoder, characterized by comprising:
One associate(d) matrix unit, to provide multiple encoder matrixs, the element and one in one of encoder matrix to have
There are p input datas to be multiplied, and exporting result in a first frequency is a calculating data；
One linear feedback shift register is an output data linearly to shift the calculating data, and in a second frequency
Middle output output data；And
One adder, to receive the output data and the processing data with p cuttings, by the output data and cutting
Processing data be added, and exporting in the second frequency addition result is another input data to the associate(d) matrix unit,
Wherein the initial treatment data of the position n with k information are cut as unit of p, as cutting processing data according to
Input to sequence the adder；The code word of one coding is obtained in [n/p] a frequency；Second frequency lags behind one frequency of first frequency
Rate；N is the length of initial treatment data, and k is the length of information, and p is manageable data number in a frequency, and n and p are
Positive integer and n >=p.
8. the encoder for multi-mode BCH code coding as claimed in claim 7, wherein the encoder matrix is with side alignment side
Formula forms an associate(d) matrix in the associate(d) matrix unit, and the associate(d) matrix unit uses a coding according to corresponding BCH code
Matrix interior element or an encoder matrix interior element carry out multiplying together with the common subexpression in another encoder matrix.
9. the encoder for multi-mode BCH code coding as claimed in claim 8, wherein each encoder matrix has following shape
FormulaAnd
Wherein the initial treatment data of the position n for this with k information are cut as unit of p, and R is defined as R=n-k+1；
g'R-1、g'R-2... and g'0For a generator polynomial g (x)=xR+g'R-1xR-1+g'R-2xR-2+…+g'2x2+g'1x1+g'0Be
Number；Any two encoder matrix has identical or different n and/or k.
10. the encoder for multi-mode BCH code coding as claimed in claim 8, wherein the associate(d) matrix unit is further
With a logical operation section, to carry out multiplying.
11. the encoder for multi-mode BCH code coding as claimed in claim 7, wherein being not coding in associate(d) matrix
0 is sentenced shared by matrix element to supply.
12. the encoder for multi-mode BCH code coding as claimed in claim 7, wherein encoder matrix sequential is in this
The side of associate(d) matrix.
13. being used for the encoder of multi-mode BCH code coding as claimed in claim 7, wherein at least one volume in the associate(d) matrix
Code matrix uses the common subexpression of another encoder matrix in the associate(d) matrix.
14. the encoder for multi-mode BCH code coding as claimed in claim 7, wherein when volume the smallest in associate(d) matrix
Code matrix can be accommodated in a part that neighbouring other encoder matrixs form 0 place, which is set to institute's shape
At 0 place and each neighbouring encoder matrix in two sides.
15. the encoder for multi-mode BCH code coding as claimed in claim 7, two of them adjacent encoder matrix is with more
A 0 separates.
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| US20010014960A1 (en) * | 2000-01-31 | 2001-08-16 | Sanyo Electric Co., Ltd., | Error-correcting device and decoder enabling fast error correction with reduced circuit scale |
| CN101567696A (en) * | 2009-05-22 | 2009-10-28 | 北京大学 | Encoder and decoder of Code BCH with changeable parameters |
| CN101976584A (en) * | 2010-10-27 | 2011-02-16 | 记忆科技(深圳)有限公司 | Quasi-cyclic low density parity-check code (QC-LDPC) decoder and decoding method |
| CN102354535A (en) * | 2011-08-04 | 2012-02-15 | 记忆科技(深圳)有限公司 | Logical unit multiplexing system |
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|---|---|---|---|---|
| CN1264032A (en) * | 1999-02-19 | 2000-08-23 | 松下电器产业株式会社 | Data error correcting device |
| US20010014960A1 (en) * | 2000-01-31 | 2001-08-16 | Sanyo Electric Co., Ltd., | Error-correcting device and decoder enabling fast error correction with reduced circuit scale |
| CN101567696A (en) * | 2009-05-22 | 2009-10-28 | 北京大学 | Encoder and decoder of Code BCH with changeable parameters |
| CN101976584A (en) * | 2010-10-27 | 2011-02-16 | 记忆科技(深圳)有限公司 | Quasi-cyclic low density parity-check code (QC-LDPC) decoder and decoding method |
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