CN103401566A - Parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device - Google Patents

Abstract

The invention discloses a parameterization BCH (broadcast channel) error-correcting code parallel encoding method and device. The method comprises the following steps of determining three variable parameters such as the error-correctable bits t, bit width p of the parallel encoding and length k of data information bit, solving a generation polynomial matrix, wherein the number of times of the generation polynomial matrix g(X) is (n-k); carrying out the logic operation for a temporary variable of a check bit and the generation polynomial matrix, and finally outputting a complete encoding module described through a verilog HDL (hardware description language) language. The generated encoding module is high in encoding speed and less in occupied resource. The encoding module utilizes one generation matrix to realize the parallel encoding function and is finally solved through a series of operation according to the generation polynomial of the BCH code. The method and the device are applicable to the application with long code word, high encoding speed and capability for continuously enhancing the error correcting capacity of the error-correcting code.

Description

Parallel encoding method and the device of parameterized Bose-Chaudhuri Hocquenghem error correction codes

Technical field

The present invention relates to circuit and technical field of information processing in electronic information subject, particularly relate to a kind of parallel encoding method and device of parameterized Bose-Chaudhuri Hocquenghem error correction codes.

Background technology

Error-correcting code technique is a kind of method in numerous channel coding technology, and its purpose is exactly in order to make data message waiting for transmission can right-only be transferred to the receiving terminal of information.Make a general survey of the whole development course of error-correcting code technique, along with the develop rapidly of coding theory knowledge and large scale integrated circuit technology, the range of application of error-correcting code technique is also more and more broader, and it has been widely used in digital system at present; For example, digital communication system, the collection of data and the storage of data, and the mobile phone in our daily life, digital camera, digital player, solid state hard disc etc.Bose-Chaudhuri Hocquenghem error correction codes is this a kind of error correction coding relatively commonly used, and therefore to the research of BCH encoding and decoding, not only aspect storage, and practical application in other respects also has larger meaning and value.

Along with the development of technology, people are also more and more higher to the requirement of information rate, and the parallel speed of chip internal also more and more faster, if also still adopt traditional serial BCH encoding and decoding technique, will be a very large reduction to the performance of whole system.For example, the data/address bus of 8 bit wides, transmission rate is 100M, to encode to the data of 512bit, if adopt traditional serial code technology, it will need 5120ns, if adopt parallel coding techniques, only need 640ns, and guarantee that the transmission rate of data does not change.Therefore,, in order to meet the demand of people to information rate and bandwidth, must adopt parallel encoding and decoding current.

Due to the whole process of traditional serial code be with the output step by step of data bit and check digit until form a complete systematic code, complete whole process subsistence level through n clock cycle, wherein n represents the length of whole code word.But, if when the figure place to be encoded in actual system is larger, when perhaps the figure place of error correction is larger,, if also adopt this method, will bring larger time delay to whole system.Thereby affected the real-time Transmission characteristic of total system.And parallel encoding is exactly the optimum method that addresses the above problem, and therefore the parallel encoding and decoding of research seem particularly important in present application.Along with the develop rapidly of digital technology, the figure place of its data can become longer in product in the future, and the bit wide of parallel encoding also can increase, and the more important thing is that the error correcting capability of its requirement requires also to become higher.

Summary of the invention

Goal of the invention:, for problems of the prior art and deficiency, the invention provides a kind of parallel encoding method and device of parameterized Bose-Chaudhuri Hocquenghem error correction codes.

Technical scheme: the parallel encoding method of parameterized Bose-Chaudhuri Hocquenghem error correction codes comprises the steps:

Determine the error correcting capability of error correcting code, but namely determine error correction figure place t, and the length k of information bit;

Solve the generator polynomial matrix, the number of times of generator polynomial g (X) is (n-k);

The figure place of parallel encoding is p, and the temporary variable of check digit and generator polynomial matrix carry out logical operation, last output encoder result;

Wherein, the information bit length k of input can be divided into the k/p equal portions by the figure place p of parallel encoding, if kmodp=0, and the figure place p of parallel encoding is the number of times (n-k) less than generator polynomial, passes through k/p beat, can complete whole codings; If kmodp ≠ 0, add extra z position 0 and make (k+z) modp=0 in information bit, wherein the value of z is fixed.With verilog HDL language output encoder result.

A kind of device of parallel encoding method of the Bose-Chaudhuri Hocquenghem error correction codes that adopts above-mentioned parameter, comprising: check digit temporary variable module, generator polynomial matrix module, logical operation module, coding result memory module; The prime information position described generator polynomial matrix module of input produces the generator polynomial matrix, check digit temporary variable and described generator polynomial matrix are by described logical operation module output data to described check digit temporary variable module, and described check digit temporary variable module is transferred to described coding result memory module with result.

The present invention adopts technique scheme, has following beneficial effect: compared with prior art, the parametrization of error correction figure place t of the present invention, can make this design can be applied in the situation of various error correcting capabilities requirements.The parametrization of the bit wide of parallel encoding, can make the hardware environment of this design consideration operation make coding rate reach maximum.The parametrization of the length of data message position, can encode to the information bit of different length the design., by this patent, can export a complete coding module of describing with verilog HDL language.The coding rate of the coding module that generates is fast, takies resource few.

Description of drawings

Fig. 1 is the Organization Chart of realizing that the present invention utilizes parallel encoding that the generator polynomial matrix realizes;

Fig. 2 is the RTL figure that the present invention adopts Verilog HDL hardware description language to realize, wherein, and t=12, p=64, k=4096;

Fig. 3 is data flow figure of the present invention.

Embodiment

Below in conjunction with specific embodiment, further illustrate the present invention, should understand these embodiment only is not used in and limits the scope of the invention for explanation the present invention, after having read the present invention, those skilled in the art all fall within the application's claims limited range to the modification of the various equivalent form of values of the present invention.

As Fig. 1-3, the parallel encoding method of parameterized Bose-Chaudhuri Hocquenghem error correction codes, comprise the steps:

(1) determine the error correcting capability of error correcting code, but namely determine error correction figure place t, and the length k of information bit;

(2) solve the generator polynomial matrix, the number of times of generator polynomial g (X) is (n-k);

(3) figure place of parallel encoding is p, and the temporary variable of check digit and generator polynomial matrix carry out logical operation, last output encoder result.

Concrete supposition: the information M=(m of (1) input ₀, m ₁, m ₂..., m _k-1) length be the k bit; (2) number of times of generator polynomial g (X) is (n-k); (3) p position information bit can be encoded simultaneously, namely the figure place of parallel encoding.In communication channel, we suppose that its coefficient is highest order the primary coefficient of information bit.For the continuous position of back, their number of times reduces successively, and last number of times is 0.

Therefore, according to above-mentioned condition, the length k of the information bit of input can be divided into the k/p equal portions by the figure place p of parallel encoding, if kmodp=0, and the figure place p of parallel encoding is the number of times (n-k) less than generator polynomial.P position information bit can be encoded simultaneously., through k/p beat, can complete whole codings; But under normal conditions, kmodp ≠ 0, we also can eliminate his impact by a suitable initial condition is set, and we can add extra z position 0 and make (k+z) modp=0 in information bit.Wherein the value of z is fixed, and knows in advance.

According to the base attribute of linear code, the original information bits M of input (X) can be comprised of the linear combination of p subsequence, uses M here _i(X) represent each subsequence., according to this method, can draw following formula:

M(X)＝m ₀+m ₁X+m ₂X ²+…+m _k-1X ^k-1＝M ₀(X)+M ₁(X)+…+M _p-1(X)

Wherein

$M_i\left(X\right)=\underset{j=0}{\overset{(k/p)-1}{\mathrm{\Σ}}}{m}_{j*p+j}{X}^{j*p+j}=m_i{X}^i+m_{p+i}{X}^{p+i}+m_{2p+i}{X}^{2p+i}+\·\·\·+m_{k-p+i}{X}^{k-p+i}$

According to the description of front, if kmodp ≠ 0 extra z position 0 on need adding,

Can be used as the M of time numerical digit 0 in information bit _i(X), X ^n-kThe computing of M (X) can be expressed as:

$X^{n-k}M\left(X\right)=X^{n-k}(M_0\left(X\right)+M_1\left(X\right)+\·\·\·+M_{p-1}\left(X\right))$

$=\underset{i=0}{\overset{r-1}{\mathrm{\Σ}}}{X}^{n-k}\underset{j=0}{\overset{(k/p)-1}{\mathrm{\Σ}}}{m}_{j*p+j}{X}^{(j+1)*p-1}$

$=\underset{i=0}{\overset{r-1}{\mathrm{\Σ}}}{X}^{n-k-(p-1)+i}\stackrel{\‾}{M_i}\left(X\right)$

Wherein,

$\stackrel{\‾}{M_i}\left(X\right)=\underset{j=0}{\overset{(k/p)-1}{\mathrm{\Σ}}}{m}_{j*p+j}{X}^{(j+1)*p-1}=m_i{X}^{p-i}+m_{p+i}{X}^{2p-1}+m_{2p+i}{X}^{3p-1}+\·\·\·+m_{k-p+i}{X}^{k-1}$

Therefore, at first the k position information bit of input is evenly distributed in p subsequence, i.e. M _i(X), wherein (0≤i≤p-1), each subsequence comprises the k/p position.According to above-mentioned formula (1-2) X ^n-kM (X) carries out suitable operation, can derive

Subsequence.This subsequence has two characteristics significantly: they can represent (1) with identical multinomial.When their number of times was non-zero, their number of times was identical.(2) having (p-1) individual this moment is 0 time continuously, and they are present between two adjacent message digits.Table 1 has been listed M _i(X) and

Relation, k=16 wherein, p=4.

According to the subsequence of above-mentioned derivation, the computing of parity check part also can be expressed as:

$S\left(X\right)=X^{n-k}M\left(X\right)\mathrm{mod}G\left(X\right)$

$=\underset{i=0}{\overset{P-1}{\mathrm{\Σ}}}{X}^{n-k-(p-1)+i}\stackrel{\‾}{M_i}\left(X\right)\mathrm{mod}G\left(X\right)$

$=(X^{n-k-p+1}\stackrel{\&OverBar;}{M_0}\left(X\right)+X^{n-k-p+2}\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="M"\; filenames="HDA00003626861400021.png"\; state="\{\{state\}\}">M</figure-callout>}}_1}\left(X\right)+\&CenterDot;\&CenterDot;\&CenterDot;+X^{n-k}\stackrel{\&OverBar;}{M_{P-1}}\left(X\right))\mathrm{mod}G\left(X\right)$

, according to the method for solving of the serial code of front, use X ^N-k-(p-1)+iPremultiplication with

Can be with mobile Entering p-1-i position divider from right-hand member realizes.

Table 1M _i(X) and

Relation

Transformation matrix T _gIts characteristic value is that the value by selected generator polynomial g (X) decides, and the row that can regard prediction matrix as, when considering that p may be the defeated value of non-zero, in the time step of the relevant p-1 of the following leading technology of application, its internal state is updated, and can represent with following equation:

$S(t+1)=T_g^{p-1}\left(T_g(S\left(t\right)\&CirclePlus;I\left(t\right))\right)=T_g^p(S\left(t\right)\&CirclePlus;I\left(t\right))$

Wherein, $I\left(t\right)={\left[0\right|m_{k-(t+1)p},m_{k-(t+1)p+1},\&CenterDot;\&CenterDot;\&CenterDot;,m_{k-(t+1)p+p-1}]}_{I\&times;(n-k)}^T$

According to following formula, the internal state of next S (t) is updated within a single clock cycle, because p information bit has identical number of times.State after we are designated as use clock signal that S (t+1) represents next state and trigger.

Fig. 2 has provided the RTL figure that adopts Verilog HDL hardware description language to realize, the signal in left side is the importation of this module, two outputs that signal is this module on right side, and the interface specific definition is as described in Table 2.

The explanation of table 2Parallel_encoder module interface

Also relate to a kind of device of parallel encoding method of the Bose-Chaudhuri Hocquenghem error correction codes that adopts above-mentioned parameter, comprise check digit temporary variable module, generator polynomial matrix module, logical operation module, coding result memory module; Prime information position input generator polynomial matrix module produces the generator polynomial matrix, check digit temporary variable and generator polynomial matrix are exported data to check digit temporary variable module by logical operation module, and check digit temporary variable module is transferred to the coding result memory module with result.

Embodiment:

The generator polynomial matrix of BCH (4320,4096,12) is The bit wide of parallel encoding is 64, and the target of design is simultaneously 64 information bits of parallel input to be encoded within each clock cycle, through completing the coding to 4096 bit data information in 64 clock cycle.Its detailed step is illustrated in fig. 2 shown below, wherein the n bit data within m clock cycle during data (m, n) presentation code; Parity_tem is the temporary variable of check digit, and function generate_gf () is the function that produces the generator polynomial matrix.T_g_r (m, n) is

An element of matrix, parity_bit are the check matrixes that generates, and have 156.T_g_r (155,155) * parity_temp represents the temporary variable of check digit and the logical operation of generator matrix.Concrete process is as follows:

1) 64 information bits move into the high 64 of parity_temp within the same clock cycle, and do logical operation.

2) 156 parity_temp in the generator polynomial matrix

Carry out logical operation.Result is given parity_temp.

3) repeat top two steps, after 64 clock cycle, the value of parity_temp the inside is exactly the check digit that will solve.

4) check digit that generates is above moved into parity_bit.

Claims (3)

1. the parallel encoding method of a parameterized Bose-Chaudhuri Hocquenghem error correction codes, is characterized in that, comprises the steps:

Determine the error correcting capability of error correcting code, but namely determine error correction figure place t, and the length k of information bit;

Solve the generator polynomial matrix, the number of times of generator polynomial g (X) is (n-k);

The figure place of parallel encoding is p, and the temporary variable of check digit and generator polynomial matrix carry out logical operation, last output encoder result;

Wherein, the information bit length k of input can be divided into the k/p equal portions by the figure place p of parallel encoding, if kmodp=0, and the figure place p of parallel encoding is the number of times (n-k) less than generator polynomial, passes through k/p beat, can complete whole codings; If kmodp ≠ 0, add extra z position 0 and make (k+z) modp=0 in information bit, wherein the value of z is fixed.

2. the parallel encoding method of parameterized Bose-Chaudhuri Hocquenghem error correction codes as claimed in claim 1, is characterized in that, with verilog HDL language output encoder result.

3. the device of the parallel encoding method of a Bose-Chaudhuri Hocquenghem error correction codes that adopts above-mentioned parameter, is characterized in that, comprises check digit temporary variable module, generator polynomial matrix module, logical operation module, coding result memory module; The prime information position described generator polynomial matrix module of input produces the generator polynomial matrix, check digit temporary variable and described generator polynomial matrix are by described logical operation module output data to described check digit temporary variable module, and described check digit temporary variable module is transferred to described coding result memory module with result.

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