CN105190887B - 紧凑型静电放电(esd)保护结构 - Google Patents
紧凑型静电放电(esd)保护结构 Download PDFInfo
- Publication number
- CN105190887B CN105190887B CN201480025014.7A CN201480025014A CN105190887B CN 105190887 B CN105190887 B CN 105190887B CN 201480025014 A CN201480025014 A CN 201480025014A CN 105190887 B CN105190887 B CN 105190887B
- Authority
- CN
- China
- Prior art keywords
- esd protection
- protection device
- field
- diode
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000003068 static effect Effects 0.000 title claims abstract description 7
- 230000004224 protection Effects 0.000 claims abstract description 63
- 230000005669 field effect Effects 0.000 claims abstract description 30
- 239000013078 crystal Substances 0.000 claims abstract description 5
- 230000006698 induction Effects 0.000 claims abstract description 5
- 238000004088 simulation Methods 0.000 claims description 12
- 230000008878 coupling Effects 0.000 claims description 10
- 238000010168 coupling process Methods 0.000 claims description 10
- 238000005859 coupling reaction Methods 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 4
- 230000000694 effects Effects 0.000 claims 1
- 238000007599 discharging Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005404 monopole Effects 0.000 description 3
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 230000003466 anti-cipated effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
多栅极肖特基耗尽型场效应晶体管FET、至少一个二极管及两个电阻器构成一种紧凑型静电放电ESD保护结构。此ESD保护结构可布设在比典型多个二极管ESD装置小的区域中。所述多栅极FET可包括各种类型的高电子迁移率晶体管HEMT装置,例如,(假晶)pHEMT、(变质)mHEMT、感应HEMT。所述肖特基场效应装置的多个栅极用于形成ESD触发及电荷泄放路径以用于保护在所述ESD保护装置之后的电路。单极性及双极性ESD保护装置两者均可提供于集成电路裸片上用于保护其输入/输出电路。
Description
相关专利申请案
本申请案主张由周培明-丹尼尔(Pei-Ming Daniel Chow)、郭永林(Yon-LinKok)、朱京(Jing Zhu)及史蒂文谢尔(Steven Schell)于2013年5月3日申请的标题为“紧凑型ESD保护结构(Compact ESD Protection Structure)”的共同拥有的第61/819,252号美国临时专利申请案的优先权,且所述美国临时专利申请案特此出于所有目的以引用的方式并入本文中。
技术领域
本发明涉及半导体保护结构,特定来说,涉及静电放电(ESD)保护结构。
背景技术
肖特基(Schottky)栅极耗尽型场效应装置由于其精细金属栅极结构(0.5μm或更小金属栅极长度)而对ESD损坏敏感。不同于CMOS硅或双极晶体管过程,在高电子迁移率晶体管(HEMT)过程中不存在可用于形成紧凑型ESD保护二极管的强健P-N结二极管。HEMT(也被称为异质结构FET(HFET)或调制掺杂FET(MODFET))为替代经掺杂区(如通常为MOSFET的情形)在具有不同带隙的两种材料之间并入有结(即,异质结)作为通道的场效应晶体管。存在数个版本的HEMT,例如,假晶HEMT(pHEMT)、变质HEMT(mHEMT)、感应HEMT等。形成有pHEMT装置的栅极的数个大肖特基二极管必须串联级联以充分保护有源HEMT电路。此多个肖特基二极管消耗昂贵GaAs集成电路裸片中的大区域。
肖特基二极管(也被称为热载流子二极管)为具有低正向电压降及非常快速的切换动作的半导体二极管。当电流流经二极管时,跨越二极管端子存在小电压降。正常二极管将具有在0.6伏特到1.7伏特之间的电压降,而肖特基二极管电压降通常在0.15伏特与0.45伏特之间。此较低电压降提供较好的***效率及较高的切换速度。在肖特基二极管中,半导体-金属结形成于半导体与金属之间,因此形成肖特基势垒。N型半导体充当阴极且金属侧充当肖特基二极管的阳极。此肖特基势垒既导致低正向电压降又导致非常快速的切换。可通过级联数个大的肖特基二极管来提供ESD保护。由于肖特基二极管的低接通电压,因此需要数个经堆叠二极管来处理操作电压,且需要大区域来处理电流。因此,使用肖特基二极管配置需要大的裸片区域。
发明内容
因此,需要一种与不需要使用肖特基二极管的HEMT及其它半导体装置兼容的高效且紧凑型ESD保护结构。
根据一实施例,一种静电放电(ESD)保护装置可包括:场效应晶体管(FET),其具有漏极、至少两个栅极及源极,其中所述场效应晶体管的所述漏极可耦合到将被保护以免受ESD事件的电路的节点;至少一个二极管,其耦合在所述FET的所述源极与电力供应器共同点之间;第一电阻器,其耦合在所述FET的所述至少两个栅极之间;及第二电阻器,其耦合到所述至少两个栅极及所述电力供应器共同点中的一者。
根据又一实施例,所述至少两个栅极中的一者可为触发栅极且所述至少两个栅极中的另一者可为放电栅极。根据又一实施例,所述FET可为耗尽型FET。根据又一实施例,所述至少一个二极管可为串联连接在所述FET的所述源极与电力供应器共同点之间的两个二极管。根据又一实施例,所述电力供应器共同点可耦合到电接地。根据又一实施例,所述耗尽型FET可为高电子迁移率晶体管(HEMT)。根据又一实施例,所述HEMT可为假晶HEMT(pHEMT)。根据又一实施例,所述HEMT可为变质HEMT(mHEMT)。根据又一实施例,所述HEMT可为感应HEMT。
根据又一实施例,所述FET、所述至少一个二极管以及所述第一电阻器及所述第二电阻器可制作于集成电路裸片上且耦合到所述电路节点,所述电路节点可耦合到所述集成电路裸片的外部连接。根据又一实施例,所述集成电路裸片的所述外部连接的功能可选自由以下各项组成的群组:模拟输入、数字输入、模拟输出、数字输出、模拟输入/输出、数字输入/输出、电力连接、偏置输入及外部补偿电容器。
根据另一实施例,一种静电放电(ESD)保护装置可包括:第一场效应晶体管(FET),其具有漏极、至少两个栅极及源极,其中所述第一场效应晶体管的所述漏极可耦合到将被保护以免受ESD事件的电路的节点;至少一个第一二极管,其具有耦合到所述第一FET的所述源极的阳极;第一电阻器,其耦合在所述第一FET的所述至少两个栅极之间;及第二电阻器,其耦合到所述至少两个栅极及所述至少一个第一二极管的阴极中的一者;第二场效应晶体管(FET),其具有漏极、至少两个栅极及源极,其中所述第二场效应晶体管的所述漏极可耦合到电力供应器共同点;至少一个第二二极管,其具有耦合到所述至少一个第一二极管的所述阴极的阴极;第三电阻器,其耦合在所述第二FET的所述至少两个栅极之间;及第四电阻器,其耦合到第二FET的所述至少两个栅极及所述至少一个第二二极管的阴极中的一者。
根据又一实施例,所述第一FET及所述第二FET的所述至少两个栅极中的一者可为触发栅极且所述第一FET及所述第二FET的所述至少两个栅极中的另一者可为放电栅极。根据又一实施例,所述第一FET及所述第二FET可为耗尽型FET。根据又一实施例,所述至少一个第一二极管及所述至少一个第二二极管可为各自串联连接在所述第一FET的所述源极与所述第二FET的所述源极之间的两个二极管。根据又一实施例,所述电力供应器共同点可耦合到电接地。根据又一实施例,所述第一耗尽型FET及所述第二耗尽型FET可为高电子迁移率晶体管(HEMT)。根据又一实施例,所述HEMT可选自由以下各项组成的群组:假晶HEMT(pHEMT)、变质HEMT(mHEMT)及感应HEMT。
根据又一实施例,所述第一FET及所述第二FET、所述至少一个第一二极管及所述至少一个第二二极管以及所述第一电阻器、所述第二电阻器、所述第三电阻器及所述第四电阻器可制作于集成电路裸片上且耦合到所述电路节点,所述电路节点可耦合到所述集成电路裸片的外部连接。根据又一实施例,所述集成电路裸片的所述外部连接的功能可包括射频信号输入。根据又一实施例,所述集成电路裸片的所述外部连接的功能可包括射频信号输出。
附图说明
通过参考结合附图进行的以下说明可获取对本发明的更完整理解,附图中:
图1图解说明根据本发明的教示的HEMT装置的示意性等角横截面图;
图2图解说明用于直流(DC)及控制端口的现有技术单极性耗尽型FET ESD保护装置的示意图;
图3图解说明根据本发明的特定实例性实施例的用于直流(DC)及控制端口的单极性多栅极肖特基耗尽型FET ESD保护装置的示意图;
图4图解说明图2中所展示的ESD保护装置的现有技术结构的示意性平面图;
图5图解说明根据本发明的特定实例性实施例的图3中所展示的ESD保护装置的结构的示意性平面图;
图6图解说明根据本发明的特定实例性实施例的图3中所展示的ESD保护装置的结构的更详细示意性平面图;
图7图解说明根据本发明的另一特定实例性实施例的用于射频(RF)端口的双极性多栅极肖特基耗尽型FET ESD保护装置的示意图;及
图8及8A图解说明根据本发明的特定实例性实施例的图7中所展示的ESD保护装置的结构的示意性平面图。
虽然本发明易于作出各种修改及替代形式,但已在图式中展示并在本文中详细描述本发明的特定实例性实施例。然而,应理解,本文对特定实例性实施例的说明并不打算将本发明限制于本文中所揭示的特定形式,而是相反,本发明打算涵盖如由所附权利要求书所定义的所有修改及等效形式。
具体实施方式
根据各个实施例,假晶高电子迁移率晶体管(pHEMT)(也被称为异质结构FET或调制掺杂FET)在本文中作为实例用来描述根据本文中所揭示的各个实施例的紧凑型ESD保护装置的概念。迄今为止,数个大肖特基二极管必须形成有pHEMT装置的栅极且经串联级联以增加电压并充分保护有源电路。此多个二极管装置消耗昂贵GaAs集成电路裸片中的大区域。根据本发明的各个实施例,提出使用多栅极HEMT来形成紧凑型ESD保护装置。HEMT装置的多栅极可用于形成ESD触发及电荷泄放路径以用于保护在所述ESD保护装置及结构之后的电路。可将ESD保护装置结构布设在比多个二极管ESD装置结构小得多的区域中。预期且在本发明的范围内,各种类型的HEMT装置(例如,pHEMT、mHEMT、感应HEMT等)可与本文中所揭示的ESD保护装置一起使用。
现在参考图式,其示意性地图解说明实例性实施例的细节。图式中,将由相似编号表示相似元件,且将由带有不同小写字母后缀的相似编号表示类似元件。
参考图1,根据本发明的教示描绘HEMT装置的示意性等角横截面图。出于说明性目的展示pHEMT,但预期且在本发明的范围内,可根据本发明的教示类似地使用其它HEMT装置。HEMT装置可包括衬底112、二维电子气体层110、间隔物108、势垒106、覆盖层104,以及金属漏极、源极及栅极电极102。源极、栅极及漏极金属102可包括(但不限于)金。势垒106可包括(但不限于)砷化铝镓(AlGaAs)。间隔物108可包括(但不限于)砷化镓(GaAs)。二维电子气体层110可包括(但不限于)砷化铟镓(InGaAs)。衬底可包括(但不限于)高电阻率GaAs。第一电阻器210可具有从约500欧姆到约2000欧姆的电阻值。第二电阻器212可具有约2000欧姆的电阻值。
参考图2及4,描绘用于直流(DC)及控制端口的现有技术单极性耗尽型FET ESD保护装置的示意图,以及图2中所展示的ESD保护装置的现有技术结构的示意性平面图。单极性单栅极ESD保护装置202已用于保护集成电路封装(未展示)的电路206的控制信号及/或偏置供应节点(引脚)。ESD保护装置202可包括:场效应晶体管(FET)208,其具有漏极(D)、源极(S)及单个栅极(G);第一肖特基二极管214及第二肖特基二极管216;第三二极管218;及第一栅极电阻器210及第二栅极电阻器212。第三二极管218为在发生ESD事件时导电(进入雪崩击穿)从而接通晶体管208的触发二极管。肖特基二极管214及216用于电压电平移位以防止耗尽型晶体管208在正常操作期间接通及传导电流。
参考图3、5及6,描绘根据本发明的特定实例性实施例的用于直流(DC)及控制端口的单极性多栅极肖特基耗尽型FET ESD保护装置的示意图,以及图3中所展示的ESD保护装置的结构的示意性平面图。具有肖特基多栅极的单极性ESD保护装置302可用于保护集成电路封装(未展示)的电路306的控制信号及/或偏置供应节点(引脚)。ESD保护装置302可包括:多栅极肖特基耗尽型场效应晶体管(FET)308(例如,HEMT装置),其具有漏极(D)、源极(S)、第一触发栅极(G1)及第二触发栅极(G2);第一二极管314及第二二极管316;及第一栅极电阻器310及第二栅极电阻器312。预期且在本发明的范围内,FET 308可具有两个或两个以上栅极。至少一个电平移位二极管可耦合在FET 308的源极与电力供应器共同点(例如,电接地)之间。FET 308的漏极可耦合到节点304,节点304可耦合到集成电路(IC)封装(未展示)的外部连接(引脚)。IC封装的外部连接(引脚)可用作(举例来说,但不限于)模拟输入、数字输入、模拟输出、数字输出、模拟输入/输出、数字输入/输出、电力连接、偏置输入、外部补偿电容器等。
当负静电电荷在节点304处积累时,将正向偏置第二触发栅极(G2)并通过第二栅极电阻器312将这些电荷泄放到接地。当正静电电荷在节点304处积累时,将积聚正电位,直到第一触发栅极(G1)处于反向击穿中。此击穿电流将流动到接地并跨越第二栅极电阻器312建立正电位。因此,当栅极到源极电位比串联连接的第一二极管314及第二二极管316的接通电压更具正性时,提供足够电压以借助其第二栅极G2接通FET 308。此第一二极管314及第二二极管316耦合在FET 308的源极与电力供应器共同点(例如,接地)之间并提供电压电平移位以防止耗尽型晶体管接通(导电)。FET 308的漏极电流提供另一路径以使节点304处的正静电电荷消散并有助于防止第一触发栅极G1具有可损坏第一触发栅极G1的过量击穿电流。
由此,多栅极结构FET 308为组合触发二极管装置与放电栅极FET(此节省宝贵的集成电路裸片区域)的独特方式。另外,仅三个有源装置区域对单极性多栅极ESD保护装置302为必需的:1)FET 308,2)第一二极管314,及3)第二二极管316。现有技术ESD保护装置202需要四个有源装置区域:1)FET 208,2)触发式第三二极管218,3)电平移位二极管214,及4)电平移位二极管216。因此,根据本发明的教示,现有技术ESD保护装置202需要比单极性多栅极ESD保护装置302所需大的集成电路裸片(未展示)上的有源装置区域来实现相同的ESD保护电平。
参考图7、8及8A,描绘根据本发明的另一特定实例性实施例的用于射频(RF)端口的双极性多栅极肖特基耗尽型FET ESD保护装置的示意图,以及图7中所展示的ESD保护装置的结构的示意性平面图。双极性多栅极肖特基耗尽型FET ESD保护装置702可用于保护集成电路封装(未展示)的电路706的控制信号及/或偏置供应节点(引脚)。ESD保护装置702可包括:第一HEMT装置308,其具有漏极、源极以及第一栅极(G1)及第二栅极(G2);第一二极管314及第二二极管316;第一栅极电阻器310及第二栅极电阻器312;第二HEMT装置708,其具有漏极、源极及第一栅极(G1)及第二栅极(G2);第三二极管714及第四二极管716;第三栅极电阻器710及第四栅极电阻器712。ESD保护装置702可有利地与和高RF电力装置相关联的RF端口一起使用。此ESD保护电路可在存在大的正RF电压摆幅及大的负RF电压摆幅的情况下使用。此双极性多栅极FET ESD保护装置702的工作原理实质上类似于单极性多栅极ESD保护装置302的工作原理。元件708到716用作元件308到316的镜像。
虽然已参考本发明的实例性实施例来描绘、描述及定义本发明的实施例,但此类参考并不暗示对本发明的限制,且不应推断出存在此限制。所揭示的标的物能够在形式及功能上具有大量修改、变更及等效形式,所属领域的技术人员将会联想到此类修改、变更及等效形式并受益于本发明。本发明的所描绘及所描述的实施例仅为实例,而并非对本发明的范围的穷尽性说明。
Claims (20)
1.一种静电放电ESD保护装置,其包括:
第一场效应晶体管,其具有漏极、至少两个栅极及一源极,其中所述第一场效应晶体管的所述漏极耦合到将被保护以免受ESD事件的电路的节点;
至少一个第一二极管,其耦合在所述第一场效应晶体管的所述源极与共同节点之间;
及
第一电阻器和第二电阻器,其串联耦合在所述至少两个栅极中的第一者及所述共同节点之间,其中位于所述第一电阻器和所述第二电阻器之间的第一节点与所述至少两个栅极中的第二者耦合。
2.根据权利要求1所述的ESD保护装置,其中所述共同节点为电力供应器共同点。
3.根据权利要求1所述的ESD保护装置,进一步包括:
第二场效应晶体管,其具有漏极,至少两个栅极及一源极,其中所述第二场效应晶体管的所述漏极耦合到电力供应器共同点;
至少一个第二二极管,其具有阴极,所述至少一个第二二极管的所述阴极耦合到所述至少一个第一二极管的阴极;
第三电阻器和第四电阻器,其串联耦合于所述第二场效应晶体管中的第一栅极和所述共同节点之间,其中位于所述第三电阻器和所述第四电阻器的第二节点与所述第二场效应晶体管中的第二栅极耦合。
4.根据权利要求1所述的ESD保护装置,其中所述第一场效应晶体管的所述至少两个栅极中的一者为触发栅极且所述至少两个栅极中的另一者为放电栅极。
5.根据权利要求3所述的ESD保护装置,其中所述第一场效应晶体管和所述第二场效应晶体管的所述至少两个栅极中的一者为触发栅极且所述至少两个栅极中的另一者为放电栅极。
6.根据权利要求1所述的ESD保护装置,其中所述第一场效应晶体管为耗尽型场效应晶体管。
7.根据权利要求3所述的ESD保护装置,其中所述第一场效应晶体管和所述第二场效应晶体管为耗尽型场效应晶体管。
8.根据权利要求1所述的ESD保护装置,其中所述至少一个第一二极管为串联连接在所述第一场效应晶体管的所述源极与所述共同节点之间的两个二极管。
9.根据权利要求3所述的ESD保护装置,其中所述至少一个第一二极管为串联连接在所述第一场效应晶体管的所述源极与所述共同节点之间的两个二极管,且所述至少一个第二二极管为串联连接在所述第二场效应晶体管的所述源极与所述共同节点之间的两个二极管。
10.根据权利要求2所述的ESD保护装置,其中所述电力供应器共同点耦合到电接地。
11.根据权利要求6或7所述的ESD保护装置,其中所述耗尽型场效应晶体管为高电子迁移率晶体管(HEMT)。
12.根据权利要求11所述的ESD保护装置,其中所述高电子迁移率晶体管(HEMT)为假晶高电子迁移率晶体管(pHEMT)。
13.根据权利要求11所述的ESD保护装置,其中所述高电子迁移率晶体管(HEMT)为变质高电子迁移率晶体管(mHEMT)。
14.根据权利要求11所述的ESD保护装置,其中所述高电子迁移率晶体管(HEMT)为感应高电子迁移率晶体管(HEMT)。
15.根据权利要求1所述的ESD保护装置,其中所述第一场效应晶体管;所述至少一个第一二极管;以及所述第一电阻器及所述第二电阻器制作于集成电路裸片上且耦合到电路节点,所述电路节点耦合到所述集成电路裸片的外部连接。
16.根据权利要求3所述的ESD保护装置,其中所述第一场效应晶体管和所述第二场效应晶体管;所述至少一个第一二极管和所述至少一个第二二极管;以及所述第一电阻器、所述第二电阻器、所述第三电阻器以及所述第四电阻器制作于集成电路裸片上且耦合到电路节点,所述电路节点耦合到所述集成电路裸片的外部连接。
17.根据权利要求2所述的ESD保护装置,其中所述第一场效应晶体管;所述至少一个第一二极管;及所述第一电阻器和第二电阻器制作于集成电路裸片上且耦合到电路节点,所述电路节点耦合到所述集成电路裸片的外部连接;且其中所述集成电路裸片的所述外部连接的功能选自由以下各项组成的群组:模拟输入、数字输入、模拟输出、数字输出、模拟输入/输出、数字输入/输出、电力连接、偏置输入及外部补偿电容器。
18.根据权利要求16所述的ESD保护装置,其中所述集成电路裸片的所述外部连接的功能选自由以下各项组成的群组:模拟输入、数字输入、模拟输出、数字输出、模拟输入/输出、数字输入/输出、电力连接、偏置输入及外部补偿电容器。
19.根据权利要求16所述的ESD保护装置,其中所述集成电路裸片的所述外部连接的功能包括射频信号输入。
20.根据权利要求16所述的ESD保护装置,其中所述集成电路裸片的所述外部连接的功能包括射频信号输出。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201361819252P | 2013-05-03 | 2013-05-03 | |
US61/819,252 | 2013-05-03 | ||
US14/267,185 US9431390B2 (en) | 2013-05-03 | 2014-05-01 | Compact electrostatic discharge (ESD) protection structure |
US14/267,185 | 2014-05-01 | ||
PCT/US2014/036499 WO2014179651A1 (en) | 2013-05-03 | 2014-05-02 | Compact electrostatic discharge (esd) protection structure |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105190887A CN105190887A (zh) | 2015-12-23 |
CN105190887B true CN105190887B (zh) | 2018-11-09 |
Family
ID=51841005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201480025014.7A Active CN105190887B (zh) | 2013-05-03 | 2014-05-02 | 紧凑型静电放电(esd)保护结构 |
Country Status (7)
Country | Link |
---|---|
US (2) | US9431390B2 (zh) |
EP (1) | EP2992555B1 (zh) |
JP (1) | JP6366687B2 (zh) |
KR (1) | KR102198021B1 (zh) |
CN (1) | CN105190887B (zh) |
TW (1) | TWI631685B (zh) |
WO (1) | WO2014179651A1 (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9627883B2 (en) | 2011-04-13 | 2017-04-18 | Qorvo Us, Inc. | Multiple port RF switch ESD protection using single protection structure |
US9728532B2 (en) * | 2011-04-13 | 2017-08-08 | Qorvo Us, Inc. | Clamp based ESD protection circuits |
US9431390B2 (en) * | 2013-05-03 | 2016-08-30 | Microchip Technology Incorporated | Compact electrostatic discharge (ESD) protection structure |
KR20150048427A (ko) * | 2013-10-28 | 2015-05-07 | 에스케이하이닉스 주식회사 | 디스차지 회로 |
US10610326B2 (en) * | 2015-06-05 | 2020-04-07 | Cianna Medical, Inc. | Passive tags, and systems and methods for using them |
KR102364340B1 (ko) * | 2015-06-30 | 2022-02-17 | 엘지디스플레이 주식회사 | 표시장치 |
JP6597357B2 (ja) * | 2016-02-09 | 2019-10-30 | 三菱電機株式会社 | 保護ダイオード付き電界効果トランジスタ |
US10158029B2 (en) * | 2016-02-23 | 2018-12-18 | Analog Devices, Inc. | Apparatus and methods for robust overstress protection in compound semiconductor circuit applications |
WO2017177074A1 (en) | 2016-04-06 | 2017-10-12 | Cianna Medical, Inc. | Reflector markers and systems and methods for identifying and locating them |
US10827949B2 (en) | 2016-04-06 | 2020-11-10 | Cianna Medical, Inc. | Reflector markers and systems and methods for identifying and locating them |
US20180026029A1 (en) * | 2016-07-21 | 2018-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated ESD Protection Circuit for GaN Based Device |
US10438940B2 (en) * | 2016-12-29 | 2019-10-08 | Nxp Usa, Inc. | ESD protection for depletion-mode devices |
US10475783B2 (en) * | 2017-10-13 | 2019-11-12 | Nxp B.V. | Electrostatic discharge protection apparatuses |
US10381828B1 (en) * | 2018-01-29 | 2019-08-13 | Dialog Semiconductor (Uk) Limited | Overvoltage protection of transistor devices |
US11883150B2 (en) | 2018-09-06 | 2024-01-30 | Cianna Medical, Inc. | Systems for identifying and locating reflectors using orthogonal sequences of reflector switching |
GB2580155A (en) * | 2018-12-21 | 2020-07-15 | Comet Ag | Radiofrequency power amplifier |
CN111756028B (zh) * | 2019-03-29 | 2022-07-01 | 北京小米移动软件有限公司 | 电子设备 |
CN114093864B (zh) * | 2019-05-15 | 2023-12-22 | 英诺赛科(珠海)科技有限公司 | 静电防护电路及电子装置 |
US11309435B2 (en) * | 2020-03-09 | 2022-04-19 | Globalfoundries U.S. Inc. | Bandgap reference circuit including vertically stacked active SOI devices |
US11764204B2 (en) * | 2020-06-18 | 2023-09-19 | Analog Devices, Inc. | Electrostatic discharge and overdrive protection circuitry |
CN117239685A (zh) * | 2022-06-08 | 2023-12-15 | 长鑫存储技术有限公司 | 静电保护结构、可控硅整流器和半导体存储器 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI317166B (en) * | 2006-08-23 | 2009-11-11 | Win Semiconductors Corp | On-chip esd protection circuit using enhancement-mode hemt/mesfet technology |
US7881029B1 (en) * | 2008-07-07 | 2011-02-01 | Rf Micro Devices, Inc. | Depletion-mode field effect transistor based electrostatic discharge protection circuit |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6826025B2 (en) * | 2002-05-20 | 2004-11-30 | International Business Machines Corporation | Method and apparatus for providing ESD protection and/or noise reduction in an integrated circuit |
US6835969B1 (en) * | 2003-06-26 | 2004-12-28 | Raytheon Company | Split-channel high electron mobility transistor (HEMT) device |
US6984853B2 (en) | 2004-02-26 | 2006-01-10 | Agilent Technologies, Inc | Integrated circuit with enhancement mode pseudomorphic high electron mobility transistors having on-chip electrostatic discharge protection |
JP2006165182A (ja) * | 2004-12-06 | 2006-06-22 | Toshiba Corp | 電界効果トランジスタ |
KR100818086B1 (ko) * | 2006-04-06 | 2008-03-31 | 주식회사 하이닉스반도체 | 정전기 방전 보호 회로 |
US7593204B1 (en) | 2006-06-06 | 2009-09-22 | Rf Micro Devices, Inc. | On-chip ESD protection circuit for radio frequency (RF) integrated circuits |
US8144441B2 (en) * | 2006-08-30 | 2012-03-27 | Triquint Semiconductor, Inc. | Electrostatic discharge protection circuit for compound semiconductor devices and circuits |
US7804669B2 (en) * | 2007-04-19 | 2010-09-28 | Qualcomm Incorporated | Stacked ESD protection circuit having reduced trigger voltage |
US9171963B2 (en) | 2011-04-11 | 2015-10-27 | University Of Central Florida Research Foundation, Inc. | Electrostatic discharge shunting circuit |
US9728532B2 (en) | 2011-04-13 | 2017-08-08 | Qorvo Us, Inc. | Clamp based ESD protection circuits |
US8970998B2 (en) * | 2012-12-31 | 2015-03-03 | Win Semiconductors Corp. | Compound semiconductor ESD protection devices |
US9064704B2 (en) * | 2013-02-15 | 2015-06-23 | Win Semiconductors Corp. | Integrated circuits with ESD protection devices |
US9431390B2 (en) * | 2013-05-03 | 2016-08-30 | Microchip Technology Incorporated | Compact electrostatic discharge (ESD) protection structure |
-
2014
- 2014-05-01 US US14/267,185 patent/US9431390B2/en active Active
- 2014-05-02 JP JP2016512060A patent/JP6366687B2/ja active Active
- 2014-05-02 EP EP14728389.9A patent/EP2992555B1/en active Active
- 2014-05-02 CN CN201480025014.7A patent/CN105190887B/zh active Active
- 2014-05-02 KR KR1020157031623A patent/KR102198021B1/ko active IP Right Grant
- 2014-05-02 WO PCT/US2014/036499 patent/WO2014179651A1/en active Application Filing
- 2014-05-02 TW TW103115860A patent/TWI631685B/zh active
-
2016
- 2016-08-29 US US15/250,855 patent/US9685432B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI317166B (en) * | 2006-08-23 | 2009-11-11 | Win Semiconductors Corp | On-chip esd protection circuit using enhancement-mode hemt/mesfet technology |
US7881029B1 (en) * | 2008-07-07 | 2011-02-01 | Rf Micro Devices, Inc. | Depletion-mode field effect transistor based electrostatic discharge protection circuit |
Also Published As
Publication number | Publication date |
---|---|
US9685432B2 (en) | 2017-06-20 |
JP2016521008A (ja) | 2016-07-14 |
TW201508894A (zh) | 2015-03-01 |
CN105190887A (zh) | 2015-12-23 |
KR102198021B1 (ko) | 2021-01-05 |
JP6366687B2 (ja) | 2018-08-01 |
US20160372459A1 (en) | 2016-12-22 |
WO2014179651A1 (en) | 2014-11-06 |
TWI631685B (zh) | 2018-08-01 |
EP2992555B1 (en) | 2018-04-04 |
US20140327048A1 (en) | 2014-11-06 |
EP2992555A1 (en) | 2016-03-09 |
US9431390B2 (en) | 2016-08-30 |
KR20160004290A (ko) | 2016-01-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105190887B (zh) | 紧凑型静电放电(esd)保护结构 | |
US10026712B2 (en) | ESD protection circuit with stacked ESD cells having parallel active shunt | |
JP6597357B2 (ja) | 保護ダイオード付き電界効果トランジスタ | |
CN103681658B (zh) | 双向异质结化合物半导体保护装置及其形成方法 | |
CN107104102A (zh) | 化合物半导体电路应用中的瞬态过应力保护的装置和方法 | |
US8964342B2 (en) | Compound semiconductor ESD protection devices | |
WO2006041087A1 (ja) | 高周波集積回路 | |
US10438940B2 (en) | ESD protection for depletion-mode devices | |
KR100582624B1 (ko) | 반도체 장치 | |
CN112470403B (zh) | 包括晶体管和二极管的电路和器件 | |
TWI495216B (zh) | 具有靜電保護元件之積體電路 | |
CN111192872A (zh) | 集成在氮化镓半导体装置上的嵌位电路及相关半导体装置 | |
US9991253B2 (en) | Protection element, protection circuit, and semiconductor integrated circuit | |
JP4535668B2 (ja) | 半導体装置 | |
US20140183544A1 (en) | Compound semiconductor esd protection devices | |
JPS61292965A (ja) | 半導体集積回路装置 | |
US8854112B2 (en) | FET drive circuit and FET module | |
US7173291B2 (en) | Vertical protecting element formed in semiconductor substrate and semiconductor device using the same | |
CN107293537B (zh) | 静电放电保护装置、存储器元件及静电放电保护方法 | |
US20240063301A1 (en) | Protective structure with depletion-mode and enhancement-mode transistors | |
US11870429B2 (en) | Circuits and methods for controlling a voltage of a semiconductor substrate | |
CN111180509B (zh) | 一种结型场效应管及其静电放电结构 | |
KR100676357B1 (ko) | 스위치 회로 장치 | |
JPS6239077A (ja) | 半導体素子保護回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |