CN105185756B - 半导体封装件和制造该半导体封装件的方法 - Google Patents
半导体封装件和制造该半导体封装件的方法 Download PDFInfo
- Publication number
- CN105185756B CN105185756B CN201510566385.2A CN201510566385A CN105185756B CN 105185756 B CN105185756 B CN 105185756B CN 201510566385 A CN201510566385 A CN 201510566385A CN 105185756 B CN105185756 B CN 105185756B
- Authority
- CN
- China
- Prior art keywords
- semiconductor package
- package part
- substrate
- encapsulated layer
- conductive elastic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48235—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
提供了一种半导体封装件和制造该半导体封装件的方法。所述半导体封装件包括:基板;至少一个芯片,设置在基板上;包封层,设置在基板上并包封至少一个芯片;导电弹性层,设置在基板的除包封层所占的区域之外的区域上并与包封层的至少一部分接触。在本发明的半导体封装件中,通过利用导电弹性层代替诸如环氧树脂的包封层的一部分,从而能够降低半导体封装件的整体翘曲。另外,由于导电弹性层具有高的散热特性,从而改善了半导体封装件的散热性。此外,由于将导电弹性层与基板的接地端所处的区域连接,从而能够改善半导体封装件的电磁屏蔽性能。
Description
技术领域
本发明的示例性实施例涉及半导体封装领域,具体地讲,涉及一种半导体封装件和制造该半导体封装件的方法。
背景技术
目前,在半导体封装件中,由于半导体封装件内的各元件的热膨胀系数(Coefficient of Thermal Expansion,CTE)不同,因此会导致该半导体封装件发生翘曲现象,继而影响后续的基板的贴装工艺和切割工艺。例如,当利用诸如环氧树脂的包封材料在基板上对半导体芯片进行包封时,会因包封材料的热膨胀和收缩而导致半导体封装件发生翘曲。
图1是示出了根据现有技术的半导体封装件的示意性剖视图,图2是示出了根据现有技术的半导体封装件的另一示意性剖视图。
参照图1和图2,根据现有技术的半导体封装件100包括基板110、设置在基板110上的芯片120、设置在基板110上并包封芯片120的包封层130以及形成在基板的与形成芯片的表面背对的表面上的焊球140。芯片120可以通过键合引线(如图1所示)或凸块(如图2所示)电连接到基板110。在形成包封层130时,通常会在相对高的温度下进行固化,从而导致在该固化工艺过程中实际上将基板110和芯片120加热至该温度下。在这样的温度下,热膨胀系数不同的基板110、芯片120和包封层130彼此结合,因此在温度降至室温时,包封层130的收缩会导致基板110沿其上安装了芯片的表面凹进的方向的翘曲,或者会导致基板110沿其上安装了芯片的表面凸起的方向的翘曲。此外,由于芯片120被较厚的包封层130包封,从而对半导体封装件100的散热产生不利影响。
此外,随着半导体封装件的日渐轻薄化,对于高密度、高频率的半导体封装件的翘曲和散热问题更为严重。因此,需要一种新的翘曲解决方案。
发明内容
为了解决现有技术中存在的上述问题,本发明的示例性实施例的目的在于提供一种改进的半导体封装件和制造该半导体封装件的方法。
根据本发明的一方面,提供了一种半导体封装件,所述半导体封装件包括:基板;至少一个芯片,设置在基板上;包封层,设置在基板上并包封至少一个芯片;导电弹性层,设置在基板的除包封层所占的区域之外的区域上并与包封层的至少一部分接触。
根据本发明的示例性实施例,导电弹性层可以包括能够固化的弹性石墨材料。
根据本发明的示例性实施例,包封层可以包括环氧树脂。
根据本发明的示例性实施例,导电弹性层可以与包封层的侧壁接触。
根据本发明的示例性实施例,导电弹性层可以包覆包封层。
根据本发明的示例性实施例,导电弹性层可以位于基板的接地端所处的区域上。
根据本发明的示例性实施例,芯片可以通过键合引线或凸块电连接到基板。
根据本发明的另一方面,提供了一种制造半导体封装件的方法,所述方法包括:将至少一个芯片设置在基板上;在基板上形成包封层以包封芯片,在基板的除包封层所占的区域之外的区域上形成与包封层的至少一部分接触的导电弹性层。
根据本发明的示例性实施例,导电弹性层可以包括能够固化的弹性石墨材料。
根据本发明的示例性实施例,包封层可以包括环氧树脂。
如上所述,在本发明的半导体封装件中,通过利用导电弹性层代替诸如环氧树脂的包封层的一部分,从而能够降低半导体封装件的整体翘曲。另外,由于导电弹性层具有高的散热特性,从而改善了半导体封装件的散热性。此外,由于将导电弹性层设置在基板的接地端所处的区域上,从而能够改善半导体封装件的电磁屏蔽性能。
附图说明
通过以下结合附图对实施例的描述,这些和/或其它方面将变得清楚且更容易理解,在附图中:
图1是示出了根据现有技术的半导体封装件的示意性剖视图;
图2是示出了根据现有技术的半导体封装件的另一示意性剖视图;
图3是示出了根据本发明的示例性实施例的半导体封装件的结构示意图;
图4是示出了根据本发明的另一示例性实施例的半导体封装件的结构示意图;
图5A至图5D是示出了根据本发明的示例性实施例的制造半导体封装件的方法的剖视图。
具体实施方式
现在将参照附图更充分地描述本发明的实施例,在附图中示出了本发明的示例性实施例。然而,本发明可以以许多不同的形式实施,而不应被解释为局限于在此阐述的实施例;相反,提供这些实施例使得本公开将是彻底的和完整的,并且这些实施例将向本领域的普通技术人员充分地传达本发明的实施例的构思。在下面详细的描述中,通过示例的方式阐述了多处具体的细节,以提供对相关教导的充分理解。然而,本领域技术人员应该清楚的是,可以实践本教导而无需这样的细节。在其它情况下,以相对高的层次而没有细节地描述了公知的方法、步骤、组件和电路,以避免使本教导的多个方面不必要地变得模糊。附图中的同样的标号表示同样的元件,因此将不重复对它们的描述。在附图中,为了清晰起见,可能会夸大层和区域的尺寸和相对尺寸。
现在将在下文中参照附图更充分地描述本发明。
图3是示出了根据本发明的示例性实施例的半导体封装件的结构示意图。图4是示出了根据本发明的另一示例性实施例的半导体封装件的结构示意图。
参照图3和图4,根据本发明的当前实施例的半导体封装件200包括:基板210;芯片220,设置在基板210上;包封层230,设置在基板210上并包封芯片220;导电弹性层240,设置在基板210的除包封层230所占的区域之外的区域上。
根据本发明的半导体封装件200的基板210可以采用本领域常用的材料制成,在此不作特别限定。如图3所示,根据本发明的实施例的芯片220可以通过键合引线250(例如,金线)与基板210电连接,然而,本发明不限于此,例如,也可以通过在芯片220和基板210之间设置凸块,以实现芯片220与基板210之间的电连接。
包封层230设置在基板210的其上贴附有芯片220的表面上并包封芯片220,从而保护芯片220免受外部环境(例如,湿气和/或空气)的影响,并使芯片120与外部绝缘。另外,包封层230可以包括环氧树脂,然而本发明并不限于此。
导电弹性层240设置在基板210的除包封层230所占的区域之外的区域上并与包封层230的至少一部分接触。根据本发明的示例性实施例,导电弹性层可以具有高的散热特性并且能够吸收并释放诸如环氧树脂的包封层的应力。根据本发明的示例性实施例,导电弹性层240可以包括能够固化的弹性石墨材料。
根据本发明的示例性实施例,导电弹性层240可以仅与包封层230的侧壁接触,也即包封层230的上表面未被导电弹性层240覆盖,如图3所示。导电弹性层240可以包覆包封层230,此时,包封层230可以作为半导体封装件200的第一包封层,而导电弹性层240可以作为半导体封装件200的第二包封层。此外,导电弹性层240可以位于基板210的接地端所处的区域上,即导电弹性层240与基板210上的Vss信号连接,从而改善半导体封装件的电磁屏蔽性能。
如图3和图4所示,根据本发明的示例性实施例,半导体封装件200还可以包括形成在基板210的与其上形成有芯片220的表面背对的表面上的焊球260。可以选用常用方法或手段将焊球260形成在基底210上。
在本发明的半导体封装件中,通过利用导电弹性层代替诸如环氧树脂的包封层的一部分,从而能够降低半导体封装件的整体翘曲。另外,由于导电弹性层具有高的散热特性,从而改善了半导体封装件的散热性。此外,由于将导电弹性层设置在基板的接地端所处的区域上,从而能够改善半导体封装件的电磁屏蔽性能。
下面将参照图5A至图5D并以导电弹性层240包覆包封层230的情况为例详细描述制造根据本发明的示例性实施例的半导体封装件的方法。
图5A至图5D是示出了根据本发明的示例性实施例的制造半导体封装件的方法的剖视图。
参照图5A,首先,将芯片220设置在基板210上,其中,芯片220通过键合引线250电连接到基板210。具体地讲,通过粘结剂(未示出)将芯片220贴附在基板210上,然后使芯片220与基板210通过键合引线250连接,以实现芯片220与基板210之间的电连接。
接下来,参照图5B,在基板210上形成包封层230以包封芯片220。具体地讲,可以将诸如环氧树脂的包封材料注入到基板210上并使其固化,从而包封芯片220。
然后,参照图5C,在基板210的除包封层230所占的区域之外的区域上形成导电弹性层240,并且使导电弹性层240包覆包封层230。此外,也可以将导电弹性层240仅形成在包封层230的侧壁处,以形成如图3所示的半导体封装件。
最后,参照图5D,在基板210的与形成芯片220的表面背对的表面上形成焊球260,从而形成半导体封装件200。可以选用常用方法或手段将焊球260形成在基底210上。
在本发明的半导体封装件中,通过利用导电弹性层代替诸如环氧树脂的包封层的一部分,从而能够降低半导体封装件的整体翘曲。
另外,由于导电弹性层具有高的散热特性,从而改善了半导体封装件的散热性。此外,由于将导电弹性层设置在基板的接地端所处的区域上,从而能够改善半导体封装件的电磁屏蔽性能。
虽然已经参照本发明的示例性实施例具体地示出并描述了本发明,但是本领域普通技术人员将理解,在不脱离如所附权利要求和它们的等同物所限定的本发明的精神和范围的情况下,可以在此做出形式和细节上的各种改变。应当仅仅在描述性的意义上而不是出于限制的目的来考虑实施例。因此,本发明的范围不是由本发明的具体实施方式来限定,而是由权利要求书来限定,该范围内的所有差异将被解释为包括在本发明中。
Claims (10)
1.一种半导体封装件,其特征在于所述半导体封装件包括:
基板;
至少一个芯片,设置在基板上;
包封层,设置在基板上并包封至少一个芯片;
导电弹性层,设置在基板的除包封层所占的区域之外的区域上并与包封层的至少一部分接触。
2.根据权利要求1所述的半导体封装件,其特征在于,导电弹性层包括能够固化的弹性石墨材料。
3.根据权利要求1所述的半导体封装件,其特征在于,包封层包括环氧树脂。
4.根据权利要求1所述的半导体封装件,其特征在于,导电弹性层与包封层的侧壁接触。
5.根据权利要求1所述的半导体封装件,其特征在于,导电弹性层包覆包封层。
6.根据权利要求1所述的半导体封装件,其特征在于,导电弹性层位于基板的接地端所处的区域上。
7.根据权利要求1所述的半导体封装件,其特征在于,芯片通过键合引线或凸块电连接到基板。
8.一种制造半导体封装件的方法,其特征在于所述方法包括:
将至少一个芯片设置在基板上;
在基板上形成包封层以包封芯片,
在基板的除包封层所占的区域之外的区域上形成与包封层的至少一部分接触的导电弹性层。
9.根据权利要求8所述的方法,其特征在于,导电弹性层包括能够固化的弹性石墨材料。
10.根据权利要求8所述的方法,其特征在于,包封层包括环氧树脂。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510566385.2A CN105185756B (zh) | 2015-09-08 | 2015-09-08 | 半导体封装件和制造该半导体封装件的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510566385.2A CN105185756B (zh) | 2015-09-08 | 2015-09-08 | 半导体封装件和制造该半导体封装件的方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN105185756A CN105185756A (zh) | 2015-12-23 |
CN105185756B true CN105185756B (zh) | 2018-04-13 |
Family
ID=54907746
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510566385.2A Active CN105185756B (zh) | 2015-09-08 | 2015-09-08 | 半导体封装件和制造该半导体封装件的方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105185756B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9953933B1 (en) * | 2017-03-30 | 2018-04-24 | Stmicroelectronics, Inc. | Flow over wire die attach film and conductive molding compound to provide an electromagnetic interference shield for a semiconductor die |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101097904A (zh) * | 2006-06-27 | 2008-01-02 | 力成科技股份有限公司 | 减少翘曲的封装结构 |
CN103794576A (zh) * | 2014-01-26 | 2014-05-14 | 清华大学 | 一种封装结构及封装方法 |
CN103915555A (zh) * | 2013-01-04 | 2014-07-09 | 隆达电子股份有限公司 | 发光二极管封装结构的制造方法 |
CN104409366A (zh) * | 2014-11-19 | 2015-03-11 | 三星半导体(中国)研究开发有限公司 | 芯片封装方法及封装基底 |
-
2015
- 2015-09-08 CN CN201510566385.2A patent/CN105185756B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101097904A (zh) * | 2006-06-27 | 2008-01-02 | 力成科技股份有限公司 | 减少翘曲的封装结构 |
CN103915555A (zh) * | 2013-01-04 | 2014-07-09 | 隆达电子股份有限公司 | 发光二极管封装结构的制造方法 |
CN103794576A (zh) * | 2014-01-26 | 2014-05-14 | 清华大学 | 一种封装结构及封装方法 |
CN104409366A (zh) * | 2014-11-19 | 2015-03-11 | 三星半导体(中国)研究开发有限公司 | 芯片封装方法及封装基底 |
Also Published As
Publication number | Publication date |
---|---|
CN105185756A (zh) | 2015-12-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20070045798A1 (en) | Semiconductor package featuring metal lid member | |
CN109716511A (zh) | 具有增强性能的晶片级封装 | |
KR101398404B1 (ko) | 기계적으로 분리된 리드 부착물을 갖는 플라스틱오버몰딩된 패키지들 | |
CN103456701A (zh) | 带有散热器的集成电路管芯组件 | |
US20060091542A1 (en) | Flip chip package including a heat spreader having an edge with a recessed edge portion and method of making the same | |
CN103681544A (zh) | 用于具有集成散热器的ic封装件的混合热界面材料 | |
KR20080013864A (ko) | 하나의 집적 회로를 다른 집적 회로 상에 적층하기 위한구조 | |
KR102231769B1 (ko) | 고열전도를 위한 히트싱크 노출형 반도체 패키지 및 그 제조방법 | |
CN106653710A (zh) | 装备有散热器的电子设备 | |
JP5751079B2 (ja) | 半導体装置及びその製造方法 | |
CN105321908A (zh) | 半导体器件及半导体器件的制造方法 | |
KR20160071319A (ko) | 반도체 패키지 및 그 제조 방법 | |
CN105720019B (zh) | 具有盖帽的图像感测装置和相关方法 | |
CN105185756B (zh) | 半导体封装件和制造该半导体封装件的方法 | |
KR19980041849A (ko) | 정전방전 보호기능을 갖는 리드 프레임과 그의 제조방법 및 패키지화된 반도체 장치와,정전방전 보호장치를 형성하는 방법 및정전방전 보호장치를 리드 프레임에 있는 다수의 리드에 부착하는 방법 | |
KR101833155B1 (ko) | 플렉시블하게-랩핑된 집적 회로 다이 | |
US8686547B1 (en) | Stack die structure for stress reduction and facilitation of electromagnetic shielding | |
US9006904B2 (en) | Dual side package on package | |
WO2021119930A1 (zh) | 芯片封装及其制作方法 | |
CN104392969A (zh) | 一种多芯片集成电路抗冲击封装结构 | |
CN107731764A (zh) | 一种半导体封装结构 | |
CN106910723B (zh) | 半导体封装件和制造该半导体封装件的方法 | |
CN103354228A (zh) | 半导体封装件及其制造方法 | |
US20120133039A1 (en) | Semiconductor package with thermal via and method of fabrication | |
JP5428123B2 (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |