CN105185747B - A kind of integrated technique for reducing cmos image sensor white pixel - Google Patents
A kind of integrated technique for reducing cmos image sensor white pixel Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000010410 layer Substances 0.000 claims abstract description 57
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- 239000011159 matrix material Substances 0.000 claims abstract description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 36
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 238000002347 injection Methods 0.000 claims abstract description 15
- 239000007924 injection Substances 0.000 claims abstract description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 15
- 229920005591 polysilicon Polymers 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 230000008569 process Effects 0.000 claims abstract description 11
- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 239000011229 interlayer Substances 0.000 claims abstract description 4
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 4
- 238000007667 floating Methods 0.000 claims description 4
- 239000007943 implant Substances 0.000 claims description 4
- 230000009467 reduction Effects 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
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- 238000001039 wet etching Methods 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
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- 238000005516 engineering process Methods 0.000 description 6
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- 238000004519 manufacturing process Methods 0.000 description 3
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
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Abstract
The integrated technique of cmos image sensor white pixel is reduced the invention discloses a kind of, including forms shallow trench isolation in the base；A pad oxide and a silicon nitride barrier are grown successively in matrix surface；Photoresist is applied, using patterned photoresist as barrier layer, and passes through silicon nitride barrier, ion implanting is carried out to matrix, to form photodiode and surrounding isolated area in the base；Silicon nitride barrier and pad oxide are removed, then, grows gate oxide and polysilicon layer；Polysilicon transmission grid and side wall are formed, and carries out shallow-layer ion implanting；Form interlayer dielectric and metal layer.Silicon nitride barrier can stop in ion implanting, especially energetic ion injection process because of the introduced metal impurities of metallic element of electronics shower volatilization, lattice defect of the ion implanting in shallow region caused by electrical arcing can be reduced at the same time, so as to be effectively reduced white pixel.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, reduces cmos image more particularly, to one kind and passes
The integrated technique of sensor white pixel.
Background technology
In recent years, as the rapid development of mobile network, mobile intelligent terminal are popularized in large quantities, and it is continuously updated and changes
Generation.And as the imaging sensor of mobile terminal " eyes ", also the followed by demand in market, ceaselessly improves the property of oneself
Energy.
The direction of future image sensor development is high pixel, low-power consumption, high image quality.High pixel and low-power consumption require pixel
Size constantly reduces.However, with the diminution of Pixel Dimensions, the quality of pixel but drastically declines, particularly quantum efficiency and
Noise.Quantum efficiency can be injected by energetic ion elongates photodiode depth to make up, but the reduction of noise is non-
Normal difficulty.
One important parameter of characterization pixel noise is the number of white pixel.White pixel refers to those brightness relative to surrounding
The extremely higher pixel of pixel intensity, white pixel number is more, and the quality of image is poorer.
At present, white picture is all repaired using specific logical operation circuit by most of cmos image sensor manufacturer
Element.This logic circuit can repair most of white pixel, but preprosthetic white pixel is passing through logical operation reparation
Afterwards, certain influence can be more or less produced to the original color of surrounding pixel.Therefore, preprosthetic white pixel number is reduced
It is still to improve picture quality importance.
White pixel mostlys come from metallic pollution or lattice defect in photodiode.Cmos image is reduced in technique to pass
The main method of sensor white pixel is to control the introducing of metallic pollution and lattice defect in technical process, such as the operation at board end
Component, which is tried one's best, selects the material without metallic element, and wafer selects silicon chip with epitaxial layer, etc. as far as possible.Although these measure energy
The number of white pixel is enough reduced, but technical process control is extremely difficult, because very low metallic pollution concentration can just cause
The drastically rise of white pixel.
The content of the invention
It is an object of the invention to overcome drawbacks described above existing in the prior art, there is provided one kind reduces cmos image sensor
The integrated technique of white pixel, can be effectively reduced white pixel.
To achieve the above object, technical scheme is as follows：
A kind of integrated technique for reducing cmos image sensor white pixel, comprises the following steps：
Step S01：One silicon substrate is provided, shallow trench isolation is formed in described matrix；
Step S02：A pad oxide and a silicon nitride barrier are grown successively on described matrix surface；
Step S03：Photoresist is applied, using patterned photoresist as barrier layer, and silicon nitride barrier is passed through, to described
Matrix carries out ion implanting, to form photodiode and surrounding isolated area in described matrix；Wherein, also by with nitrogen
Barrier layer when SiClx barrier layer is as ion implanting, stops electronics shower institute in ion implantation process using silicon nitride barrier
The metallic element ion of volatilization, while ion implanting is reduced in shallow region implant damage caused by electrical arcing, to have
Effect reduces white pixel；
Step S04：The silicon nitride barrier and pad oxide are removed, then, grows gate oxide and polysilicon layer；
Step S05：Polysilicon transmission grid and side wall are formed, and carries out shallow-layer ion implanting；Formed interlayer dielectric and
Metal layer.
Preferably, the thickness of the pad oxide is not less than 6nm.
Preferably, the thickness of the silicon nitride barrier is 30~100nm.
Preferably, in step S03, using energetic ion injection mode, formed in described matrix photodiode and its
The isolated area of surrounding.
Preferably, in step S03, using energetic ion injection mode, formed in described matrix N-type photodiode and
Surrounding deep p+isolated area.
Preferably, in step S04, silicon nitride barrier and pad oxide are removed using wet etching.
Preferably, in step S05, using chemical vapor deposition method growing polycrystalline silicon layer, and photoetching and etching are passed through
Technique prepares to form polysilicon transmission grid.
Preferably, using ion implanting mode, the photodiode being made of gradual PN junction is formed, matrix is p-type, from depth
Gradually increase to shallow donor's type impurity concentration, be transitioned into N+ types from N-type successively.
Preferably, in step S05, using shallow-layer ion implanting mode, P+ type region is formed in photodiode surface, with
Photodiode is isolated with matrix surface.
Preferably, in step S05, using shallow-layer ion implanting mode, N+ types floating diffusion region is formed, as transmission grid
Leakage.
It can be seen from the above technical proposal that the present invention is directed to the problem of cmos image sensor white pixel is higher, pass through
In ion implantation process, one layer of silicon nitride barrier is introduced, which can stop ion implanting, especially energetic ion
Because of the metal impurities that the metallic element of electronics shower volatilization is introduced in injection process, while ion implanting can be reduced in shallow-layer
Lattice defect of the region caused by electrical arcing, so as to be effectively reduced white pixel.
Brief description of the drawings
Fig. 1 is a kind of flow chart for the integrated technique for reducing cmos image sensor white pixel of the present invention；
Fig. 2~Fig. 8 is to make cmos image sensor pixel unit according to the method for Fig. 1 in a preferred embodiment of the present invention
When processing step schematic diagram；
Fig. 9 a~Fig. 9 b are to make CMOS figures using the ion implanting mode of traditional ion implanting mode and the present invention
Contrast schematic diagram during as sensor；Wherein, Fig. 9 a represent traditional ion implanting mode, and Fig. 9 b represent the ion note of the present invention
Enter mode.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in further detail.
It should be noted that in following embodiments, when embodiments of the present invention are described in detail, in order to clear
Ground represents the present invention in order to illustrate, special not draw to the structure in attached drawing according to general proportion, and has carried out partial enlargement, become
Shape and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In embodiment of the invention below, passed referring to Fig. 1, Fig. 1 is a kind of cmos image that reduces of the invention
The flow chart of the integrated technique of sensor white pixel；Meanwhile Fig. 2~Fig. 8 is please referred to, Fig. 2~Fig. 8 is that the present invention one is preferably real
Processing step schematic diagram when applying in example according to the method for Fig. 1 making cmos image sensor pixel unit.As shown in Figure 1, this
A kind of integrated technique of reduction cmos image sensor white pixel of invention, comprises the following steps：
As shown in frame 01, step S01：One silicon substrate is provided, shallow trench isolation is formed in described matrix.
Refer to Fig. 2.First, conventional CMOS planar technologies can be used, pass through photoetching, etching and chemical vapor deposition
Etc. technique, the shallow-layer area in matrix 1 makes to form shallow trench isolation 2.In order to control the lattice defect in matrix, its production is reduced
The influence of raw white pixel, employs the P-type wafer with epitaxial layer as basis material in the present embodiment.
As shown in frame 02, step S02：A pad oxide and a silicon nitride barrier are grown successively on described matrix surface.
Please continue to refer to Fig. 2.Then, a pad oxide 3 is grown on 1 surface of described matrix.Wherein, positioned at the pad of active area
Oxide layer should keep certain thickness, such as should keep the pad oxide of one layer of 6nm thickness.Therefore, the growth of the pad oxide
Thickness should be not less than 6nm.
Refer to Fig. 3.Then, one silicon nitride barrier 4 of regrowth on pad oxide 3.In the method for the invention,
Silicon nitride layer will act as barrier layer during ion implanting, and therefore, silicon nitride layer should have necessary thickness.Implement as preferable
Mode, the thickness of the silicon nitride barrier can be 30~100nm.
As shown in frame 03, step S03：Photoresist is applied, using patterned photoresist as barrier layer, and is hindered through silicon nitride
Barrier, ion implanting is carried out to described matrix, to form photodiode and surrounding isolated area in described matrix.
Refer to Fig. 4.Then, one layer of photoresist (figure omits) is applied on silicon nitride barrier, and passes through photoetching, etching
Mode is patterned the photoresist.Using patterned photoresist as barrier layer, the area of ion implanting will need not be carried out
Domain is covered, and removes the photoresist for needing to carry out ion implanted regions.Then, during then using silicon nitride layer 4 as ion implanting
Barrier layer, and pass through silicon nitride barrier, ion implanting carried out to described matrix 1.After ion implanting, in described matrix
Middle formation photodiode 5 and surrounding isolated area 6.
It is the ion implanting using traditional ion implanting mode and the present invention to refer to Fig. 9 a~Fig. 9 b, Fig. 9 a~Fig. 9 b
Contrast schematic diagram of the mode when making cmos image sensor；Wherein, Fig. 9 a represent traditional ion implanting mode, Fig. 9 b generations
The ion implanting mode of the table present invention.As illustrated in fig. 9, traditional ion implantation technology, injects ion (downward arrow as shown
Head is signified) only need to be through one layer of pad oxide 3 on matrix 1, you can reach deep ion injection zone 15 predetermined in matrix.
This region is used for forming photodiode and surrounding isolated area.Due to inject depth requirement, typically using high energy from
Son is injected.In energetic ion injection process, because electronics shower acts on volatilized metallic element ion 13, to base layer
In photodiode cause metallic pollution.And ion implanting in shallow region due to electrical arcing, will also produce injection damage
Wound 14, causes the lattice damage of photodiode in matrix.
As shown in figure 9b, in the integrated technique of reduction cmos image sensor white pixel provided by the invention, employ
The double-decker of pad oxide 3 plus silicon nitride barrier 4, on this basis, then carries out ion implantation process.Hindered using silicon nitride
Barrier 4 can stop the metallic element ion 13 that electronics shower is volatilized in ion implanting, especially energetic ion injection process,
Ion implanting can be reduced in shallow region implant damage 14 caused by electrical arcing at the same time, thus can be effectively reduced white
Pixel.It can be seen that by comparison diagram 9a and Fig. 9 b under the barrier effect of silicon nitride barrier 4, because electronics shower acts on institute
The metallic element ion 13 of volatilization, will be effectively resisted in silicon nitride barrier 4, so as to avoid 1 mid-deep strata of matrix from
The photodiode of sub- injection zone 15 is contaminated.Meanwhile using silicon nitride layer bear ion implanting shallow region due to
Most of implant damage 14 caused by electrical arcing, so as to effectively reduce the lattice damage phenomenon of photodiode in matrix.
In order to ensure certain depth during injection, energetic ion can be used to inject the leading ion injection side as this stage
Formula, and N-type photodiode 5 and surrounding deep p+isolated area 6 are formed in described matrix 1 by ion implanting.Photoelectricity
Make the isolation of deep layer region around diode 5 by P+ type region 6, shallow-layer area is using shallow trench isolation 2.
As shown in frame 04, step S04：Remove the silicon nitride barrier and pad oxide, then, growth gate oxide and
Polysilicon layer.
Refer to Fig. 5.Then, the silicon nitride barrier 4 on 1 surface of matrix and pad oxide 3 are removed totally.Can be excellent
Choosing removes silicon nitride barrier and pad oxide using wet-etching technology.
Refer to Fig. 6.Then, one layer of gate oxidation is grown in the matrix surface for eliminating silicon nitride barrier and pad oxide
Layer 7 and polysilicon layer.As optional embodiment, chemical vapor deposition method growth gate oxide and polysilicon can be used
Layer.
As shown in frame 05, step S05：Polysilicon transmission grid and side wall are formed, and carries out shallow-layer ion implanting；Forming layer
Between dielectric and metal layer.
Please continue to refer to Fig. 6.Then, can prepare to form polysilicon transmission grid 8 and grid by photoetching and etching technics
Side wall.
Refer to Fig. 7.Then, using shallow-layer ion implanting mode, the photodiode with gradual PN junction structure is formed
5, and form a P+ type region 9 in this photodiode upper surface and form N+ types floating diffusion region 10 in drain terminal.Wherein, light
Electric diode 5 is made of gradual PN junction, and matrix is p-type, is gradually increased from depth to shallow donor's type impurity concentration, successively from N-type mistake
Cross to N+ types.This 5 structure of photodiode can be formed by the deep layer ion implanting combination different with shallow-layer.Photoelectricity two
The P+ type region 9 of pole pipe upper surface is used for being isolated photodiode with body upper surface.Make N+ types floating diffusion region 10
To transmit the drain terminal of grid 8.
Refer to Fig. 8.Finally, the CMOS technology of standard can be used, 11 He of interlayer dielectric is continuously formed above matrix 1
Metal layer 12 and other corresponding steps, complete the manufacturing process of cmos image sensor pixel unit.
In conclusion the present invention is directed to the problem of cmos image sensor white pixel is higher, by ion implantation process
In, one layer of silicon nitride barrier is introduced, which can stop in ion implanting, especially energetic ion injection process because of electricity
Stranguria during pregnancy bathes the introduced metal impurities of the metallic element to volatilize, while can reduce ion implanting in shallow region since electric arc is imitated
Caused lattice defect is answered, so as to be effectively reduced white pixel.
It is above-described to be merely a preferred embodiment of the present invention, the embodiment and the patent guarantor for being not used to the limitation present invention
Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in
In protection scope of the present invention.
Claims (10)
1. a kind of integrated technique for reducing cmos image sensor white pixel, it is characterised in that comprise the following steps：
Step S01：One silicon substrate is provided, shallow trench isolation is formed in described matrix；
Step S02：A pad oxide and a silicon nitride barrier are grown successively on described matrix surface；
Step S03：Photoresist is applied, using patterned photoresist as barrier layer, and silicon nitride barrier is passed through, to described matrix
Ion implanting is carried out, to form photodiode and surrounding isolated area in described matrix；Wherein, also by with silicon nitride
Barrier layer when barrier layer is as ion implanting, stops that electronics shower is volatilized in ion implantation process using silicon nitride barrier
Metallic element ion, while ion implanting is reduced in shallow region implant damage caused by electrical arcing, effectively to drop
Low white pixel；
Step S04：The silicon nitride barrier and pad oxide are removed, then, grows gate oxide and polysilicon layer；
Step S05：Polysilicon transmission grid and side wall are formed, and carries out shallow-layer ion implanting；Form interlayer dielectric and metal
Layer.
2. the integrated technique according to claim 1 for reducing cmos image sensor white pixel, it is characterised in that the pad
The thickness of oxide layer is not less than 6nm.
3. the integrated technique according to claim 1 for reducing cmos image sensor white pixel, it is characterised in that the nitrogen
The thickness on SiClx barrier layer is 30~100nm.
4. the integrated technique according to claim 1 for reducing cmos image sensor white pixel, it is characterised in that step
In S03, using energetic ion injection mode, photodiode and surrounding isolated area are formed in described matrix.
5. the integrated technique of the reduction cmos image sensor white pixel according to claim 1 or 4, it is characterised in that step
In rapid S03, using energetic ion injection mode, formed in described matrix N-type photodiode and surrounding deep p+every
From area.
6. the integrated technique according to claim 1 for reducing cmos image sensor white pixel, it is characterised in that step
In S04, silicon nitride barrier and pad oxide are removed using wet etching.
7. the integrated technique according to claim 1 for reducing cmos image sensor white pixel, it is characterised in that step
In S05, prepare to form polysilicon biography using chemical vapor deposition method growing polycrystalline silicon layer, and by photoetching and etching technics
Defeated grid.
8. it is according to claim 1 reduce cmos image sensor white pixel integrated technique, it is characterised in that using from
Sub- injection mode, forms the photodiode being made of gradual PN junction, and matrix is p-type, from depth to shallow donor's type impurity concentration by
It is cumulative to add, successively N+ types are transitioned into from N-type.
9. the integrated technique according to claim 1 for reducing cmos image sensor white pixel, it is characterised in that step
In S05, using shallow-layer ion implanting mode, P+ type region is formed in photodiode surface, by photodiode and matrix
Surface is isolated.
10. the integrated technique according to claim 1 for reducing cmos image sensor white pixel, it is characterised in that step
In S05, using shallow-layer ion implanting mode, N+ types floating diffusion region is formed, the leakage as transmission grid.
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| CN105742305A (en) * | 2016-04-07 | 2016-07-06 | 上海华力微电子有限公司 | Method for reducing metal contamination introduced in ion implantation of CMOS image sensor |
| CN105870004A (en) * | 2016-04-07 | 2016-08-17 | 上海华力微电子有限公司 | Method for eliminating shallow trench isolation induced dark current of CMOS image sensor |
| CN106128945A (en) * | 2016-07-18 | 2016-11-16 | 上海集成电路研发中心有限公司 | A kind of ion injection method |
| CN108063146A (en) * | 2017-12-15 | 2018-05-22 | 上海华力微电子有限公司 | The manufacturing method of cmos image sensor |
| CN109065565B (en) * | 2018-09-29 | 2021-03-02 | 德淮半导体有限公司 | Image sensor and forming method thereof |
| CN110444556B (en) * | 2019-08-30 | 2021-12-03 | 上海华力微电子有限公司 | CMOS sensor and method for forming CMOS sensor |
| CN113224098A (en) * | 2021-04-27 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for manufacturing CMOS image sensor |
| CN113611600A (en) * | 2021-07-29 | 2021-11-05 | 上海华力微电子有限公司 | Method for manufacturing semiconductor device |
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| CN102237383A (en) * | 2010-04-23 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Image sensor device and method of fabricating the same |
| CN103077883A (en) * | 2013-01-11 | 2013-05-01 | 陆伟 | Method for repairing surface defect of wafer |
| CN103456749A (en) * | 2012-06-04 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Image device and methods of forming the same |
| CN103489883A (en) * | 2012-06-08 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Image device and methods of forming the same |
| CN103872066A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | Method for reducing white pixels of complementary metal-oxide semiconductor image sensor |
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| CN102237383A (en) * | 2010-04-23 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Image sensor device and method of fabricating the same |
| CN103456749A (en) * | 2012-06-04 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Image device and methods of forming the same |
| CN103489883A (en) * | 2012-06-08 | 2014-01-01 | 台湾积体电路制造股份有限公司 | Image device and methods of forming the same |
| CN103077883A (en) * | 2013-01-11 | 2013-05-01 | 陆伟 | Method for repairing surface defect of wafer |
| CN103872066A (en) * | 2014-03-24 | 2014-06-18 | 上海华力微电子有限公司 | Method for reducing white pixels of complementary metal-oxide semiconductor image sensor |
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