CN105576026B - Semiconductor devices and preparation method thereof - Google Patents
Semiconductor devices and preparation method thereof Download PDFInfo
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- CN105576026B CN105576026B CN201410550472.4A CN201410550472A CN105576026B CN 105576026 B CN105576026 B CN 105576026B CN 201410550472 A CN201410550472 A CN 201410550472A CN 105576026 B CN105576026 B CN 105576026B
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Abstract
The invention discloses a kind of semiconductor devices and preparation method thereof, by in being pre-formed N insert layer in semiconductor substrate, then subsequent semiconductor device fabrication processes are carried out again, since the N insert layer can receive carrier from substrate, to inhibit the substrate current and drain current of semiconductor devices, and then inhibit the hot carrier's effect for influencing device lifetime, and since the N insert layer is located at below the channel region of the semiconductor devices, and not with channel region contacts, therefore it will not influence the doping concentration in semiconductor device channel area, and then device performance will not be impacted.
Description
Technical field
The present invention relates to a kind of technical field of manufacturing semiconductors more particularly to a kind of semiconductor devices and preparation method thereof.
Background technique
With the continuous development of ic manufacturing technology, semiconductor devices shrink to nanoscale, in small size device and
The reduction of the reliability of MOSFET has become serious problem in large scale integrated circuit, wherein is especially sent out with hot carrier
It penetrates maximum to the reliability effect of MOSFET.When grid voltage is greater than drain voltage, thermionic emission can be caused, and work as grid
Voltage can cause hot hole to emit when being less than drain voltage, and thermionic emission and hot hole transmitting can all cause device performance
It degenerates, therefore reduce hot carrier transmitting to become urgent problem to be solved.
Currently, generalling use the following two kinds mode to reduce hot carrier transmitting, a kind of mode is super by setting one
To reduce hot carrier transmitting, in addition the arsenic region of the high concentration in deep low phosphorus region and an an ultra shallow is to optimize drain electrode
A kind of mode be by widening side wall layer, improving LDD concentration and changing rapid thermal anneal process process flow, though these methods
Hot carrier in jection can so be inhibited, but also change device performance simultaneously, therefore, how in the premise for not influencing device performance
It is lower that hot carrier's effect is inhibited to become the direction that those skilled in the art endeavour research.
Summary of the invention
In view of the above problems, the present invention discloses a kind of semiconductor devices and preparation method thereof, is not influencing device
Hot carrier's effect is inhibited under the premise of performance.
To achieve the goals above, the application describes a kind of preparation method of semiconductor devices, wherein including walking as follows
Suddenly：
Semiconductor substrate is provided；
The first energy is used to inject the N-type ion of the first dosage into the semiconductor substrate in the semiconductor substrate
The first N insert layer of interior formation；
Being formed in the surface of the semiconductor substrate has the exposure mask of gate patterns with by the part table of the semiconductor substrate
Face is covered；
Use the second energy injected into the semiconductor substrate N-type ion of the second dosage in the gate patterns just
The 2nd N insert layer is formed in the semiconductor substrate of lower section；
After removing the exposure mask, into the semiconductor substrate, to prepare P type trap zone, the first N is inserted injecting p-type ion
Enter layer the 3rd N insert layer of thinning formation, the 2nd N insert layer forms the since top edge portion is compensated by P-type ion
Four N insert layers；
Wherein, first energy is greater than second energy, and first dosage is less than or equal to second dosage.
The preparation method of above-mentioned semiconductor devices, wherein the value of first energy be 360-450kev, described first
The value of dosage is 8e13-2e14ionscm-2。
The preparation method of above-mentioned semiconductor devices, wherein the value of the second energy be 500-1000kev, described second dose
The value of amount is 2e13-8e13ionscm-2。
The preparation method of above-mentioned semiconductor devices, wherein the 4th N insert layer is located at the ditch of the semiconductor devices
Below road area, and do not contacted with the channel region.
The preparation method of above-mentioned semiconductor devices, wherein the 3rd N insert layer upper surface and the 4th N insertion
Layer following table face contact.
The preparation method of above-mentioned semiconductor devices, wherein the exposure mask is photoresist.
The preparation method of above-mentioned semiconductor devices, wherein the method also includes：
After forming the 4th N insert layer, gate structure is formed in the semiconductor substrate surface, and the gate structure is overlapping
Right above the 4th N insert layer；
Carry out lightly doped technique；
Continue subsequent source-drain electrode preparation process.
The application also describes a kind of semiconductor devices, wherein including：
Semi-conductive substrate；
The first N insert layer being set in the semiconductor substrate；
The 2nd N insert layer being set to above the first N insert layer；
Gate structure on the semiconductor substrate is set, and the gate structure overlaps on the 2nd N insertion
Right above layer.
Above-mentioned semiconductor devices, wherein the step of forming the first N insert layer and the 2nd N insert layer include：
One substrate is provided；
The first energy is used to inject the N-type ion of the first dosage into the substrate in formation original first in the substrate
N insert layer.
Being formed in the surface of the substrate has the exposure mask of gate patterns to be covered the part of the surface of the substrate；
Continue the N-type ion for using the second energy to inject the second dosage into the substrate in the gate patterns just
Former 2nd N insert layer is formed in the substrate of lower section；
After removing the exposure mask, continuing the injecting p-type ion into the substrate, to prepare P type trap zone, former first N is inserted
Enter that layer is thinning to form the first N insert layer, the former 2nd N insert layer since top edge portion is compensated by P-type ion and
The 2nd N insert layer is formed, the substrate is the semiconductor substrate；
Wherein, first energy is greater than second energy, and first dosage is less than or equal to second dosage.
Above-mentioned semiconductor devices, wherein the value of first energy is 360-450kev, and the value of first dosage is
8e13-2e14ions·cm-2。
Above-mentioned semiconductor devices, wherein the value of the second energy is 500-1000kev, and the value of second dosage is
2e13-8e13ions·cm-2。
Above-mentioned semiconductor devices, wherein the exposure mask is photoresist.
Above-mentioned semiconductor devices, wherein the 2nd N insert layer is located at below the channel region of the semiconductor devices,
And it is not contacted with the channel region.
Above-mentioned semiconductor devices, wherein the first N insert layer upper surface and the 2nd N insert layer lower surface connect
Touching.
Foregoing invention is with the following advantages or beneficial effects：
The invention discloses a kind of semiconductor devices and preparation method thereof, by slotting in being pre-formed N in semiconductor substrate
Enter layer, then carry out subsequent gate structure and source-drain electrode preparation process again, since the N insert layer can receive current-carrying from substrate
Son to inhibit the substrate current and drain current of semiconductor devices, and then inhibits the hot carrier for influencing device lifetime
Effect, and since the N insert layer is located at below the channel region of semiconductor devices, and not with channel region contacts, therefore it can't shadow
The doping concentration of channel region is rung, and then device performance will not be impacted.
Specific Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent.Identical label indicates identical part in all the attached drawings.Not can according to than
Example draws attached drawing, it is preferred that emphasis is shows the gist of the present invention.
Fig. 1-9 is the flow diagram of the preparation method of semiconductor devices in the embodiment of the present invention；
Figure 10 is the structural schematic diagram of semiconductor devices in the embodiment of the present invention；
Figure 11 is that the semiconductor devices of prior art preparation is partly led with prepared by method of the invention in the embodiment of the present invention
The drain current of body device and the contrast schematic diagram of substrate current.
Specific embodiment
The present invention is further illustrated with specific embodiment with reference to the accompanying drawing, but not as limit of the invention
It is fixed.
Fig. 1-9 is the flow diagram of the preparation method of semiconductor devices in the embodiment of the present invention, as shown in figs 1-9, this
Embodiment is related to a kind of preparation method of semiconductor devices：
Step S1 provides semi-conductive substrate 100, which can be P type substrate or include traditional device
The substrate of part structure, structure as shown in Figure 1.
Step S2 uses the first energy to inject the N-type ion of the first dosage into semiconductor substrate 100 in the semiconductor
The first N insert layer 111 is formed in substrate 100, in an embodiment of the present invention, the value range of the value of first energy is 360-
450kev (such as 360kev, 400kev, 420kev or 450kev etc.), wherein kev is energy unit：Kilo electron volt, should
The value range of the value of first dosage is 8e13-2e14ionscm-2(such as 8e13ionscm-2、10e13ions·cm-2、
1e14ions·cm-2Or 2e14ionscm-2Deng), the semiconductor substrate 100 is changed due to internal material at this time
And become the semiconductor substrate 101 for having formed the first N insert layer, structure as shown in Figure 2.
Preferably, use the N-type ion of the first energy first dosage of vertical injection into semiconductor substrate 100 in this half
The first N insert layer 111 of a rectangular shape is formed in conductor substrate 100.
Step S3 forms the exposure mask with gate patterns on the surface for having formed the semiconductor substrate 101 of the first N insert layer
112 to be covered the part of the surface of the semiconductor substrate, specifically, the step of forming exposure mask 112 includes：One layer of coating
The surface of the above-mentioned semiconductor substrate 101 for having formed the first N insert layer of photoresist overlay, the layer photoresist through exposure and development after,
The photoresist with gate patterns is formed, it is exposure mask 112 that this, which has the photoresist of gate patterns, in an embodiment of the present invention, should
The unlapped region of exposure mask 112 is the region for being subsequently formed gate structure, structure as shown in Figure 3.
Step S4 continues to inject the into the above-mentioned semiconductor substrate 101 for having formed the first N insert layer using the second energy
The N-type ion of two dosage in the semiconductor substrate 101 for having formed the first N insert layer formed the 2nd N insert layer 113, this
When, which becomes the semiconductor substrate for having formed the 2nd N insert layer since internal material changes
102, structure as shown in Figure 4.
Wherein, the value of second energy is less than the value of above-mentioned first energy, and the value of second dosage is greater than or equal to above-mentioned
The value of first dosage.
In an embodiment of the present invention, the value range of the value of second energy be 500-1000kev (such as 500kev,
600kev, 800kev or 1000kev etc.), the value range of the value of second dosage is 2e13-8e13ionscm-2(such as
2e13ions·cm-2、4e13ions·cm-2、6e13ions·cm-2Or 8e13ionscm-2Deng).
Preferably, the semiconductor for having formed the first N insert layer of exposure mask 112 is covered with to above-mentioned surface using the second energy
The N-type ion of the second dosage of vertical injection is in shape in the semiconductor substrate 101 for having formed the first N insert layer in substrate 101
At the 2nd N insert layer 113.
Step S5 is covered in the above-mentioned semiconductor substrate 102 for having formed the 2nd N insert layer using wet clean process removal
The exposure mask 112 on surface, structure as shown in Figure 5.
Step S6 is continued up and is stated in the semiconductor substrate 102 for having formed the 2nd N insert layer injecting p-type ion to form P
Type well region (not shown), due to the compensating action of the P-type ion, thinning the 3rd N that becomes of above-mentioned first N insert layer 111 is inserted
Enter layer 114, the top edge portion of above-mentioned 2nd N insert layer 112 makes the 2nd N insert layer 112 due to being compensated by P-type ion
Become the 4th N insert layer 115 of massif shape, at this point, having been injected into the semiconductor substrate of P-type ion becomes semiconductor substrate 104,
Structure as shown in FIG. 6.
In an embodiment of the present invention, and the lower section positioned at the channel region being subsequently formed of the 4th N insert layer 115, and
It is not contacted with the channel region.
In an embodiment of the present invention, under the upper surface and the 4th N insert layer 115 of above-mentioned 3rd N insert layer 114
Surface contact.
Step S7 forms gate structure 116, and the grid in the surface of the above-mentioned semiconductor substrate 103 for having been injected into P-type ion
Pole structure 116 is located at the surface of above-mentioned 4th N insert layer 115, the gate structure 116 include grid, gate oxide (in figure not
Show), the technique for forming the gate structure is well known in the art, and it will not be described here, it is preferred that the grid is polysilicon gate
(Poly), the material of the gate oxide is silica, structure as shown in Figure 7.
Step S8 continues lightly doped technique with light in being formed in the above-mentioned semiconductor substrate 103 for having been injected into p-well ion
Doped region 117, structure shown in Fig. 8.
Step S9 forms a side wall 118 and covers above-mentioned 116 side wall of gate structure, and the technique for forming the side wall 117 is ability
Well known to domain, it will not be described here, it is preferred that the material of the side wall is silicon nitride or silica.
Step S10 continues source-drain electrode ion implanting in the above-mentioned semiconductor substrate 104 for having carried out lightly doped technique
Interior formation source-drain electrode 119, structure as shown in Figure 10.
Figure 11 is that the semiconductor devices of prior art preparation is partly led with prepared by method of the invention in the embodiment of the present invention
The drain current of body device and the contrast schematic diagram of substrate current, as shown in figure 11, wherein X-axis indicates the electricity of unit length
Stream, unit are A/um (every micron of ampere), and Y-axis indicates voltage, and unit is V (volt), and curve 1 is expressed as utilizing traditional technology system
The drain current for the semiconductor devices made, curve 2 are expressed as the drain current of the semiconductor devices using the technology of the present invention manufacture,
Curve 3 is the substrate current of the semiconductor devices manufactured using traditional technology, and curve 4 is partly to be led using what the technology of the present invention manufactured
The substrate current of body device.
And in one embodiment of the invention, using the semiconductor devices of method preparation of the invention and using traditional skill
Substrate/drain current of the semiconductor devices of art preparation is as shown in the table：
| Device preparation method | Substrate/drain current |
| The semiconductor devices of traditional technology preparation | 2.429e-01 |
| Semiconductor devices prepared by the present invention | 4.032e-02 |
It can obviously obtain method of the invention in inhibiting hot carrier's effect by Figure 11 and above table
Advantage, in the identical situation of voltage, the drain current of semiconductor devices prepared by the present invention prepared than traditional technology half
The value of the drain current of conductor device is small, and the value of the substrate current of semiconductor devices prepared by the present invention is also prepared than traditional technology
Semiconductor devices substrate current value it is small.
Figure 10 is the structural schematic diagram of semiconductor devices in the embodiment of the present invention, and as shown in Figure 10, the present embodiment is related to one
Kind semiconductor devices, including：
Semi-conductive substrate 104；And it is set to the first N insert layer 114 in the semiconductor substrate 104；And it is set to
A the 2nd N insert layer 115 for massif shape in the semiconductor substrate 104 and above the first N insert layer；Further include
Gate structure 116 on semiconductor substrate 104 is set, and gate structure 116 overlaps on the 2nd N insert layer of massif shape
Right above 115.
In an embodiment of the present invention, above-mentioned semiconductor device further includes 117 ' of lightly doped region, the above-mentioned grid knot of covering
The side wall 118 and source-drain electrode 119 of 116 side wall of structure.
In an embodiment of the present invention, the step of forming the first N insert layer 114 and the 2nd N insert layer 115 include：
One substrate is provided；
The first energy is used to inject the N-type ion of the first dosage into above-mentioned substrate in formation original first in above-mentioned substrate
N insert layer.
Being formed in the surface of the above-mentioned substrate for having formed former first N insert layer has the exposure mask of gate patterns with by the substrate
Part of the surface covered；
Continue to use the second energy injected into the substrate for having formed former first N insert layer the N-type ion of the second dosage with
In the former 2nd N insert layer of formation in the substrate of the underface of above-mentioned gate patterns；
After removing exposure mask, continue into the substrate for having formed former first N insert layer injecting p-type ion to prepare P type trap zone,
Former first N insert layer the first N insert layer 114 of thinning formation, the top edge portion of former 2nd N insert layer is due to by P-type ion
It compensates and former 2nd N insert layer is made to become the 2nd N insert layer 115 of massif shape, and formed the substrate of the 2nd N insert layer
Form semiconductor substrate 104；
And above-mentioned first energy is greater than the second energy, above-mentioned first dosage is less than or equal to the second dosage.
Preferably, the value range of the value of first energy is 360-450kev (such as 360kev, 400kev, 420kev
Or 450kev etc.), the value range of the value of first dosage is 8e13-2e14ionscm-2(such as 8e13ionscm-2、10e13ions·cm-2、1e14ions·cm-2Or 2e14ionscm-2Deng)；The value range of the value of second energy
For 500-1000kev (such as 500kev, 600kev, 800kev or 1000kev etc.), the value range of the value of first dosage
For 2e13-8e13ionscm-2(such as 2e13ionscm-2、4e13ions·cm-2、6e13ions·cm-2Or
8e13ions·cm-2Deng).
Above-mentioned 2nd N insert layer 115 is located at below the channel region (not shown) of above-mentioned semiconductor device, and with the ditch
Road area does not contact, and above-mentioned first N insert layer, 114 upper surface and 115 following table face contact of the 2nd N insert layer.
It is not difficult to find that the present embodiment is structure corresponding with the embodiment of the preparation method of above-mentioned semiconductor device implementation
Example, present embodiment can the embodiment of preparation method of above-mentioned semiconductor device work in coordination implementation.Above-mentioned semiconductor device
The relevant technical details mentioned in the embodiment of preparation method are still effective in the present embodiment, in order to reduce repetition, here
It repeats no more.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in the preparation of above-mentioned semiconductor device
In the embodiment of method.
In conclusion the invention discloses a kind of semiconductor devices and preparation method thereof, by pre- in semiconductor substrate
It is initially formed N insert layer, then carries out the preparation process of subsequent semiconductor devices again, since the N insert layer can connect from substrate
Carrier is received, to inhibit the substrate current and drain current of semiconductor devices, and then the heat for influencing device lifetime is inhibited to carry
Flow sub- effect, and since the N insert layer is located at below the channel region of the semiconductor devices, and not with channel region contacts, therefore simultaneously
It will not influence the doping concentration in semiconductor device channel area, and then device performance will not be impacted.
It should be appreciated by those skilled in the art that those skilled in the art are combining the prior art and above-described embodiment can be with
Realize the change case, this will not be repeated here.Such change case does not affect the essence of the present invention, not superfluous herein
It states.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, devices and structures not described in detail herein should be understood as gives reality with the common mode in this field
It applies；Anyone skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this is not affected the essence of the present invention.Therefore, anything that does not depart from the technical scheme of the invention, foundation
Technical spirit of the invention any simple modifications, equivalents, and modifications made to the above embodiment, still fall within the present invention
In the range of technical solution protection.
Claims (13)
1. a kind of preparation method of semiconductor devices, which is characterized in that include the following steps：
Semiconductor substrate is provided；
The first energy is used to inject the N-type ion of the first dosage into the semiconductor substrate in shape in the semiconductor substrate
At the first N insert layer；
Being formed in the surface of the semiconductor substrate has the exposure mask of gate patterns to give the part of the surface of the semiconductor substrate
With covering；
The second energy is used to inject the N-type ion of the second dosage into the semiconductor substrate immediately below the gate patterns
Semiconductor substrate in formed the 2nd N insert layer；
After removing the exposure mask, into the semiconductor substrate, injecting p-type ion is to prepare P type trap zone, the first N insert layer
The 3rd N insert layer of thinning formation, the 2nd N insert layer form the 4th N and insert since top edge portion is compensated by P-type ion
Enter layer；
Wherein, first energy is greater than second energy, and first dosage is less than or equal to second dosage.
2. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the value of first energy is 360-
450kev, the value of first dosage are 8e13-2e14ionscm-2。
3. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the value of the second energy is 500-
1000kev, the value of second dosage are 2e13-8e13ionscm-2。
4. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the 4th N insert layer is located at institute
Below the channel region for stating semiconductor devices, and do not contacted with the channel region.
5. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the 3rd N insert layer upper surface
With the 4th N insert layer following table face contact.
6. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the exposure mask is photoresist.
7. the preparation method of semiconductor devices as described in claim 1, which is characterized in that the method also includes：
After forming the 4th N insert layer, gate structure is formed in the semiconductor substrate surface, and the gate structure overlaps on institute
It states right above the 4th N insert layer；
Carry out lightly doped technique；
Continue subsequent source-drain electrode preparation process.
8. a kind of semiconductor devices, which is characterized in that including：
Semi-conductive substrate；
The first N insert layer being set in the semiconductor substrate；
The 2nd N insert layer being set to above the first N insert layer；
Gate structure on the semiconductor substrate is set, and the gate structure is overlapping on the 2nd N insert layer just
Top；
The step of forming the first N insert layer and the 2nd N insert layer include：
One substrate is provided；
The first energy is used to inject the N-type ion of the first dosage into the substrate with slotting in forming the first N of original in the substrate
Enter layer；
Being formed in the surface of the substrate has the exposure mask of gate patterns to be covered the part of the surface of the substrate；
The N-type ion for continuing that the second energy is used to inject the second dosage into the substrate is in the underface of the gate patterns
Substrate in form former 2nd N insert layer；
After removing the exposure mask, continue into the substrate injecting p-type ion to prepare P type trap zone, the former first N insert layer
Thinning to form the first N insert layer, the former 2nd N insert layer is formed since top edge portion is compensated by P-type ion
2nd N insert layer, the substrate are the semiconductor substrate；
Wherein, first energy is greater than second energy, and first dosage is less than or equal to second dosage.
9. semiconductor devices as claimed in claim 8, which is characterized in that the value of first energy is 360-450kev, institute
The value for stating the first dosage is 8e13-2e14ionscm-2。
10. the preparation method of semiconductor devices as claimed in claim 8, which is characterized in that the value of the second energy is 500-
1000kev, the value of second dosage are 2e13-8e13ionscm-2。
11. the preparation method of semiconductor devices as claimed in claim 8, which is characterized in that the exposure mask is photoresist.
12. the preparation method of semiconductor devices as claimed in claim 8, which is characterized in that the 2nd N insert layer is located at institute
Below the channel region for stating semiconductor devices, and do not contacted with the channel region.
13. the preparation method of semiconductor devices as claimed in claim 8, which is characterized in that the first N insert layer upper surface
With the 2nd N insert layer following table face contact.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6501131B1 (en) * | 1999-07-22 | 2002-12-31 | International Business Machines Corporation | Transistors having independently adjustable parameters |
| CN102751193A (en) * | 2011-04-20 | 2012-10-24 | 格罗方德半导体公司 | MOS semiconductor device and methods for its fabrication |
| CN103187273A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and manufacturing method thereof |
-
2014
- 2014-10-16 CN CN201410550472.4A patent/CN105576026B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6501131B1 (en) * | 1999-07-22 | 2002-12-31 | International Business Machines Corporation | Transistors having independently adjustable parameters |
| CN102751193A (en) * | 2011-04-20 | 2012-10-24 | 格罗方德半导体公司 | MOS semiconductor device and methods for its fabrication |
| CN103187273A (en) * | 2011-12-31 | 2013-07-03 | 中芯国际集成电路制造(上海)有限公司 | Mos transistor and manufacturing method thereof |
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