CN105183930A - Methods and devices for setting and using hardware timer - Google Patents

Abstract

The invention discloses methods and devices for setting and using a hardware timer, and belongs to the field of digital circuits. The method for setting the hardware timer comprises the following steps: S101, determining timing time, and setting an initial value of a counter register of the hardware timer and a value of a compare register; S102, starting up the hardware timer, starting timing, restoring the counter register to the initial value when the timing time is reached, and restarting timing; and S103, every time the timing time is reached, executing a timer interrupt processing function at the same time in order to realize self-adding or self-subtraction of a first counting variable F1. Compared with the prior art, the method has the advantages that the use efficiency of the hardware timer can be increased; the parallel usability of the hardware timer is high; the application range of the hardware timer is widened; and the power consumption of a system is lowered.

Description

Arrange and use method and the device of hardware timer

Technical field

The present invention relates to digital circuit field, refer to a kind of method and the device that arrange and use hardware timer especially.

Background technology

For the design of existing digital circuitry, CPU (CentralProcessingUnit, central processing unit), MCU (MicrocontrollerUnit, micro-control unit), DSP (DigitalSignalProcess, i.e. Digital Signal Processing) chip, FPGA (Field-ProgrammableGateArray, field programmable gate array), CPLD (ComplexProgrammableLogicDevice, CPLD) etc. right and wrong primary processor usually, and in these primary processors, except central processing unit core, also can integrated a lot of conventional hardware module, and hardware timer is due to the importance of its status, have integrated in each processor, an integrated hardware timer at least, integrated four to five hardware timers at most.

Hardware timer is as the term suggests be used between timing, due to its accurate timing, easy to use, is widely used in software programming, and is an indispensable part.

Hardware timer inside is all provided with one or more counter register and one or more comparand register, and hardware timer all can have a work clock, and its frequency counts H; If timing is T, before timing starts, the value of comparand register is set to N, the initial value of counter register is set to COUNT; After timing starts, each clock, the capital of counter register changes a value, or adds 1, or subtracts 1.When the instantaneous value COUNT_REAL of counter register is equal with the value N of comparand register time, represent that timing arrives, now hardware timer will arrange an interrupt flag, when hardware timer interrupt function is enabled time, will trigger an interruption.This interrupt flag is stored in certain specific register, and by judging whether have interrupt flag to judge in this register, whether timing reaches application program, thus carries out follow-up work, removing interrupt flag after follow-up work completes.When next clock arrives, the value in counter register automatically returns to initial value COUNT, for timing next time is prepared.

Prior art to the use of device when determining hardware as depicted in figs. 1 and 2; In Fig. 1, when hardware timer timing, application software does not perform any action, represents that application software carries out follow-up work after waiting for a period of time again; In Fig. 2 when hardware timer timing, application software carries out associative operation, until carry out other work again after timing.There are the following problems for prior art:

One, not high to the utilization ratio of hardware timer: a hardware timer is only used in an application scenarios, and the quantity of the hardware timer of primary processor inside is conditional, in time having plurality of application scenes, the problem that hardware timer is not enough will be caused;

Two, parallel usability is poor: some hardware timers, if used in some places, so now this hardware timer just can not be used in other place again; Especially, in multi-process, multi-thread programming, it is more outstanding that this problem shows.

Three, range of application is narrow: the application of hardware timer is just confined to timing, counting functionally, without any expanded application.

Summary of the invention

The invention provides a kind of method and the device that arrange and use hardware timer, the method can improve the service efficiency to hardware timer, make the parallel usability of hardware timer good, and widened the scope of application of hardware timer, reduce the power consumption of system.

For solving the problems of the technologies described above, the invention provides technical scheme as follows:

A method for hardware timer is set, comprises:

Step S101: determine timing, sets the initial value of the counter register of described hardware timer and the value of comparand register;

Step S102: start described hardware timer, start timing, if timing arrives, counter register returns to initial value, restarts timing;

Step S103: each timing then, performs timer interruption process function simultaneously, makes the first counting variable F1 from adding or certainly subtracting.

Use a method for hardware timer, comprising:

Step S501: when bringing into use described hardware timer, obtains described hardware timer net cycle time now, is designated as Time_total_1;

Step S502: after bringing into use described hardware timer, reads the current net cycle time of described hardware timer in real time, is designated as Time_total_2;

Step S503: judge | whether Time_total_1-Time_total_2| equals setting-up time, if so, terminates, otherwise, go to step S502.

A device for hardware timer is set, comprises:

Setting module, for determining timing, sets the initial value of the counter register of described hardware timer and the value of comparand register;

Time block, for starting described hardware timer, start timing, if timing arrives, counter register returns to initial value, restarts timing;

Interrupt module, for each timing then, performs timer interruption process function simultaneously, makes the first counting variable F1 from adding or certainly subtracting.

Use a device for hardware timer, comprising:

First acquisition module, for when bringing into use described hardware timer, obtaining described hardware timer net cycle time now, being designated as Time_total_1;

Second acquisition module, for after bringing into use described hardware timer, reads the current net cycle time of described hardware timer in real time, is designated as Time_total_2;

Second judge module, for judging | whether Time_total_1-Time_total_2| equals setting-up time, if so, terminates, otherwise, go to the second acquisition module.

The present invention has following beneficial effect:

Of the present inventionly arrange in the method for hardware timer, first set the timing of hardware timer, then start hardware timer, start timing, after timing arrives, automatically restart timing, so circulate execution; And after each timing arrives, all perform a timer interruption process function, make the first counting variable F1 from adding or certainly subtracting.Like this, the number of times of hardware timer circulation is counted by the first counting variable F1, the current net cycle time Time_total of hardware timer can be calculated by parameters, thus provide timing function for each application program and wherein each application scenarios.

Compared with prior art, the method arranging hardware timer of the present invention only needs a hardware timer at circulation timing, each application program is when needs completion timing operates, the net cycle time of hardware timer just can be obtained when fixed cycle operator starts, be designated as Time_total_1, then associative operation is performed, certainly this operation can not exist, the current net cycle time of hardware timer is obtained needing the place judging fixed cycle operator, be designated as Time_total_2, both differences can calculate the time of fixed cycle operator.So, a hardware timer can be used in multiple application scenarios, improves the service efficiency to hardware timer; And when this hardware timer is used in some places, also can be used in other place, parallel usability is good again.

In addition, because this hardware timer is always at continual circulation timing, and by the first counting variable F1 computation cycles number of times, if equipment or system have been set up an enlightenment time, so just with the time of enlightenment for basic point, the current time can be calculated by Time_total.Therefore this hardware timer can be used as real-time clock, widen the scope of application of hardware timer.

Moreover because a hardware timer can meet the needs of application, remaining hardware timer does not just need to re-use, and closes these hardware timers, the power consumption of system will be reduced to a certain extent.

Therefore the method arranging hardware timer of the present invention can improve the service efficiency to hardware timer, make the parallel usability of hardware timer good, and widened the scope of application of hardware timer, reduce the power consumption of system.

Accompanying drawing explanation

Fig. 1 is the method flow diagram one using hardware timer in prior art;

Fig. 2 is the method flow diagram two using hardware timer in prior art;

Fig. 3 is the method flow diagram one arranging hardware timer of the present invention;

Fig. 4 is the method flow diagram two arranging hardware timer of the present invention;

Fig. 5 is the method flow diagram of use hardware timer of the present invention;

Fig. 6 is the structure drawing of device one arranging hardware timer of the present invention;

Fig. 7 is the structure drawing of device two arranging hardware timer of the present invention;

Fig. 8 is the structure drawing of device of use hardware timer of the present invention.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearly, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

The invention provides a kind of method that hardware timer is set, as shown in Figure 3, comprising:

Step S101: determine timing, the initial value of counter register of setting hardware timer and the value of comparand register;

Timing is set by the initial value COUNT of counter register and the value N of comparand register that set hardware timer; Now needing, timing is set enable to interruption;

Step S102: start hardware timer, start timing, if timing arrives, counter register returns to initial value, restarts timing;

After having set, start hardware timer, start timing, now the instantaneous value COUNT_REAL of counter register is from adding or certainly subtracting, and hardware timer constantly can compare COUNT_REAL and N, when COUNT_REAL and N is equal, timing arrives, and now hardware timer arranges an interrupt flag, when next clock arrives, value in counter register automatically returns to initial value COUNT, restarts timing; Like this, hardware timer always at constantly circulation timing, can not be able to stop;

Step S103: each timing then, performs timer interruption process function simultaneously, makes the first counting variable F1 from adding or certainly subtracting;

By reading interrupt flag, interrupt processing function judges whether timing is to arriving, like this, if timer interruption function is enabled, timer interruption process function can be automatically triggered execution.

Of the present inventionly arrange in the method for hardware timer, first set the timing of hardware timer, then start hardware timer, start timing, after timing arrives, automatically restart timing, so circulate execution; And after each timing arrives, all perform a timer interruption process function, make the first counting variable F1 from adding or certainly subtracting.Like this, the number of times counting hardware timer circulation by the first counting variable F1, can calculate the net cycle time Time_total of hardware timer by parameters, thus provides timing function for each application program and wherein each application scenarios.

Compared with prior art, the method arranging hardware timer of the present invention only needs a hardware timer at circulation timing, each application program is when needs completion timing operates, the net cycle time of hardware timer just can be obtained when fixed cycle operator starts, be designated as Time_total_1, then associative operation is performed, certainly this operation can not exist, the current net cycle time of hardware timer is obtained needing the place judging fixed cycle operator, be designated as Time_total_2, both differences can calculate the time of fixed cycle operator.So, a hardware timer can be used in multiple application scenarios, improves the service efficiency to hardware timer; And when this hardware timer is used in some places, also can be used in other place, parallel usability is good again.

In addition, because this hardware timer is always at continual circulation timing, and by the first counting variable F1 computation cycles number of times, if equipment or system have been set up an enlightenment time, so just with the time of enlightenment for basic point, the current time can be calculated by Time_total.Therefore this hardware timer can be used as real-time clock, widen the scope of application of hardware timer.

Moreover because a hardware timer can meet the needs of application, remaining hardware timer does not just need to re-use, and closes these hardware timers, the power consumption of system will be reduced to a certain extent.

Therefore the method arranging hardware timer of the present invention can improve the service efficiency to hardware timer, make the parallel usability of hardware timer good, and widened the scope of application of hardware timer, reduce the power consumption of system.

After above-mentioned hardware timer is started working, its net cycle time can be obtained by following formula:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-{F1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of counter register, and COUNT is the initial value of counter register, and N is the value of comparand register, and H is the frequency of the work clock of hardware timer, f1 ₀it is the initial value of the first counting variable F1.

Concrete example is as follows:

Suppose that the working clock frequency of hardware timer is H, unit hertz; So the time of each clock is exactly 1/Hs, often carry out a clock, the counter register of hardware timer inside will change a value and (or increase by 1, or reducing 1, the hardware timer on different processor has certain difference, the function only having growth had, the function only having minimizing had, have both have concurrently, control by arranging control register), the time that the value namely in counter register often changes one is exactly 1/Hs.

(clock is namely often carried out for down counter, the counter register of hardware timer inside just reduces 1), suppose that in the comparand register in hardware timer, set numerical value is N, initial value in counter register is set to COUNT (wherein, COUNT>N), the instantaneous value of counter register be COUNT_REAL (wherein, COUNT>=COUNT_REAL>=N), the difference of the instantaneous value of the counter register of reading and the initial value of counter register is D=COUNT-COUNT_REAL.

If the first counting variable F1 is 32bit, so-called first counting variable F1 is exactly after timer is started working, and whenever COUNT_REAL=N time, F1 adds 1, until be added to maximal value.

After supposing that hardware timer is started working, total time is Time_total, and its computing formula is:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-{F1}_0|;$

Once, i.e. T=10ms, interrupting 100 times is exactly 1s in setting hardware timer 10ms circulation (interruption).If one-level count value F1 is a count value of a 32bit, so F1 meter full after numerical value equal 2^32-1=4294967295, (2^32 – 1)/100 times/60 seconds/60 points/24 hours=497.1 days, that is, if often interrupt an one-level count value F1 from adding 1, the continuous non-stop run of hardware timer 497.1 days, F1 is from 0 full number.

Do not safeguard, so a hardware timer can use as real-time clock completely due to the unlikely non-stop run nearly 500 days continuously of equipment.And now the work clock of hardware timer can reach the rank of MHz, that is during the using as real-time clock of hardware timer, its precision can reach nanosecond, very accurately.And existing real-time clock can only be accurate to second.

Improve as the one arranging the method for hardware timer of the present invention, as shown in Figure 4, also comprise after step S103:

Step S104: judge whether F1 reaches setting value, if so, then makes the second counting variable F2 from adding or certainly subtracting, and makes F1 become its initial value again.

When the first counting variable F1 counts completely, the full number of times of meter that the second counting variable F2 counts the first counting variable F1 can be set, extend the working time of hardware timer.

Therefore the method arranging hardware timer of the present invention makes the working time of hardware timer extend further.

After above-mentioned hardware timer is started working, its net cycle time can be obtained by following formula:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-{F1}_0|+T|F2-{F2}_0||{f1}_s-{f1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of counter register, and COUNT is the initial value of counter register, and N is the value of comparand register, and H is the frequency of the work clock of hardware timer, f1 ₀be the initial value of the first counting variable F1, f2 ₀be the initial value of the second counting variable F2, f1 _sit is the setting value of the first counting variable F1.

If the second counting variable F2 is 32bit, when F1 is added to setting value (getting maximal value herein as setting value) time, F2 adds 1, and simultaneously F1 gets back to initial value (getting 0 herein as initial value) and again counts.

Mention the first counting variable F1 above and can make the continuous non-stop run of hardware timer 497.1 days, add the second counting variable F2 even the 3rd counting variable F3, the working time indefinite extension of hardware timer can be made in theory.

On the other hand, the present invention puies forward a kind of method using hardware timer, (carries out other relevant treatment in figure can not exist) as shown in Figure 5, comprising:

Step S501: when bringing into use hardware timer, obtains hardware timer net cycle time now, is designated as Time_total_1;

When application software needs fixed cycle operator, such as timed wait a period of time as shown in Figure 1, or as shown in Figure 2 within a period of time, perform some action, when bringing into use hardware timer, read parameters, calculate hardware timer net cycle time now, be designated as Time_total_1;

Step S502: after bringing into use hardware timer, reads the current net cycle time of hardware timer in real time, is designated as Time_total_2;

Step S503: judge | whether Time_total_1-Time_total_2| equals setting-up time, if, then terminate (end be this use procedure, instead of the timing process of above-mentioned timer, timer is always in timing), otherwise, carry out other relevant treatment and go to step S502 (carrying out other relevant treatment not essential).

Compared with prior art, the method of use hardware timer of the present invention only needs a hardware timer at circulation timing, each application program is when needs completion timing operates, the net cycle time of hardware timer just can be obtained when fixed cycle operator starts, be designated as Time_total_1, then associative operation is performed, certainly this operation can not exist, the current net cycle time of hardware timer is obtained needing the place judging fixed cycle operator, be designated as Time_total_2, both differences can calculate the time of fixed cycle operator.So, a hardware timer can be used in multiple application scenarios, improves the service efficiency to hardware timer; And when this hardware timer is used in some places, also can be used in other place, parallel usability is good again.

In addition, because this hardware timer is always at continual circulation timing, and by the first counting variable F1 computation cycles number of times, if equipment or system have been set up an enlightenment time, so just with the time of enlightenment for basic point, the current time can be calculated by Time_total.Therefore this hardware timer can be used as real-time clock, widen the scope of application of hardware timer.

Moreover because a hardware timer can meet the needs of application, remaining hardware timer does not just need to re-use, and closes these hardware timers, the power consumption of system will be reduced to a certain extent.

Therefore the method for use hardware timer of the present invention can improve the service efficiency to hardware timer, make the parallel usability of hardware timer good, and widened the scope of application of hardware timer, reduce the power consumption of system.

Corresponding with the above-mentioned method arranging hardware timer, the present invention also provides a kind of device arranging hardware timer, as shown in Figure 6, comprising:

Setting module 11, for determining timing, the initial value of counter register of setting hardware timer and the value of comparand register;

Time block 12, for starting hardware timer, start timing, if timing arrives, counter register returns to initial value, restarts timing;

Interrupt module 13, for each timing then, performs timer interruption process function simultaneously, makes the first counting variable F1 from adding or certainly subtracting.

Corresponding with the above-mentioned method arranging hardware timer, the device arranging hardware timer of the present invention can improve the service efficiency to hardware timer, make the parallel usability of hardware timer good, and widened the scope of application of hardware timer, reduce the power consumption of system.

After above-mentioned hardware timer is started working, its net cycle time is:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-{F1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of counter register, and COUNT is the initial value of counter register, and N is the value of comparand register, and H is the frequency of the work clock of hardware timer, f1 ₀it is the initial value of the first counting variable F1.

Improve as the one arranging the device of hardware timer of the present invention, as shown in Figure 7, also comprise after interrupt module 13:

First judge module 14, for judging whether F1 reaches setting value, if so, then making the second counting variable F2 from adding or certainly subtracting, and making F1 become its initial value again.

Corresponding with the above-mentioned method arranging hardware timer, the device arranging hardware timer of the present invention makes the working time of hardware timer extend further.

After above-mentioned hardware timer is started working, its net cycle time is:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-{F1}_0|+T|F2-{F2}_0||{f1}_s-{f1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of counter register, and COUNT is the initial value of counter register, and N is the value of comparand register, and H is the frequency of the work clock of hardware timer, f1 ₀be the initial value of the first counting variable F1, f2 ₀be the initial value of the second counting variable F2, f1 _sit is the setting value of the first counting variable F1.

Corresponding with the method for above-mentioned use hardware timer, the present invention also provides a kind of device using hardware timer, as shown in Figure 8, comprising:

First acquisition module 51, for when bringing into use hardware timer, obtaining hardware timer net cycle time now, being designated as Time_total_1;

Second acquisition module 52, for after bringing into use hardware timer, reads the current net cycle time of hardware timer in real time, is designated as Time_total_2;

Second judge module 53, for judging | whether Time_total_1-Time_total_2| equals setting-up time, if so, terminates, otherwise, go to the second acquisition module 52.

Corresponding with the method for above-mentioned use hardware timer, the method of use hardware timer of the present invention can improve the service efficiency to hardware timer, make the parallel usability of hardware timer good, and widened the scope of application of hardware timer, reduce the power consumption of system.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the prerequisite not departing from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (10)

1. a method for hardware timer is set, it is characterized in that, comprising:

Step S101: determine timing, sets the initial value of the counter register of described hardware timer and the value of comparand register;

Step S102: start described hardware timer, start timing, if timing arrives, counter register returns to initial value, restarts timing;

Step S103: each timing then, performs timer interruption process function simultaneously, makes the first counting variable F1 from adding or certainly subtracting.

2. the method arranging hardware timer according to claim 1, is characterized in that, after described hardware timer is started working, its net cycle time is:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-f{1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of the counter register of hardware timer, and COUNT is the initial value of the counter register of hardware timer, and N is the value of the comparand register of hardware timer, and H is the frequency of the work clock of hardware timer, f1 ₀it is the initial value of the first counting variable F1.

3. the method arranging hardware timer according to claim 1, is characterized in that, also comprises after described step S103:

Step S104: judge whether F1 reaches setting value, if so, then makes the second counting variable F2 from adding or certainly subtracting, and makes F1 become its initial value again.

4. the method arranging hardware timer according to claim 3, is characterized in that, after described hardware timer is started working, its net cycle time is:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-f{1}_0|+T|F2-f{2}_0||f{1}_s-f{1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of the counter register of hardware timer, and COUNT is the initial value of the counter register of hardware timer, and N is the value of the comparand register of hardware timer, and H is the frequency of the work clock of hardware timer, f1 ₀be the initial value of the first counting variable F1, f2 ₀be the initial value of the second counting variable F2, f1 _sit is the setting value of the first counting variable F1.

5. use a method for the hardware timer in claim 1-4 described in arbitrary claim, it is characterized in that, comprising:

Step S501: when bringing into use described hardware timer, obtains described hardware timer net cycle time now, is designated as Time_total_1;

Step S502: after bringing into use described hardware timer, reads the current net cycle time of described hardware timer in real time, is designated as Time_total_2;

Step S503: judge | whether Time_total_1-Time_total_2| equals setting-up time, if so, terminates, otherwise, go to step S502.

6. a device for hardware timer is set, it is characterized in that, comprising:

Setting module, for determining timing, sets the initial value of the counter register of described hardware timer and the value of comparand register;

Time block, for starting described hardware timer, start timing, if timing arrives, counter register returns to initial value, restarts timing;

Interrupt module, for each timing then, performs timer interruption process function simultaneously, makes the first counting variable F1 from adding or certainly subtracting.

7. the device arranging hardware timer according to claim 6, is characterized in that, after described hardware timer is started working, its net cycle time is:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-f{1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of the counter register of hardware timer, and COUNT is the initial value of the counter register of hardware timer, and N is the value of the comparand register of hardware timer, and H is the frequency of the work clock of hardware timer, f1 ₀it is the initial value of the first counting variable F1.

8. the device arranging hardware timer according to claim 6, is characterized in that, also comprises after described interrupt module:

First judge module, for judging whether F1 reaches setting value, if so, then making the second counting variable F2 from adding or certainly subtracting, and making F1 become its initial value again.

9. the device arranging hardware timer according to claim 8, is characterized in that, after described hardware timer is started working, its net cycle time is:

$\mathrm{Time}\_\mathrm{total}=\frac{|\mathrm{COUNT}\_\mathrm{REAL}-\mathrm{COUNT}|}{H}+T|F1-f{1}_0|+T|F2-f{2}_0||f{1}_s-f{1}_0|;$

Wherein, T is timing, cOUNT_REAL is the instantaneous value of the counter register of hardware timer, and COUNT is the initial value of the counter register of hardware timer, and N is the value of the comparand register of hardware timer, and H is the frequency of the work clock of hardware timer, f1 ₀be the initial value of the first counting variable F1, f2 ₀be the initial value of the second counting variable F2, f1 _sit is the setting value of the first counting variable F1.

10. use a device for the hardware timer described in the arbitrary claim of claim 6-9, it is characterized in that, comprising:

First acquisition module, for when bringing into use described hardware timer, obtaining described hardware timer net cycle time now, being designated as Time_total_1;

Second acquisition module, for after bringing into use described hardware timer, reads the current net cycle time of described hardware timer in real time, is designated as Time_total_2;

Second judge module, for judging | whether Time_total_1-Time_total_2| equals setting-up time, if so, terminates, otherwise, go to the second acquisition module.