CN101089823A - Computer watchdog device and its working method - Google Patents
Computer watchdog device and its working method Download PDFInfo
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- CN101089823A CN101089823A CN200610061147.7A CN200610061147A CN101089823A CN 101089823 A CN101089823 A CN 101089823A CN 200610061147 A CN200610061147 A CN 200610061147A CN 101089823 A CN101089823 A CN 101089823A
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Abstract
A watch dog device of computer is prepared as generating clock overflow signal by the first stage of watchdog circuit and sending said signal to he second stage of watchdog circuit and interruption-generating circuit, generating interruption request signal being sent to central processor by interruption-generating circuit when overflow signal is received, simultaneously starting up counting by the second stage of watchdog circuit and generating reset signal to reset central processor if counting value of two said watchdog circuits are not reset by central processor when counting is up to assigned value.
Description
[technical field]
The present invention relates to a kind of computing machine, relate in particular to a kind of a plurality of computer watchdog circuit arrangement and method of work thereof.
[background technology]
Along with science and technology development, computing machine has been widely used in people's routine work, study, various fields in life, becomes one of indispensable instrument of modern humans society.
Computer watchdog device, be a kind of based on the counter principle, be used to improve the device of computer reliability.Counter is counted a clock source, and the at the appointed time interior of CPU cycle sends the order of counting again to counter, and counter does not reach designated value forever.When accident appearred in computing machine, central processing unit did not send counting order again to counter, when then rolling counters forward is to designated value, sends the clock spill over, causes central processing unit to reset, restart computing machine, avoids computing machine to be in unexpected state always.
Present computer watchdog device comprises central processing unit and one-level watchdog circuit, central processing unit is provided with count value for the one-level watchdog circuit, the periodic at the appointed time interior order of counting again that described one-level watchdog circuit is sent, when central processing unit does not send counting order again to the one-level watchdog circuit, when then the one-level watchdog circuit count down to designated value, send the clock spill over, being transferred to central processing unit resets, cause central processing unit to reset, restart the computer, avoid computing machine to be in unexpected state always.
Yet present existing computer system is supported multitask mostly, is worked in protected mode, and the watchdog device central processing unit that directly resets can cause loss of data, operating system to damage, and interrupts the task of not meeting accident.
[summary of the invention]
Technical matters to be solved by this invention is to provide a kind of computer watchdog device and method of work thereof, interrupt to the central processing unit application earlier, when can not get responding, interruption sends the reseting signal reset central processing unit again, avoid loss of data, operating system to damage, and interrupt the task of not meeting accident.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is: a kind of computer watchdog device is provided, it comprises central processing unit and one-level watchdog circuit, described computer watchdog device also comprises the secondary watchdog circuit, described secondary watchdog circuit is connected with described one-level watchdog circuit and described central processing unit, and central processing unit directly resets behind the buffering one-level watchdog circuit generation clock spill over.
More specifically, described computer watchdog device comprises that also interruption produces circuit, described interruption produces circuit and is connected with described one-level watchdog circuit and interruption generation circuit, and the clock spill over generation interrupt request singal that receives the one-level watchdog circuit is transferred to central processing unit and handles.
More specifically, it is programmable circuit that described interruption produces circuit, interrupt request singal that can the generating routine appointment.
More specifically, described one-level watchdog circuit and secondary watchdog circuit are shared an initial value register.
More specifically, described one-level watchdog circuit and secondary watchdog circuit have separately independently initial value register.
The present invention also provides a kind of method of work of computer watchdog device, may further comprise the steps:
Step 1: when the one-level watchdog circuit count down to designated value,, just change step 2 over to if central processing unit is not given the one-level watchdog circuit value of setting;
Step 2: one-level watchdog circuit meter produces the clock spill over to the secondary watchdog circuit;
Step 3: when the secondary watchdog circuit count down to designated value, if central processing unit is provided with count value for the secondary watchdog circuit, then the secondary watchdog circuit changed step 4 over to;
Step 4: the secondary watchdog circuit produces the clock spill over and is transferred to central processing unit, and central processing unit resets.
More specifically, comprise also that in step 1 the one-level watchdog circuit count down to designated value before, central processing unit is the one-level watchdog circuit value of setting, then the one-level watchdog circuit step of restarting to count.
More specifically, comprise also that in step 2 the one-level watchdog circuit is transferred to interruption with the clock spill over and produces circuit, interrupt producing circuit and will interrupt producing the step that signal is transferred to central processing unit.
More specifically, comprise also that in step 3 central processing unit is provided with count value for the one-level watchdog circuit, then the secondary watchdog circuit stops counting, the step that the one-level watchdog circuit restarts to count.
Beneficial effect of the present invention is: increased the secondary watchdog circuit in the computer watchdog device of the present invention and interrupted producing circuit, the one-level watchdog circuit is produced circuit with secondary watchdog circuit and interruption to be connected, the buffering one-level watchdog device central processing unit that directly resets just sends reset signal to central processing unit, solve computer watchdog device loss of data and the operating system that central processing unit causes that directly resets and damaged, and interrupted the problem of the task of not meeting accident.
[description of drawings]
Fig. 1 is the synoptic diagram of computer watchdog device of the present invention.
Fig. 2 is a computer watchdog device method of work process flow diagram of the present invention.
[embodiment]
See also Fig. 1, computer watchdog device of the present invention comprises central processing unit 101, one-level watchdog circuit 102, secondary watchdog circuit 103 and interrupts producing circuit 104.Described central processing unit 101 is connected with described one-level watchdog circuit 102 and described secondary watchdog circuit 103 and carries out the count value setting, described one-level watchdog circuit 102 produces circuit 104 with described secondary watchdog circuit 103 and described interruption and is connected the transmission clock spill over, described secondary watchdog circuit 103 and interruption produce circuit 104 and are connected with central processing unit 101, and generation reset signal and interrupt request singal are transferred to central processing unit 101 and handle.
101 pairs of one-level watchdog circuits 102 of described central processing unit and secondary watchdog circuit 103 are provided with count value, the periodic at the appointed time interior order of counting again that described one-level watchdog circuit 102 is sent.Described one-level watchdog circuit 102 comprises a counter, and the order that receives described central processing unit 101 is counted.When accident appears in described central processing unit 101, one-level watchdog circuit 102 is not sent counting order again, produce the clock spill over when counting down to designated value and be transferred to secondary watchdog circuit 103 and interrupt generation circuit 104.The clock spill over that described secondary watchdog circuit 103 receives 102 transmission of one-level watchdog circuit begins counting, and count down to designated value, sends reset signal to central processing unit 101.Described one-level watchdog circuit 102 and secondary watchdog circuit 103 shared initial value register or independently initial value register arranged separately.It is programmable circuits that described interruption produces circuit 104, and when receiving the clock spill over of secondary watchdog circuit 103 transmission, the interrupt request singal of generating routine appointment is transferred to central processing unit 101.
Be appreciated that described computer watchdog circuit, be a kind of based on the counter principle, be used to improve the device of computer reliability.The computer watchdog circuit is counted its clock internal source, and central processing unit 101 is periodically at the appointed time interior to send the order of counting again to the computer watchdog circuit, and the computer watchdog circuit does not reach designated value forever.When accident appearred in computing machine, central processing unit 101 did not send counting order again to the computer watchdog circuit, when then the computer watchdog circuit count is to designated value, send the clock spill over, cause central processing unit 101 to reset, restart, avoid computing machine to be in unexpected state always.
The principle of work of computer watchdog device of the present invention is as follows:
When 101 pairs of one-level watchdog circuits 102 of central processing unit and secondary watchdog circuit 103 are provided with count value, have only one-level watchdog circuit 102 to begin counting, one-level watchdog circuit 102 clock spill in counting process is invalid, and secondary watchdog circuit 103 can not begin counting.When one-level watchdog circuit 102 count down to designated value, output clock spill over, send look-at-me to central processing unit 101 when interrupt producing circuit 104 and receiving the clock spill over of one-level watchdog circuit 102, secondary watchdog circuit 103 begins counting simultaneously, when central processing unit 101 responses are interrupted, again to one-level watchdog circuit 101 or/and secondary watchdog circuit 103 is provided with count value, one-level watchdog circuit 102 or secondary watchdog circuit 103 restart counting, and central processing unit 101 immediately can not reset; Only when central processing unit 101 can not respond interruption, secondary watchdog circuit 103 just can count down to designated value, sends reset signal to central processing unit 101.
The method of work of computer watchdog device of the present invention may further comprise the steps:
Step 1: central processing unit 101 is provided with count value for one-level watchdog circuit 102 and secondary watchdog circuit 103;
Step 2: when one-level watchdog circuit 102 count down to designated value, if central processing unit 101 is one-level watchdog circuit 102 values of setting, then one-level watchdog circuit 102 restarted counting, repeating step 2; If central processing unit 101 is not given one-level watchdog circuit 102 values of setting, just change step 3 over to;
Step 3: one-level watchdog circuit 102 count down to designated value, produces the clock spill over to interrupting producing circuit 104 and secondary watchdog circuit 103;
Step 4: interrupt producing circuit 104 and send look-at-me to central processing unit 101, secondary watchdog circuit 103 begins counting simultaneously; When secondary watchdog circuit 103 count down to designated value, if central processing unit 101 is provided with count value for one-level watchdog circuit 102, then secondary watchdog circuit 103 stopped counting, and one-level watchdog circuit 102 restarts counting, gets back to step 2; If central processing unit 101 is provided with count value for secondary watchdog circuit 103, then secondary watchdog circuit 103 restarts counting; If reset count value for one-level watchdog circuit 102 and secondary watchdog circuit 103, then enter step 5;
Step 5: secondary watchdog circuit 103 count down to designated value, produces the clock spill over to central processing unit 101, and central processing unit 101 resets.
Claims (10)
1. computer watchdog device, comprise central processing unit, it is characterized in that: described computer watchdog device comprises one-level watchdog circuit and secondary watchdog circuit, described one-level watchdog circuit generation clock spill over is transferred to described secondary watchdog circuit and begins counting, described secondary watchdog circuit is connected with described one-level watchdog circuit and described central processing unit, the buffering one-level watchdog circuit central processing unit that resets.
2. computer watchdog device as claimed in claim 1, it is characterized in that: described computer watchdog device comprises that also interruption produces circuit, described interruption produces circuit and is connected with described one-level watchdog circuit and central processing unit, and the clock spill over generation interrupt request singal that receives the one-level watchdog circuit is transferred to central processing unit and handles.
3. computer watchdog device as claimed in claim 1 is characterized in that: it is programmable circuit that described interruption produces circuit, interrupt request singal that can the generating routine appointment.
4. computer watchdog device as claimed in claim 1 is characterized in that: described one-level watchdog circuit and secondary watchdog circuit are shared an initial value register.
5. computer watchdog device as claimed in claim 1 is characterized in that: described one-level watchdog circuit and secondary watchdog circuit have separately independently initial value register.
6. the method for work of a computer watchdog device may further comprise the steps:
Step 1: when the one-level watchdog circuit count down to designated value,, just change step 2 over to if central processing unit is not given the one-level watchdog circuit value of setting;
Step 2: one-level watchdog circuit meter produces the clock spill over to the secondary watchdog circuit;
Step 3: when the secondary watchdog circuit count down to designated value, if central processing unit is provided with count value for one-level watchdog circuit or secondary watchdog circuit, then the secondary watchdog circuit changed step 4 over to;
Step 4: the secondary watchdog circuit produces the clock spill over and is transferred to central processing unit, and central processing unit resets.
7. the method for work of computer watchdog device as claimed in claim 6, it is characterized in that: before comprising also that in step 1 the one-level watchdog circuit count down to designated value, central processing unit is the one-level watchdog circuit value of setting, then the one-level watchdog circuit step of restarting to count.
8. the method for work of computer watchdog device as claimed in claim 6, it is characterized in that: comprise also that in step 2 the one-level watchdog circuit is transferred to interruption with the clock spill over and produces circuit, interrupt producing circuit and will interrupt producing the step that signal is transferred to central processing unit.
9. the method for work of computer watchdog device as claimed in claim 6, it is characterized in that: comprise also that in step 3 central processing unit is provided with count value for the one-level watchdog circuit, then the secondary watchdog circuit stops counting, the step that the one-level watchdog circuit restarts to count.
10. the method for work of computer watchdog device as claimed in claim 6 is characterized in that: comprise also that in step 3 central processing unit is provided with count value for the secondary watchdog circuit, then the secondary watchdog circuit step of restarting to count.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100611477A CN100495350C (en) | 2006-06-12 | 2006-06-12 | Computer watchdog device and its working method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100611477A CN100495350C (en) | 2006-06-12 | 2006-06-12 | Computer watchdog device and its working method |
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| CN101089823A true CN101089823A (en) | 2007-12-19 |
| CN100495350C CN100495350C (en) | 2009-06-03 |
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| CNB2006100611477A Active CN100495350C (en) | 2006-06-12 | 2006-06-12 | Computer watchdog device and its working method |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521098A (en) * | 2011-11-23 | 2012-06-27 | 中兴通讯股份有限公司 | Processing method and processing device for monitoring dead halt of CPU (Central Processing Unit) |
| CN102981918A (en) * | 2012-11-23 | 2013-03-20 | 西安坤蓝电子技术有限公司 | Watchdog circuit for realizing nesting and transmission method of dog feeding signal thereof |
| CN104050050A (en) * | 2013-03-13 | 2014-09-17 | 施耐德电器工业公司 | Watchdog control circuit and control method |
| CN105955870B (en) * | 2016-05-24 | 2018-10-19 | 北京广利核***工程有限公司 | A kind of monitoring system of FPGA operating statuses |
| CN111856991A (en) * | 2020-06-22 | 2020-10-30 | 北京遥测技术研究所 | Signal processing system and method with five-level protection on single event upset |
| CN112988104A (en) * | 2019-12-17 | 2021-06-18 | 广达电脑股份有限公司 | Audio output device and protection method thereof |
-
2006
- 2006-06-12 CN CNB2006100611477A patent/CN100495350C/en active Active
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102521098A (en) * | 2011-11-23 | 2012-06-27 | 中兴通讯股份有限公司 | Processing method and processing device for monitoring dead halt of CPU (Central Processing Unit) |
| CN102521098B (en) * | 2011-11-23 | 2014-12-10 | 中兴通讯股份有限公司 | Processing method and processing device for monitoring dead halt of CPU (Central Processing Unit) |
| CN102981918A (en) * | 2012-11-23 | 2013-03-20 | 西安坤蓝电子技术有限公司 | Watchdog circuit for realizing nesting and transmission method of dog feeding signal thereof |
| CN104050050A (en) * | 2013-03-13 | 2014-09-17 | 施耐德电器工业公司 | Watchdog control circuit and control method |
| CN105955870B (en) * | 2016-05-24 | 2018-10-19 | 北京广利核***工程有限公司 | A kind of monitoring system of FPGA operating statuses |
| CN112988104A (en) * | 2019-12-17 | 2021-06-18 | 广达电脑股份有限公司 | Audio output device and protection method thereof |
| CN111856991A (en) * | 2020-06-22 | 2020-10-30 | 北京遥测技术研究所 | Signal processing system and method with five-level protection on single event upset |
| CN111856991B (en) * | 2020-06-22 | 2021-11-16 | 北京遥测技术研究所 | Signal processing system and method with five-level protection on single event upset |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100495350C (en) | 2009-06-03 |
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