CN105161418B - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic device Download PDFInfo
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- CN105161418B CN105161418B CN201410260442.XA CN201410260442A CN105161418B CN 105161418 B CN105161418 B CN 105161418B CN 201410260442 A CN201410260442 A CN 201410260442A CN 105161418 B CN105161418 B CN 105161418B
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Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof and electronic device, the production method include: offer semiconductor substrate, is formed with fin structure in the semiconductor substrate；Deposition forms gate material layers in the semiconductor substrate and the fin structure, wherein the surface of the gate material layers is formed with multiple protrusions；Deposition forms sacrificial material layer in the gate material layers；The first chemical mechanical grinding is executed, is stopped on the top surface of the gate material layers, and the remaining sacrificial material layer for having part between adjacent protrusion；The second chemical mechanical grinding is executed, to completely remove the remaining sacrificial material layer.According to the method for the present invention, can effective monitoring grinding endpoint realize the preferably control to gate material layers thickness, while improving the flatness of grid material layer surface, avoid the appearance of step height, and then improve the performance and yield of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof and electronics
Device.
Background technique
The raising of performance of integrated circuits mainly improves its speed by constantly reducing the size of integrated circuit device
Come what is realized.Currently, due to pursue high device density, semi-conductor industry has advanced to a nanometer skill in high-performance and low cost
Art process node, especially when dimensions of semiconductor devices drops to 22nm or following, the challenge from manufacture and design aspect is
Through the development for resulting in three dimensional design such as FinFET (FinFET).
Relative to existing planar transistor, the FinFET is in the side such as channel control and reduction shallow ridges channel effect
Face has more superior performance, and planar gate is set to above the channel, and grid is surround in FinFET
The fin setting, therefore electrostatic can be controlled from three faces, the performance in terms of Electrostatic Control is also more prominent；Simultaneously again more
It is compact, the integrated level of device is improved, therefore in analog circuit (analog circuits) and static memory (SRAMs)
It is used widely.
However, many problems are faced in the manufacturing process of FinFET, for example, depositing in polysilicon gate material layer
Afterwards, it since the density degree of fin structure on substrate is different, causes the surface state of polysilicon gate material layer different, causes
During chemical mechanical grinding (Chemical Mechanical Polishing, abbreviation CMP) later, it is difficult to capture grinding
Terminal, and it is difficult the appearance of the rugged step problem of polysilicon gate material layer surface after control grinding.
Therefore, it is necessary to propose a kind of new production method, so as to solve the deficiencies in the prior art.
Summary of the invention
In view of the deficiencies of the prior art, the embodiment of the present invention one provides a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, is formed with fin structure in the semiconductor substrate；
Deposition forms gate material layers in the semiconductor substrate and the fin structure, wherein the gate material layers
Surface be formed with multiple protrusions；
Deposition forms sacrificial material layer in the gate material layers；
The first chemical mechanical grinding is executed, is stopped on the top surface of the gate material layers, and is remaining between adjacent protrusion
There is the sacrificial material layer of part；
The second chemical mechanical grinding is executed, to completely remove the remaining sacrificial material layer.
Further, the gate material layers are polysilicon layer.
Further, the material of the sacrificial material layer is oxide.
Further, the height for controlling the gate material layers in rarefaction is greater than the object height of scheduled gate material layers
With polishing wheel height and.
Further, the sacrificial material layer with a thickness of 2000~3500 angstroms.
Further, the sacrificial material layer is formed using chemical vapour deposition technique.
Further, first chemical mechanical grinding is carried out using with highly selective grinding slurry.
Further, the grinding using optical end point detection or current of electric end point determination to first chemical mechanical grinding
Terminal is detected.
Further, second chemical mechanical grinding is carried out using low selectivity grinding slurry.
Further, it is captured when the remaining sacrificial material layer is removed completely using optical end point detection method as institute
State the grinding endpoint of the second chemical mechanical grinding.
Further, when executing second chemical mechanical grinding, the excessive polishing processing of certain time can also be carried out,
So that the surface of the gate material layers is more flat.
Further, after second chemical mechanical grinding, further include the steps that executing third chemical mechanical grinding, institute
Stating third chemical mechanical grinding is chemical polishing process.
Further, fleet plough groove isolation structure is formed between the fin structure.
Second embodiment of the present invention provides a kind of semiconductor devices adopted and made with the aforedescribed process, the semiconductor devices tool
There are smooth gate material layers.
The embodiment of the present invention three provides a kind of electronic device comprising above-mentioned semiconductor devices.
In conclusion according to the method for the present invention, can effective monitoring grinding endpoint realize preferably to gate material layers
The control of thickness, while the flatness of grid material layer surface is improved, the appearance of step height is avoided, and then improve device
Performance and yield.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
The schematic cross section for the device that the step of Figure 1A -1D is successively implemented for the method for the prior art obtains respectively
Figure；
Fig. 2A -2E is the signal of the device obtained respectively the step of successively implementation according to the method for the embodiment of the present invention one
Property sectional view；
Fig. 3 is flow chart the step of successively implementation according to the method for the embodiment of the present invention one.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to illustrate skill of the invention
Art scheme.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention can also have
Other embodiments.
In the following, depositing post-chemical mechanical polishing process to the gate material layers of existing FinFET with reference to Figure 1A -1D
Implementation steps be briefly described.
First as shown in Figure 1A, semiconductor substrate 100 is provided, is formed with fin structure 101 on the semiconductor substrate,
Fleet plough groove isolation structure 102 is formed between the fin structure, in the fin structure 101 and fleet plough groove isolation structure
Deposition forms polysilicon gate material layer 103 on 102, and later, polysilicon gate material layer surface forms three kinds of different shapes
Looks:
Region A: this region corresponds to the smaller compact district of spacing of FinFET fin chip architecture, polysilicon gate material layer
Surface is gentle, and peak (height) is located at the top of fin structure.
Region B: this region corresponds to the bigger compact district of spacing of FinFET fin chip architecture, polysilicon gate material layer
Several island polysilicon peaks of the formation on surface, between fin and fleet plough groove isolation structure.
Region C: this region corresponds to the rarefaction of FinFET fin chip architecture, the polysilicon above fleet plough groove isolation structure
Gate material layers are easy to be influenced by dish-shaped (Dishing) effect of CMP.
As shown in Figure 1B, the first chemical mechanical grinding is executed, removal 103 surface of polysilicon gate material layer is outstanding multiple
Peak, to planarize polysilicon gate material layer surface.In this step, being added in lapping liquid has inhibitor 104, and inhibitor can
It prevents from grinding too fast.
As shown in Figure 1 C, the second chemical mechanical grinding is executed, polysilicon gate material layer 103 is further ground
Polishing, until being polished to target value.In this step, inhibitor 104 does not work in lapping liquid.
As shown in figure iD, the defects of carrying out chemical polishing, removing the scratch or recess on surface.
The surface of final polysilicon gate material layer has rugged step, and then influences the performance of device and good
Rate.
In consideration of it, the invention proposes a kind of new production methods, to solve the above problems.
Embodiment one
In the following, the step of successively implementing referring to Fig. 2A~2E to the present invention is described in detail.
Firstly, providing semiconductor substrate 200 with reference to Fig. 2A, the semiconductor substrate 200 can be the following material being previously mentioned
At least one of material: silicon (SSOI) is laminated on insulator, SiGe (S- is laminated on insulator for silicon, silicon-on-insulator (SOI)
SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..
Fin structure 201 is formed in the semiconductor substrate 200.Optionally, the fin 201 is silicon fin, can be adopted
The silicon fin is formed with method commonly used in the art.Illustratively, semiconductor material layer is formed on a semiconductor substrate first,
The semiconductor material layer can be sequentially depositing pad oxide with Si, SiGe, Ge or III-V material on semiconductor material layer
With pad nitride layer, patterned mask layer, such as photoresist mask layer are then formed on the semiconductor material layer, it is described
Photoresist mask layer defines width, length and position of the fin structure etc., is then with the photoresist mask layer
Then pad nitride layer, pad oxide and semiconductor material layer described in mask etch remove the photoresist and cover to form fin
Film layer, the method for removing the photoresist mask layer can be oxidative ashing method.It should be noted that the fin structure 201
Formation be only exemplary
Illustratively, three regions are divided into according to the density degree of fin structure 201, wherein fin spacing is the smallest close
Ji Qu is known as the area A, and the fin spacing biggish compact district that compares is known as the area B, and the big rarefaction of fin spacing is known as the area C.
It is formed with fleet plough groove isolation structure 202 between the fin structure 201, its forming process is briefly described are as follows:
Separation layer is filled between the fin structure, the material of separation layer can be oxide, nitride or nitrogen oxides etc..It is laggard
Row etch back process forms the fleet plough groove isolation structure that the fin structure is isolated with fin structure described in exposed portion.
Gate material layers 203 are formed in the disposed thereon of the fin structure 201 and fleet plough groove isolation structure 202.
The constituent material of gate material layers 203 includes polysilicon, metal, conductive metal nitride, conductive metal oxygen
One of compound and metal silicide are a variety of, wherein metal can be tungsten (W), nickel (Ni) or titanium (Ti)；Conductive metal
Nitride includes titanium nitride (TiN)；Conductive metal oxide includes yttrium oxide (IrO2)；Metal silicide includes titanium silicide
(TiSi).When selecting constituent material of the polysilicon as gate material layers, optional low-pressure chemical vapor phase deposition (LPCVD) technique
Gate material layers are formed, process conditions include: that reaction gas is silane (SiH4), and flow is 100~200sccm, preferably
150sccm；Temperature in reaction chamber is 700~750 DEG C；Pressure in reaction chamber is 250~350mTorr, preferably
300mTorr；The reaction gas can also include buffer gas, and the buffer gas is helium (He) or nitrogen (N2), stream
Amount is 5~20 liters/min (slm), preferably 8slm, 10slm or 15slm.Due to being uneven for semiconductor substrate structure, therefore
The surface of the gate material layers of formation is formed with multiple protrusion 203a.
When carrying out this step, the deposition within the area C rarefaction (for example, area is greater than 50 μm * 50 μm of pad area) is controlled
The height of gate material layers 203, guarantee the height of gate material layers be greater than the object heights of the predetermined gate material layers formed with
The sum of one polishing wheel height.
As shown in Figure 2 B, it deposits to form sacrificial material layer 204 on the surface of the gate material layers 203.
Illustratively, the material of the sacrificial material layer 204 can be oxide, nitride or nitrogen oxides etc..One
In a example, the material of the sacrificial material layer is oxide.Optionally, the sacrificial material layer with a thickness of 2000~3500
Angstrom.Can use chemical vapour deposition technique (CVD), plasma activated chemical vapour deposition (PECVD), it is possible to use for example sputter and
The methods of physical vapour deposition (PVD) (PVD) forms the sacrificial material layer 204.
As shown in Figure 2 C, the first chemical mechanical grinding is executed, is stopped on the top surface of gate material layers 203.
First chemical mechanical grinding is carried out using with highly selective grinding slurry.Illustratively, it can be selected sacrificial
Domestic animal material layer and gate material layers selection are than the grinding slurry greater than 4.In one example, gate material layers are polysilicon layers,
And sacrificial material layer is oxide skin(coating), then can be selected including CeO2 and/or SiO2 abrasive grains grinding slurry, and can pass through to
Increase the inhibitor for having grinding inhibiting effect to polysilicon in grinding slurry, Lai Shixian bigger selection ratio, the inhibitor can
For polyethylene glycol, the ethylene oxide adduct of acetylenic diol or alkoxylate straight-chain fatty alcohol etc..Due to highly selective,
Grinding rate to gate material layers 203 is far longer than to the grinding rate of sacrificial material layer 204.General CMP tool is matched
Standby end point determination device, to be detected as needed to the terminal of grinding.When material is ground to a preset target thickness
When degree or target material (target position), end point determination device is to issue the signal for stopping grinding.In an example, using light
It learns end point determination or current of electric end point determination detects the grinding endpoint of first chemical mechanical grinding.
Since 203 surface of gate material layers is uneven, after the first chemical mechanical grinding stops, in gate material layers
It there remains the sacrificial material layer 204 of part between adjacent protrusion 203a on 203 surface.
As shown in Figure 2 D, the second chemical mechanical grinding is executed, to completely remove remaining sacrificial material layer.
The second chemical mechanical grinding is carried out, to completely remove remaining sacrificial material layer.Preferably, it is ground using low selectivity
Defibrination material carries out the second chemical mechanical grinding.The grinding slurry has basic phase to remaining sacrificial material layer and gate material layers
Same grinding rate.Optionally, the low selectivity grinding slurry includes pyrogenic silica, water, potassium hydroxide etc..One
In a example, gate material layers are polysilicon layers, and sacrificial material layer is oxide skin(coating), then can reach by adjusting dilution ratio
To the 1:1 grinding rate of oxide and polysilicon.Using the grinding slurry of low selectivity can make the second chemical mechanical grinding it
203 surface of gate material layers afterwards is very flat.Illustratively, remaining expendable material is captured using optical end point detection method
Grinding endpoint when layer is removed completely as the second chemical mechanical grinding.Optionally, the excessive of certain time can also be carried out
(over polish, OP) processing is polished, so that the surface of gate material layers 203 is more flat.
As shown in Figure 2 E, third chemical mechanical grinding is executed, to improve defect existing for 203 surface of gate material layers.
The third chemical mechanical grinding is chemical polishing process, passes through the chemical component and grid material in grinding slurry
Layer 203 occur corrosion etc. chemical reaction, reduce surface roughness, improve the scratch as caused by the grinding of fast speed early period,
The defects of slight step.In one example, grinding slurry includes pyrogenic silica, water, potassium hydroxide etc., can be passed through
It adjusts dilution ratio and realizes the third chemical mechanical grinding.
In conclusion according to the method for the present invention, can effective monitoring grinding endpoint realize preferably to gate material layers
The control of thickness, while the flatness of grid material layer surface is improved, the appearance of step height is avoided, and then improve device
Performance and yield.
Fig. 3 is the flow chart for the step of method is successively implemented in the embodiment of the present invention one, to schematically illustrate entire technique mistake
Journey includes the following steps:
In step 301, semiconductor substrate is provided, is formed with fin structure in the semiconductor substrate；
In step 302, deposition forms gate material layers in the semiconductor substrate and the fin structure, wherein institute
The surface for stating gate material layers is formed with multiple protrusions；
In step 303, deposition forms sacrificial material layer in the gate material layers；
In step 304, the first chemical mechanical grinding is executed, is stopped on the top surface of the gate material layers, and in phase
The remaining sacrificial material layer for having part between adjacent protrusion；
In step 305, the second chemical mechanical grinding is executed, to completely remove the remaining sacrificial material layer；
Within step 306, third chemical mechanical grinding is executed.
Embodiment two
The present invention also provides a kind of semiconductor devices made of method in embodiment one, wherein the semiconductor device
Part has smooth gate material layers.
Gate material layers are smooth in the semiconductor devices that the method is prepared through the invention, in compact district and sparse
Surface height difference is not present in Qu Jun, therefore has excellent performance and yield.
Embodiment three
In addition the present invention also provides a kind of electronic device comprising semiconductor devices above-mentioned.
Since the semiconductor devices for including has higher yield and performance, which is equally had the above advantages.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, are also possible to have
The intermediate products of above-mentioned semiconductor device, such as: the cell phone mainboard etc. with the integrated circuit.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (15)
1. a kind of production method of semiconductor devices, comprising:
Semiconductor substrate is provided, fin structure is formed in the semiconductor substrate, according to the density degree of the fin structure
It is divided into three regions, wherein the smallest compact district of fin structure spacing and the fin structure spacing compare biggish
Compact district and the big rarefaction of the fin structure spacing；
Deposition forms gate material layers in the semiconductor substrate and the fin structure, wherein the table of the gate material layers
Face compares biggish compact district and described sparse in the smallest compact district of the fin structure spacing, the fin structure spacing
Area is each formed with multiple protrusions；
Deposition forms sacrificial material layer in the gate material layers；
Execute the first chemical mechanical grinding, stop on the top surface of the gate material layers, and the fin structure spacing most
Small compact district, the fin structure spacing residue between biggish compact district and the adjacent protrusion of the rarefaction that compares have portion
The sacrificial material layer divided, wherein be greater than the grinding to the gate material layers to the grinding rate of the sacrificial material layer
Rate；
The second chemical mechanical grinding is executed, to completely remove the remaining sacrificial material layer, wherein second chemical machinery
Grinding slurry used in grinding is to the remaining sacrificial material layer and gate material layers grinding rate having the same.
2. the method according to claim 1, wherein the gate material layers are polysilicon layer.
3. the method according to claim 1, wherein the material of the sacrificial material layer is oxide.
4. the method according to claim 1, wherein the height of the gate material layers is greater than in control rarefaction
The object height of scheduled gate material layers and polishing wheel height and.
5. the method according to claim 1, wherein the sacrificial material layer with a thickness of 2000~3500 angstroms.
6. the method according to claim 1, wherein forming the expendable material using chemical vapour deposition technique
Layer.
7. the method according to claim 1, wherein using having highly selective grinding slurry to carry out described the
One chemical mechanical grinding.
8. the method according to claim 1, wherein using optical end point detection or current of electric end point determination pair
The grinding endpoint of first chemical mechanical grinding is detected.
9. the method according to claim 1, wherein carrying out second chemistry using low selectivity grinding slurry
Mechanical lapping.
10. the method according to claim 1, wherein being captured using optical end point detection method remaining described
Grinding endpoint when sacrificial material layer is removed completely as second chemical mechanical grinding.
11. the method according to claim 1, wherein also being carried out when executing second chemical mechanical grinding
The excessive polishing of certain time is handled, so that the surface of the gate material layers is more flat.
12. the method according to claim 1, wherein further including holding after second chemical mechanical grinding
The step of row third chemical mechanical grinding, the third chemical mechanical grinding are chemical polishing process.
13. the method according to claim 1, wherein being formed with shallow trench isolation between the fin structure
Structure.
14. a kind of semiconductor devices made of method of any of claims 1-13, which is characterized in that described
Semiconductor devices has smooth gate material layers.
15. a kind of electronic device comprising semiconductor devices described in claim 14.
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| CN105957818B (en) * | 2016-05-17 | 2018-08-24 | 上海华力微电子有限公司 | Chemical mechanical milling tech model calibration verifies film thickness introducing method in flow |
| KR102486477B1 (en) * | 2016-05-31 | 2023-01-06 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| CN108228943B (en) * | 2016-12-21 | 2021-02-12 | 中国科学院微电子研究所 | CMP (chemical mechanical polishing) process modeling method of FinFET (Fin field effect transistor) device |
| CN109987575A (en) * | 2017-12-29 | 2019-07-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of MEMS device and preparation method, electronic device |
| CN111554574B (en) * | 2020-05-19 | 2023-03-21 | 中国科学院微电子研究所 | Planarization method, semiconductor device and manufacturing method thereof |
| CN114038755A (en) * | 2021-10-25 | 2022-02-11 | 上海华力集成电路制造有限公司 | Etching method |
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| US6756643B1 (en) * | 2003-06-12 | 2004-06-29 | Advanced Micro Devices, Inc. | Dual silicon layer for chemical mechanical polishing planarization |
| CN102543702A (en) * | 2010-12-23 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Formation method of metal gate |
| CN103854966A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
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| US6756643B1 (en) * | 2003-06-12 | 2004-06-29 | Advanced Micro Devices, Inc. | Dual silicon layer for chemical mechanical polishing planarization |
| CN102543702A (en) * | 2010-12-23 | 2012-07-04 | 中芯国际集成电路制造(上海)有限公司 | Formation method of metal gate |
| CN103854966A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | Planarization processing method |
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